Claims
- 1. A method of manufacturing a resistive semiconductor memory device, comprising:
providing a semiconductor workpiece; forming an insulating layer over the workpiece; defining a pattern for a plurality of alignment marks and a pattern for a plurality of conductive lines within the insulating layer; filling the alignment mark and conductive line patterns with a conductive material to form conductive lines; forming a masking layer over the conductive lines; and removing at least a portion of the conductive material from the alignment mark pattern, wherein the alignment marks may be used for alignment of subsequent layers of the resistive semiconductor memory device.
- 2. The method according to claim 1, wherein filling the alignment mark and conductive line patterns comprises:
depositing a conductive material over the workpiece to fill the alignment mark and conductive line patterns; and using a chemical-mechanical polish process to remove excess conductive material from a top surface of the insulating layer.
- 3. The method according to claim 1, wherein forming the masking layer comprises:
depositing a masking material over the conductive lines and alignment mark pattern; patterning the masking material; and removing the masking material from over the alignment mark pattern, leaving masking material residing over the conductive lines.
- 4. The method according to claim 3, wherein the masking material comprises a resist.
- 5. The method according to claim 3, wherein the masking material comprises a nitride.
- 6. The method according to claim 5, wherein the masking material comprises tantalum nitride or silicon nitride.
- 7. The method according to claim 5, further comprising:
depositing a resist over the masking layer, after depositing the masking material; and using the resist to pattern the masking layer.
- 8. The method according to claim 1, wherein depositing a conductive material comprises depositing a material including copper.
- 9. The method according to claim 8, further comprising depositing a liner, before depositing the conductive material.
- 10. The method according to claim 1, further comprising removing the masking layer from over the conductive lines.
- 11. The method according to claim 10, wherein the resistive semiconductor memory device comprises a magnetic random access memory (MRAM), further comprising:
depositing a magnetic stack layer over the insulating layer, conductive lines, and alignment marks; and patterning the magnetic stack layer to form a magnetic tunnel junction (MTJ) over at least one of the conductive lines, using the alignment marks to align the MTJ to the conductive line.
- 12. The method according to claim 1, wherein removing at least a portion of the conductive material from the alignment mark pattern comprises removing all of the conductive material from the alignment mark pattern.
- 13. A method of manufacturing a magnetic random access memory (MRAM) device, comprising:
providing a semiconductor workpiece; forming an insulating layer having a top surface over the workpiece; using a damascene process, patterning the insulating layer to form a plurality of alignment marks and a plurality of trenches for conductive lines; filling the alignment mark and conductive line patterns with a conductive material to form conductive lines; forming a masking layer over the conductive lines; removing at least a portion of the conductive material from the alignment mark pattern so that the alignment marks may be used for alignment of subsequent layers of the resistive semiconductor memory device; and removing the masking layer from over the conductive lines.
- 14. The method according to claim 13, wherein filling the alignment mark and conductive line patterns with a conductive material comprises:
depositing a conductive material over the insulating layer to fill the conductive line pattern and alignment marks, leaving excess conductive material disposed over at least the conductive line pattern; and chemically-mechanically polishing the insulating layer top surface to form the conductive lines, leaving conductive material residing within the alignment marks.
- 15. The method according to claim 13, wherein forming the masking layer comprises:
depositing a masking material over the conductive lines and alignment mark pattern; patterning the masking material; and removing the masking material from over the alignment mark pattern, leaving masking material residing over the conductive lines.
- 16. The method according to claim 15, wherein the masking material comprises a resist.
- 17. The method according to claim 15, wherein the masking material comprises a nitride.
- 18. The method according to claim 17, wherein the masking material comprises tantalum nitride or silicon nitride.
- 19. The method according to claim 15, further comprising:
depositing a resist over the masking layer, after depositing the masking material; and using the resist to pattern the masking layer.
- 20. The method according to claim 13, wherein depositing a conductive material comprises depositing a material including copper.
- 21. The method according to claim 20, further comprising depositing a liner, before depositing the conductive material.
- 22. The method according to claim 15, further comprising:
depositing a magnetic stack layer over the insulating layer, conductive lines, and alignment marks; and patterning the magnetic stack layer to form a magnetic tunnel junction (MTJ) over at least one of the conductive lines, using the alignment marks to align the MTJ to the conductive line.
- 23. The method according to claim 13, wherein removing at least a portion of the conductive material from the alignment mark pattern comprises removing all of the conductive material from the alignment mark pattern.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This invention is related to U.S. patent application Ser. No. 09/854,760, filed on May 14, 2001 by Xian J. Ning, entitled “Design of Lithography Alignment and Overlay Measurement Marks on CMP Finished Damascene Surface”, and U.S. patent application Ser. No. 10/161,867, filed on Jun. 3, 2001 by Xian J. Ning, entitled, “Lithography Alignment and Overlay Measurement Marks Formed by Resist Mask Blocking for MRAMs,” which are incorporated herein by reference.