Patent Grant
9178725
Not Applicable
Not Applicable
A portion of the material in this patent document is subject to copyright protection under the copyright laws of the United States and of other countries. The owner of the copyright rights has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the United States Patent and Trademark Office publicly available file or records, but otherwise reserves all copyright rights whatsoever. The copyright owner does not hereby waive any of its rights to have this patent document maintained in secrecy, including without limitation its rights pursuant to 37 C.F.R. §1.14.
1. Field of the Invention
This invention pertains generally to chip interconnection, and more particularly to a multi-band RF-interconnect transceiver as an advanced high-speed interface.
2. Description of Related Art
Chip-to-chip RF (radio-frequency) communication has become increasingly important to support exponential chip development advances with high pin counts and high complexity, that are increasingly difficult to distribute over traditional wired connections. In response to these interconnection problems, a number of solutions have been advanced for establishing RF chip-to-chip interconnections. One recent type of interconnection is directed at using a frequency-division multiple access interconnect (FDMA-I) transceiver for transmission line based multiple-band chip-to-chip communications.
However, although this interconnection mechanism provides a number of advantages, it suffers from power intensive phase and frequency synchronizations to demodulate binary phase-shift keying (BPSK) at the receiver, which increases transceiver architectural complexity, while requiring a large circuit area and a high overall power consumption. Consequently, this form of interconnection is not scalable and is not particularly well-suited for use in low power off-chip busses, such as those utilized within parallel memory busses.
Power and bandwidth requirements for dynamic random access memories (DRAMs) have continued becoming increasingly stringent. This is not surprising, in view of devices, such as mobile devices (e.g., smart phones) relying more intensively on graphics. The inputs and outputs (I/Os) of current double data rate (DDR) memory devices operate at approximately 5 Gb/s with a power efficiency of about 17.4 mW/Gb/s (i.e., 17.4 pJ/b). High-speed serial links provide an increased power efficiency of around 1 mW/Gb/s, which would be favorable for use in mobile memory I/O interfaces.
However, serial links typically suffer from the need of long initialization time, such as on the order of 1000 clock cycles, and do not meet mobile DRAM I/O requirements for fast switching between active, stand-by, self-refresh and power-down operating modes. In addition, traditional baseband-only (or BB-only) signaling tends to consume power super-linearly for extended bandwidth due to the need of power intensive pre-emphasis and equalization circuits.
Accordingly, the present invention provides apparatus and methods for overcoming wireless RF chip-to-chip interconnection issues with regard to power consumption, speed and circuit area, while being particularly well-suited for use in DRAM memory systems.
Multi-band signaling is described for providing inter-chip (chip-to-chip) and intra-chip interconnection. The invention provides numerous benefits and is particularly well-suited for use interconnecting with, or between, memory devices, such as from microprocessors, memory control circuits, or other memory modules and/or individual memory devices. The invention is configured for simultaneously communicating baseband and RF signals across a shared transmission line, preferably a differential transmission line. Various embodiments are described, which provide different numbers of channels, directions of transmission (e.g., baseband and RF signals in same direction, opposing directions, or combinations with multiple RF signal channels).
According to one simple case, a baseband transmitter connects as a common mode signal to a differential off-chip transmission line, while an RF band transmitter performs differential amplitude shift keying (ASK) of a carrier frequency over the same transmission line. Accordingly, multiple bands are simultaneously communicated between a CPU (or memory controller, DIMM, or other control circuit) and memory devices (e.g., memory modules, DIMMs, DRAM chips and so forth). In other embodiments, multiple RF bands are communicated over the same transmission line shared with the baseband signal.
The present invention provides a number of beneficial elements which can be implemented either separately or in any desired combination without departing from the present teachings.
Further aspects and embodiments of the invention will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the invention without placing limitations thereon.
The invention will be more fully understood by reference to the following drawings which are for illustrative purposes only:
The present invention provides apparatus and methods for increasing speed and efficiency for inter-chip (chip-to-chip) and intra-chip interconnections. Embodiments are described in which control circuits (e.g., processor, memory control chips, and so forth) are interconnected to memory chips (e.g., individual DRAM chips or modules), while other embodiments describe interconnecting between a memory control chip and memory chips within a dual in-line memory module (DIMM). It will also be appreciated that any of these inventive communications aspects can also be implemented between portions of a single chip as an intra-chip interconnection mechanism.
One aspect of the invention is an off-chip multi-band RF interconnect (OMRF-I) for increasing aggregate data rate, and reducing energy/bit for chip-to-chip communication, such as between a microprocessor, or other device accessing memory, such as a memory controller, and DRAM memory devices. By sharing the same physical transmission line between the traditional baseband and multiple (by a factor of N) RF-bands to provide an ultra-high speed advanced memory I/O bus.
By way of example, and not of limitation, one embodiment of the invention provides a technique based on OMRF-I with an amplitude shift keying (ASK) (de)modulation scheme with novel pseudo-differential signal mixing utilized for off-chip ultra-high speed wire-line communications. More particularly, an aspect of the invention utilizes OMRF-I transceiver architecture to provide an ultra-high data rate parallel memory interface.
An interconnection is shown in the figure between a transmitting chip 12 and receiving chip 14 through off-chip transmission lines 16. RF (DIN2) and baseband (DIN1) inputs are received 18, 20 into buffers 22, 24 and connected to respective transformers 28, 30. It should be appreciated that as the loading of the baseband output is typically very high (e.g., received by numerous chip inputs), a cascade or multiple buffers are depicted for driving the baseband output. The transformer for the RF band is driven by a voltage controlled oscillator (VCO) creating a carrier frequency. The RF band data stream is shown for switching on and off the transformer portion 29 coupled to the baseband transformer. Thus, the RF band is differentially coupled through the upper portion 29 of transformer 30 into off-chip transmission line 16, exemplified as a 5 cm transmission line.
On the receiver side, a transformer 34 is shown coupled to buffers 36 whose output (DOUT1) is a baseband signal 38. One winding of transformer 36 is shown coupled to a mixer 32 generating an RF output to buffers 40 having output (DOUT2) 42 in the RF band.
It should be appreciated that the different functions within this circuit, and the other circuits shown and described herein, can be implemented with numerous variations, as will be known to one of ordinary skill in the art, without departing from the teachings of the invention.
The BB transmitter (BBTX) 54 circuit comprises a digital section 58 with output from the on-die CMOS process variation detector logic 60 input to a digital transmitter impedance control 62 which detects process variations and feeds back corner information to an impedance control calibrator which corrects for the process variation. A low common mode push-pull output driver is shown with amplifier 64 outputting to a pre-driver 66 having a pair of complementary transistors at the source and sink, and another transistor in the source and sink of the pre-driver gated by the digital impedance control circuit 62. Output from pre-driver 66 is directed through a main transmit driver gating a series of pull-up 68 and pull-down 70 transistors, between each pair of which are a resistive divider network 72, with signal 73 (shown as connector AA) being output to the output transformer 89, seen here on a portion of the RF transmitter 52. It will be noted that the resistive dividers operate to control output impedance to overcome process variation, while providing a single BB TX output. The n-bit digitally calibrated BB output driver can overcome the on-chip process variation and reduce the impedance mismatch of active devices and the characteristic mismatch of off-chip transmission line (i.e., micro-strip on printed circuit board, PCB).
The RF transmitter (RFTX) circuit consists of an LC tank VCO having an oscillator with current source 74 and transistors 76a, 76b, capacitor 78 and inductors within on-chip transformer 80. The VCO generates an RF carrier (LO=20 GHz) and is inductively coupled to the ASK modulator section through 2:1 ratio on-chip transformer. The ASK modulator comprises a current source 82, first transistors 84a, 84b gated by transformer 80, second transistors 86a, 86b gated by DIN2 87, and third transistor 88 also gated by DIN2. Clearly, the transistors 86a, 86b and 88 operate to modulate the signal from transistors 84a, 84b, prior to receipt by transformer 89 and output through off-chip transmission line (TL) 56. It will be noted that the input data stream (DIN2) is up-converted with an RF carrier by current mode logic (CML) ASK NMOS switches and then the frequency selective transformer transmits the modulated signal into the TL by inductive coupling.
This dual RF/BB transmitter can transmit the two-level baseband signal and the ASK modulated RF signal simultaneously and achieve beneficial signal integrity against severe impedance discontinuity of the off-chip multi-drop memory bus. Unlike circuits utilizing a BPSK (de)modulation scheme, the present ASK RF transceiver eliminates the need of carrier regeneration at the receiver (i.e., quadrature voltage controlled oscillator (QVCO)) for demodulating binary phase signals (I/Q, 0/90 degree), which automatically eliminates process-induced carrier (re)generation variations between the TX and RX.
The band-selection transformer is designed to reject the baseband signal and the pseudo-differential mixer is designed to amplify the incoming RF signal. In contrast to this, the use of conventional single-ended passive mixers suffer from substantial signal losses in microwave frequencies which are sensitive to supply noise coupling. In contrast, the pseudo-differential active mixer of the present invention amplifies and down-converts the modulated RF carriers by feeding ASK modulated signals to differential gates and drains. This active differential-signal mixing scheme with subsequent differential amplifier generates differential outputs to the baseband output driver. Consequently, ultra wide bandwidth with enhanced RF signaling and compact area is achieved by eliminating inductors in the low-noise amplifier (LNA) and eliminating phase/frequency locked loops (PLL and FLL) completely.
The OMRF-I interconnection circuits were fabricated in 65 nm CMOS technology to demonstrate simultaneous and reconfigurable multi-chip access capability.
This invention is compatible with existing fabrication processes, as demonstrated by the embodiments described being realized in a 65 nm commercial CMOS process. The dual-band transceiver can be inserted between a microprocessor (or a memory controller, or other control circuit) and DRAMs, such as based on a DDR memory interface platform.
Potential advantages of the above aspects of the present invention include, but are not limited to: (1) ultra-high data rate, (2) overall power reduction, (3) Pad/pin/die/package size reductions, (4) increased signal integrity, (5) reconfigurable data communication, and (6) scalability.
The ultra-high data rate (1) is achieved in response to increasing aggregate data rate by a factor of N for chip-to-chip communications. The overall power reduction (2) is achieved in response to reducing the number of parallel high-speed channels by using simultaneous multi-channel data transactions through a shared off-chip transmission line to achieve overall cost reductions. The reductions in size and pads/pins (3) is achieved by reducing the number of data, address and command channels. The increased signal integrity (4) is provided in response to reducing noise sources (e.g., channel crosstalk) by reducing the number of parallel high-speed PCB lines, and power supply noise by reducing overall memory I/O interface power consumption. The configurability (5) of this data communication system is achieved as simultaneous multi-band data communications are enabled between a microprocessor and memories by shared off-chip transmission lines in contrast to use of conventional fixed chip-to-chip communication. The scalability (6) benefits are achieved because as CMOS technology continues to scale, the scalable OMRF-I transceiver can boost data rates of next generation DDR interfaces by inserting more RF bands above the baseband.
This aspect of the invention is advantageous because it offers scalable and CMOS compatible solutions to Double Data Rate (DDR) memory products, including state-of-the-art DDR3, next generation DDR4 prototypes, ultra high speed GDDR5 memories, next generation GDDR6, and other memory device technologies. Use of current state-of-the-art DDR I/O interfaces toward achieving 10 Gb/s/pin data rate of multipoint (or multi-drop) memory busses, would result in high operating power caused by pre-emphasis and equalization in transceivers, while lowering production yield caused by dramatically increased noises from crosstalk and power supplies of parallel bus. The present invention potentially alleviates all of these issues with an energy efficient solution.
One aspect of the present invention increases aggregate data rate by a factor of N while reducing energy-per-bit of an off-chip memory interface between a microprocessor, or other circuit such as a memory controller, and DRAMs by sharing the same physical transmission line between the traditional baseband and multiple RF-bands (N RF bands) within an ultra-high speed advanced memory I/O bus.
By way of example, and not of limitation, an embodiment of a dual (base+RF)-band interconnect (DBI) is described which enables a high throughput data rate with low power consumption operation in a DRAM I/O interface, such as in a portable DRAM based device. Unlike conventional baseband (BB) only signaling, the inventive DBI signaling utilizes both BB and RF bands for simultaneous dual data stream communications, but shares the common transmission line (T-Line). Instead of limiting the baseband operation within its linear-power-consumption region versus bandwidth, the interface bandwidth can be doubled by using DBI while still maintaining a linear power-consumption versus bandwidth curve for each of the dual bands.
Additionally, forwarded clocking is preferably incorporated within the source synchronous circuit, whereby the transmitter (TX) and receiver (RX) are all synchronized without the need of additional clock data recovery circuits. The inclusion of forward clocking in the DBI circuit enables bidirectional data links, while only necessitating a small increase in overhead. It should be appreciated that a memory controller (or microprocessor) contains an on-chip internal clock generator, such as a delay-locked-loop (DLL) or phase-locked-loop (PLL). An example of the clock generator is a reference clock of the DLL which can be forwarded directly to the memory side coupled to the memory controller (or microprocessor). The memory can directly utilize this clock for sampling the read/write data without the need of incorporating an on-chip DLL or PLL on the memory side. In applying these links to DRAM I/O data (DO) and command/address (C/A), DRAM access time can be greatly reduced by requesting DRAM read/write-operations simultaneously. Consequently, bi-directional DRAM I/Os can be performed with a significantly higher aggregate data rate (e.g., up to 10 Gb/s) while benefiting from lower operating power (e.g., approximately 2.5 mW/Gb/s).
Core B is shown with transceiver 202 having RFTX and BBRX, while Core A is shown with transceiver 208 also having RFTX and BBRX. On the memory side, Rank B is shown with transceiver 210 with BBTX and RFRX, while Rank A is shown with transceiver 216 having BBTX and RFRX. Both of these transceivers are shown coupled to N differential transmission lines 182.
The RFTX 232 comprises an LC tank VCO 246 shown with current source 248, oscillator circuit 250 of cross coupled transistors, capacitance 252 and inductance within transformer 254. Output from the VCO is modulated in response to amplitude-shift keying (ASK) and a frequency-selective transformer. In RFTX, the VCO first generates RF carrier at f2 (i.e., 23 GHz) 240 and continuously modulates transistors M1 and M2, whose output is then switched in response to data stream D1(RF) 236 through transistors M3 and M4, within transistor modulator section 258 that is fed by current source 256, and which outputs through frequency selective transformer 260 to generate ASK communication inductively coupled into off-chip T-Line 244. In one example implementation a frequency selective transformer may comprise two inductors of the transformer coupled to each other in a narrow band.
The BBRX section 234 amplifies the incoming data stream D2(BB), from transformer 260 with center tap signal 262, using buffers 266, 268. Buffer/amplifier 266 is shown with a reference VTERM (Voltage Termination) input 264, and coupled to an on die termination (ODT) to set the common mode voltage at the transformer center tap and remove the impedance mismatch. The ODT circuit is shown with digital OCT control logic 269 coupled to a series of transistor pairs Q1a, Q1b, Q2a, Q2b, through Q15a, Q15b with source/drain resistor pairs R1a through R15b coupled respectively to VTERM and one amplifier input.
Consequently, the DBI circuit transmits and receives D1(RF) and D2(BB) data streams concurrently under both differential (RF-band) and common (BB) modes. It should be appreciated that any inter-band interference generated in response to the simultaneous transmission of the dual band streams can be suppressed utilizing spectral separation and the orthogonal property between the differential and common mode signaling.
The BBTX 274 receives the D2(BB) signal 278 by input buffer 326, the output of which is received, along with signals from digital OCD impedance control logic 328 by a pre-driver 330 of transistors 332, 334, 336, 338, 340 and 342 which outputs to a BB output driver. The on-chip driver (OCD) is based on impedance control logic to overcome impedance mismatch and reduce sensitivity to PVT variations. In the meantime, the BB output driver couples the data stream D2(BB) via the common mode (i.e., the center tap of the differential transformer) to the off-chip T-Line. By way of example the BB output stage is shown comprising a series of transistor-resistor push-pull pairs, exemplified as resistors 344a, 344b, 348a, 348b, and transistors 346a, 346b, 350a, 350b, continuing on to resistors 352a, 352b, and transistors 354a, 354b, with output connecting to the transformer 286 in
Since the RF-band in the DBI circuit can readily be applied to a high microwave frequency carrier to minimize inter-band interference, its signal bandwidth to carrier ratio becomes relatively small, whereby equalization is generally unnecessary. It should be appreciated that this dual (BB+RF) band circuit can be further extended to Base+Multiple-RF bands, wherein multiple data streams can be simultaneously transmitted through a shared memory I/O interface transmission line (T-Line), insofar as a multi-band coupling scheme is utilized. Furthermore, as the receiver mixer with differential input signals only senses amplitude of the incoming signal, frequency and phase synchronizations between RFTX and RX are not required. This greatly simplifies the overall memory I/O interface design. For the same reason, the bit error rate (BER) is expected to be less than that which is provided in response to the use of phase sensitive modulation schemes.
On the memory side
The dual-band transceiver can be inserted between microprocessor (or memory controller) and DRAMs to provide a DDR memory interface platform. It is seen that the fabricated DBI is particularly well-suited for this DRAM I/O interface, such as in portable devices, although it can be utilized to interface other chip devices which require high bandwidth interconnection. The example illustrates fabrication in a 65 nm CMOS commercial process, from which an aggregate data throughput of 8.4 Gb/s (FR4) and 10 Gb/s (Roger test boards) was obtained, with power consumptions of 21 mW and 25 mW, respectively. The bit-error-rates (BERs) for both of these test boards were measured at less than 1×10−15 by using 223−1 PRBS from the Agilent-70843C. The DBI exhibits the highest aggregate data throughput, best energy efficiency (−2.5 pJ/b) and smallest active die area. Table 6 compares DBI performance with that of previous memory devices.
Potential advantages of the above aspects of the present invention include, but are not limited to: (1) ultra-high data rate, (2) simultaneous and bi-directional mobile memory I/O interface, (3) reduced overall power consumption, (4) scalability, and (5) forward clocking for synchronous communication.
The ultra-high data rate (1) is achieved in response to increasing aggregate data rate by a factor of N for future mobile memory I/O interface. The simultaneous and bi-directional mobile memory I/O interface (2) operates in which DBI transceivers can reduce DRAM access time by requesting DRAM read/write operation concurrently. Overall power consumption is reduced (3) in response to the DBI circuit eliminating the need for power intensive pre-emphasis and equalization circuits. The DBI of this aspect of the invention is scalable (4) as it allows boosting data rate of next generation mobile memory I/O interface by inserting more RF bands above the baseband, and can be scaled to even high frequency operations. The forward clocking scheme (5) for the synchronous DBI communication, (a) eliminates the need for any phase (or delay) locked loop (PLL or DLL) on the memory side by simply buffering a forwarded clock to synchronize the DRAM TX, RX clocks; while it also (b) allows for quick DRAM power state transitions with low idle power consumption (on the DRAMs), which is suitable for ultra high speed memory I/O interfaces.
This aspect of the invention is advantageous because it offers scalable and CMOS compatible solutions to interfacing with ultra-high speed memory products, such as mobile memory systems. Toward achieving 10 Gb/s/pin data rate for multipoint (or multi-drop) memory busses, conventional state-of-the-art mobile memory I/O interfaces suffer from high operating power caused by pre-emphasis and equalization in transceivers, and slow DRAM power state transitions. The present invention overcomes these issues in an energy efficient solution.
This aspect of the invention describes a novel DIMM architecture with a multiband RF interface to provide high bandwidth, scalability, and low power.
Demand for off-chip bandwidth DRAM interconnections continue to grow as more memory cores are integrated onto a die. Traditional RC interconnects have numerous shortcomings and are thus insufficient to meet these demands. Emerging alternative interconnects, such as multiband radio frequency interconnect (MRF-I) described in previous sections, have the potential to provide sufficient bandwidth at a low power consumption to meet the demands of future multiple-core processors. This section details the benefits of using MRF-I for chip-to-DRAM communication in terms of higher throughput, low power, and better scalability to a many-DIMM DRAM system. An apparatus and method are described for reducing power consumption by approximately 60% over a traditional RC interconnect by using MRF-I. In addition, existing DIMM architectures are modified using MRF-I with MRF-DIMM according to the invention which increases throughput by 107% on average (up to 126%) in a 4-DIMM system and provides increased throughput per watt (by an average of 10%). A multiband tree DIMM architecture (MT-DIMM) is also taught that increases scalability, and which utilizes MRF-I in an inventive MT-DIMM that further increases throughput while maintaining low power consumption, and the ability to be scaled to an even larger number of DIMMs. Utilizing the DIMM tree architecture with MT-DIMMs increases throughput by 143% (up to 184%) on an 8-DIMM system with comparable throughput per watt. Scaling was demonstrated in scaling to 256 MT-DIMMs on a single channel with little degradation in throughput.
The “memory wall” problem, in which DRAM system performance has not been able to scale at the same rate as processor performance, has been an ever-increasing problem for micro-architects. This is further complicated with the emergence of chip multi-processors (CMPs). As scaling continues further with additional cores on a chip, a point is reached at which overall system performance cannot increase any further due to the limits of the DRAM system. For desktop and notebook systems, DRAM system performance is limited by DRAM bandwidth. For servers such as main memory database systems and so-called “RAMClouds”, which are required to access large amounts of data quickly, DRAM system performance is limited by both DRAM bandwidth and capacity. It has been indicated that with enough capacity, DRAM can be utilized as permanent storage for data, thus eliminating the need for a hard drive while improving throughput and latency for data intensive applications by 100-1000×. Although there have been numerous advances in DRAM bandwidth and capacity over the years, there are significant tradeoffs between bandwidth, capacity and power. The progression of conventional DDRx DIMMs to higher and higher data rates has come at the cost of reduced DRAM system capacity. In response to that, FB-DIMM was created toward providing a high bandwidth, high capacity DRAM system; however, this is achieved at the cost of high power consumption. FB-DIMMs rely on serial links between CPU (memory controller) and memory. However, the power consumption of the buffer is very high on a high capacity DRAM system. To overcome this problem, industry developed novel emerging LR-DIMMs with moderate power increase and the ability to be pushed to higher capacities (up to about 8 to 16 DIMMS at max. Although LR-DIMM can provide improvement over FB-DIMMs they still suffer from inclusion of a limited number of DIMMs. This limitation is particularly troublesome on some system, such as cloud systems, which require using up to 32 or more DIMMs on the channel for the desired ultra-high capacity level.
The present aspect of the invention is a promising solution for providing high bandwidth at low power within a multiband radio frequency interconnect (MRF-I) capable of simultaneous transmission of multiple data streams over a single shared medium. This technology has the capacity to provide significant increases in power efficiency over traditional RC interconnects at high data rates beyond 3 Gbps/pin. However, as existing DRAM technologies operate at much lower data rates where MRF-I is not as power efficient. DDR3-1600 operates at 1.6 Gbps/pin. Therefore, in order to apply MRF-I to existing DRAM technologies, the power efficiency of MRF-I at these lower data rates should be improved. Once MRF-I becomes sufficiently power efficient for use in existing DRAM technologies, it is possible to utilize MRF-I's ability for simultaneous transmission of multiple data streams over a single shared medium to create novel DRAM architectures for high bandwidth and lower power systems.
The following sections describe utilizing MRF-I to create novel DIMM architectures for high throughput, scalability, and low power. The inventive apparatus and methods improve energy per bit of MRF-I at lower data rates required for existing DRAM technologies while providing reduced energy per bit. MRF-I, as described in previous sections, provides a 60% energy per bit reduction achieved over traditional RC interconnects.
The following describes application of MRF-I to a conventional DDR3 DIMM to create a multiband radio frequency interconnect DIMM (MRF-DIMM). MRF-DIMM uses MRF-I to create multiple logical channels over a single physical channel. MRF-DIMM increases throughput by 107% on average (up to 126%) in a 4-DIMM system while increasing throughput/watt by an average of 10%. MRF-DIMM is particularly well-suited for the desktop and notebook markets, where high throughput and low power are important.
A DIMM tree architecture is described consisting of tree DIMMs (T-DIMMs). By arranging the DIMMs as a tree, the number of DIMMs grows exponentially with each level of latency that is added. The DIMM tree architecture allows a DRAM system to scale to much larger capacities without degradation in throughput, which is ideal for servers that need to access large amounts of data quickly. A DIMM tree architecture consisting of the inventive T-DIMMs is able to scale to 64 DIMMs without significant throughput degradation.
This section also describes application of MRF-I to the T-DIMMs, creating MRF-I tree DIMMs, referred to herein as multiband tree DIMMs (MT-DIMMs), for higher throughput, lower power, and higher scalability than T-DIMMs. A DIMM tree architecture using MT-DIMMs is able to increase throughput by 143% (up to 184%) on an 8-DIMM system while increasing throughput/watt by 4% on average, and scaling beyond 256 DIMMs.
Multiband RF-I provides high aggregate bandwidth and power saving over traditional RC interconnects. MRF-I is realized via transmission of electromagnetic waves through multiple carrier channels over a shared transmission line, rather than the transmission of a voltage signal through a single baseband over a wire. In MRF-I, carrier waves are continuously propagated along the transmission line, and data is generated through either the amplitude or phase modulation of the carrier wave. MRF-I can therefore provide simultaneous transmissions of multiple data streams over a shared physical transmission line to improve the aggregate bandwidth and data rates. It should be noted that each data stream is herein referred to as an RF band.
Advanced off-chip MRF-I described in previous sections uses ASK modulation with differential signaling, referred to as ASK MRF-I. Since ASK MRF-I uses differential signaling, it utilizes two lines to propagate a signal. Differential signaling can provide higher signal integrity, leading to the use of higher data rates and a higher number of RF bands per pin overall. Using more RF bands per pair of differential lines also leads to reduced pin counts compared to traditional RC interconnects. ASK MRF-I can support multiple DIMMs (e.g., at least four) on a multi-drop bus operating up to 4 Gbps per RF band with two bands per pin. Work is continuing to further increase the number of RF bands per pin.
The area of the transceivers, including pads, for 8-bit baseband and RF-I transceivers is shown in Table 1 for a 65 nm process technology. The individual transceiver size can be obtained by taking the “area” and dividing by “#transceivers.” In one aspect of the present invention, circuit area is reduced by fabricating the passive structures directly over the top of the digital logic circuits. Table 1 shows that as the number of RF bands per pin increases, the area shrinks significantly, and the number of pins is reduced.
While ASK RF-I as described in previous sections is very power efficient at high data rates, it is relatively inefficient at lower data rates required for existing DRAM technology, such as DDR3-1600 (1.6 Gbps). This section describes modifications to reduce power consumption at low data rates. The previously described ASK RF-I devices utilized one voltage-controlled oscillator (VCO) per pair of differential lines in order to produce the RF carrier.
Following is a brief overview of existing DIMM technologies in order to understand the tradeoffs of MRF-DIMM, T-DIMM, and MT-DIMM.
MRF-DIMM according to the present invention is an MRF-I based architecture designed to increase throughput, but without sacrificing power efficiency. An MRF-DIMM utilizes the capability of supporting multiple RF bands per pin of MRF-I to create multiple logical channels over a single physical channel. This allows an MRF-DIMM to reduce the number of DIMMs contending for a single logical channel, thereby increasing concurrency and throughput. MRF-DIMM provides high bandwidth at low power, which is ideal for desktop and notebook computing systems.
In a conventional DDRx SDRAM memory system using a multi-drop bus, as seen in
The DIMM tree architecture is designed to increase the capacity of a DRAM system without throughput degradation. The DIMM tree architecture creates a tree of DIMMs in order to grow the latency in response to the logarithmic growth in the number of DIMMs, instead of a steeper linear latency increase as the number of DIMMs increases. Accordingly, this architecture allows the memory system to readily scale to a many-DIMM DRAM system. This is accomplished by doubling the pin data rates and halving the number of pins for each DIMM-to-DIMM connection, which allows the support of two DIMM-to-DIMM interfaces on each DIMM without significant pin overhead. The DIMM tree architecture can be implemented without MRF-I, using tree DIMMs (T-DIMMs). However, in response to ongoing DRAM clock rate increases, T-DIMMs are able to support fewer and fewer DIMMs on a multi-drop bus. MRF-I does not share that shortcoming. Therefore, by adopting MRF-I additional improvements in power, throughput, and scalability of DIMMs can be achieved. The DIMM tree architecture is ideal for servers, which requires high capacity in addition to high bandwidth and low power.
It should be appreciated that the physical layout in
The operation of the inventive embodiment was evaluated using generated memory transaction traces from a benchmark suite (SPEC CPU 2006), with traces gathered using a dynamic instrumentation tool (called “Pin”), with a 2 MB 8-way set associative L2 cache model with 64B blocks taken from Simplescalar®. The traces were generated by warming up for 1 billion instructions before recording and then running for another 1 billion instructions while recording memory transactions. The traces were captured as input into a detailed memory system simulator, and several trace files mixed together in order to create a multiprogrammed CMP workload that stresses the DRAM system.
Table 3 shows six different mixes of standardized memory testing patterns utilized in evaluating the devices. The mixes are categorized by how much they stress the DRAM system, such as low, medium, and high. Parameters are shown in Table 4 that were utilized for the evaluation simulations. The simulation was modified to provide a per-rank transaction queue instead of a single per channel transaction queue, thereby allowing scheduling transactions from different ranks concurrently insofar as no DRAM timing conflicts arise. Per rank transaction queues were utilized in all the evaluations.
For DRAM chips on the LR-DIMMs, MRF-DIMMs, T-DIMMs, and MT-DIMMs, the timing and power parameters from the Micron® datasheets for DDR3-1600 were utilized as representative. For the DRAM chips on the FB-DIMM, information from the Micron datasheet for DDR2-800 were utilized. FB-DIMM only supports up to DDR2-800, and not DDR3. While the DRAM simulator utilized has a power model for the DRAM chips, it does not model interconnect power. Therefore, an interconnect power model was added to the simulator for baseband and RF-I which also includes transceiver power. The interconnect power numbers and structures not modeled in the simulator were obtained from a highly accurate circuit simulator.
In this section the throughput and power of a DIMM tree architecture using T-DIMMs and MT-DIMMs is compared to DRAM systems using DDR3-1600 LR-DIMMs and DDR2-800 FB-DIMMs. For each DRAM system, one rank per DIMM and 8 DIMMs in the system are assumed. The DIMM tree architectures are configured as quadrary (4-ary) trees (i.e., each DIMM has up to 4 children). The conventional devices are compared with MT-DIMMs using 1, 2, and 4 RF bands per pin.
In this section, the scalability of the DIMM tree architecture is explored versus FB-DIMM.
Referring to
So far these simulation results have only reflected the effect that the DRAM latency has on the throughput of the system. They have not reflected the additional system performance that may be gained by increased DRAM capacity, which results in a reduced number of disk accesses. Therefore, the results outlined have been very conservative. If the performance gains which arise from reduced disk accesses were factored in, the benefits of the inventive embodiments would be seen to be even more significant.
Table 5 sums up the latencies, throughput, and capacities of T-DIMM/MT-DIMM with 64 DIMMs against a hard drive and a solid state drive. It is assumed that each DIMM can hold 4 GB. Latency for T-DIMM/MT-DIMM is calculated as the time from the beginning of the first DRAM command for a read transaction sent from the memory controller until the data for that transaction is received at the memory controller. As can be seen, both T-DIMM and MT-DIMM dominate solid state drives and hard drives in terms of latency and throughput, but with a comparable amount of capacity.
DRAM systems are reaching a tipping point where technology is pushing the limits of traditional RC interconnects. Multiband RF-I (MRF-I) is a particularly well-suited candidate for replacing RC interconnect for interfacing DRAMs. MRF-I supports more concurrent logical channels, can operate at a higher frequency with lower power, and is fully compatible with CMOS technology. Evaluations have been shown in which MRF-I energy per bit was reduced by 60% over a traditional RC interconnect. MRF-DIMM was able to achieve an average of 107% and up to 126% improvement in throughput while still being as power efficient as LR-DIMM. For a DIMM tree architecture with MT-DIMMs, an average of 143% and up to 184% improvement was achieved in throughput while still being power efficient in an 8 DIMM system. MT-DIMM was also able to scale beyond 256 DIMMs on a single channel and improve throughput by 22% over an LR-DIMM system with just 8 DIMMs. By utilizing MRF-I for chip-to-DRAM communication in the inventive DIMM architectures, a clear benefit in terms of throughput, power, and scalability has been shown.
From the description herein it will be appreciated that the invention can be embodied in multiple ways without departing from the inventive concepts herein, including but not limited to the following embodiments:
1. An apparatus for memory interfacing, comprising: a baseband transmitter at a first frequency within a first integrated circuit configured for connection to a transmission line adapted for connection to at least a second integrated circuit; wherein said baseband transmitter is configured for outputting a baseband signal in response to receipt of a first data stream within said first integrated circuit; and at least one RF transmitter having a carrier at a second frequency which is amplitude shift keyed (ASK) and configured for connection to said transmission line; wherein multiple bands are simultaneously communicated from said first integrated circuit to at least said second integrated circuit.
2. The apparatus of embodiment 1, wherein said first integrated circuit comprises a microprocessor or memory controller configured for interfacing with said at least one second integrated circuit comprising memory devices.
3. The apparatus of embodiment 1, wherein said transmission lines comprise at least one differential pair of transmission lines within a shared parallel bus or point-to-point link.
4. The apparatus of embodiment 1, wherein said carrier of at least one RF transmitter is generated by one or more voltage controlled oscillators.
5. The apparatus of embodiment 1, wherein said at least one RF transmitter comprises multiple RF transmitters at a first integrated circuit; and wherein the carrier for these multiple RF transmitters is generated by a single voltage controlled oscillator.
6. The apparatus of embodiment 1, wherein said amplitude shift keying (ASK) is performed in response to switching the carrier on and off from connection to said transmission line.
7. The apparatus of embodiment 6, wherein said RF transmitter is transformer coupled to said transmission line.
8. The apparatus of embodiment 1, wherein said transmission line comprises a pair of transmission lines operating differentially as a single line.
9. The apparatus of embodiment 1, wherein said at least one baseband transmitter is configured with a multiple bit digitally calibrated baseband output which corrects for on-chip process variation and reduces impedance mismatch of active devices and characteristic mismatch of the transmission line.
10. The apparatus of embodiment 1, further comprising additional transmission lines coupled between said first integrated circuit and said second integrated circuit.
11. The apparatus of embodiment 1: wherein said at least one RF transmitter operates differentially on said transmission line, and said baseband transmitter operates in common mode on said transmission line; and wherein inter-band interference generated in response to simultaneous transmission of RF and baseband signals is suppressed utilizing spectral separation and orthogonal property between differential and common mode signaling.
12. The apparatus of embodiment 1, further comprising forward clocking in response to buffering a forwarded clock, wherein no phase locked loops (PLLs) or delay locked loops (DLLs) are required on one of said first integrated circuit or said second integrated circuit.
13. The apparatus of embodiment 1, wherein said chip-to-chip memory interfacing is performed within a memory module containing a plurality of dynamic random access memory (DRAM) devices.
14. The apparatus of embodiment 13, wherein said memory module comprises a dual in-line memory module (DIMM).
15. The apparatus of embodiment 14, further comprising a DIMM interface router (DIR) within a DIMM configured for receiving data, address, and control lines over a multiband interconnection along with other DIMM devices.
16. The apparatus of embodiment 14, further comprising a DIMM tree architecture in which each said RF transmitter is configured for transmitting multiple RF bands, and number of DIMMs increases exponentially as each new level of DIMMs and their associated latency are added.
17. An apparatus for memory interfacing, comprising: a baseband receiver of a first frequency within a second integrated circuit configured for connection to a transmission line adapted for connection to a first integrated circuit; wherein said baseband receiver is configured for outputting a digital baseband signal in response to receiving and converting a received baseband signal through said transmission line; and at least one RF receiver, configured for connection to said transmission line for receiving and converting an amplitude shift keyed (ASK) RF signal having a carrier at a second frequency to a digital RF band output; wherein multiple bands are simultaneously communicated from the first integrated circuit to at least said second integrated circuit.
18. The apparatus of embodiment 17, further comprising a band selective transformer for separating the baseband signal from the RF band signal.
19. The apparatus of embodiment 17, further comprising an active differential mixer circuit within said RF receiver for converting the ASK modulated RF signal back to an RF data signal.
20. A system for memory interfacing, comprising: a first integrated circuit device; a second integrated circuit device; a transmission line adapted for connection between said first integrated circuit device and said second integrated circuit device; a baseband transmitter at a first frequency within said first integrated circuit and a baseband receiver within said second integrated circuit, or said baseband transmitter at a first frequency within said second integrated circuit and a baseband receiver within said first integrated circuit; wherein said baseband transmitter is configured for outputting a baseband signal in response to receipt of a first data stream; and at least one RF transmitter within said first integrated circuit and/or said second integrated circuit having a carrier at a second frequency which is amplitude shift keyed (ASK) and configured for connection to said transmission line; wherein multiple bands are simultaneously communicated between said first integrated circuit and said second integrated circuit.
21. An apparatus for chip-to-chip memory interfacing, comprising: at least one baseband transmitter at a first frequency within a first integrated circuit configured for connection to an off-chip transmission line; wherein said at least one baseband transmitter is configured for outputting a baseband signal in response to receipt of a first data stream within said first integrated circuit; and at least one RF transmitter within a second integrated circuit coupled to said off-chip transmission line, and having a carrier at a second frequency modulated by amplitude shift keying (ASK) in response to receipt of a second data stream; wherein simultaneous bi-directional communication of said first data stream and said second data stream over multiple bands is performed between said first integrated circuit and said second integrated circuit.
22. The apparatus of embodiment 21, wherein said first integrated circuit comprises a microprocessor or memory controller configured for interfacing with said at least one second integrated circuit comprising memory devices, or said second integrated circuit comprises a microprocessor or memory controller configured for interfacing with said at least one first integrated circuit comprising memory devices.
23. The apparatus of embodiment 21, wherein said transmission lines comprise at least one differential pair of transmission lines within a shared parallel bus or point-to-point link.
24. The apparatus of embodiment 21, wherein said carrier of at least one RF transmitter is generated by one or more voltage controlled oscillators.
25. The apparatus of embodiment 21, wherein said at least one RF transmitter comprises multiple RF transmitters.
26. The apparatus of embodiment 25, wherein the carrier for said multiple RF transmitters is generated by a single voltage controlled oscillator coupled to said multiple RF transmitters.
27. The apparatus of embodiment 21, wherein said at least one RF transmitter is transformer coupled to said baseband transmitter and/or said baseband receiver, and to said off-chip transmission line.
28. The apparatus of embodiment 21, wherein said baseband transmitter is configured with a digitally calibrated baseband output which overcomes on-chip process variation and reduces impedance mismatch of active devices and characteristic mismatch to said off-chip transmission line.
29. The apparatus of embodiment 21: wherein said at least one RF transmitter operates differentially on said off-chip transmission line, and said baseband transmitter operates in common mode on said off-chip transmission line; and wherein inter-band interference generated in response to simultaneous transmission of RF and baseband signals is suppressed utilizing spectral separation and orthogonal property between differential and common mode signaling.
30. The apparatus of embodiment 21, further comprising: forward clocking, from said first integrated circuit to said second integrated circuit, or from said second integrated circuit to said first integrated circuit, in response to buffering a forwarded clock; wherein no phase locked loops (PLLs) or delay locked loops (DLLs) are required.
31. The apparatus of embodiment 21, wherein said chip-to-chip memory interfacing is performed within a memory module containing a plurality of dynamic random access memory (DRAM) devices.
32. The apparatus of embodiment 31, wherein said memory module comprises a dual in-line memory module (DIMM).
33. The apparatus of embodiment 32, further comprising a DIMM interface router (DIR) within a DIMM configured for receiving data, address, and control lines over a multiband interconnection along with other DIMM devices.
34. A system for chip-to-chip communication between integrated circuits, comprising: at least one baseband transmitter at a first frequency within a first integrated circuit configured for connection to a differential pair of off-chip transmission lines adapted for connection to a second integrated circuit; wherein said at least one baseband transmitter is configured for outputting a baseband signal in response to receipt of a first data stream within said first integrated circuit; and at least one RF transmitter, within said first integrated circuit or said second integrated circuit configured for amplitude shift keying (ASK) of a carrier at a second frequency which is coupled to said pair of off-chip transmission lines; wherein multiple bands are simultaneously communicated chip-to-chip between integrated circuits.
35. The system of embodiment 34, wherein said first integrated circuit comprises a microprocessor or memory controller configured for interfacing with said at least one second integrated circuit comprising memory devices, or said second integrated circuit comprises a microprocessor or memory controller configured for interfacing with said at least one first integrated circuit comprising memory devices.
36. The system of embodiment 34, wherein said carrier of at least one RF transmitter is generated by one or more voltage controlled oscillators.
37. The system of embodiment 34, wherein said at least one RF transmitter comprises multiple RF transmitters.
38. The system of embodiment 37, wherein the carrier for said multiple RF transmitters is generated by a single voltage controlled oscillator coupled to said multiple RF transmitters.
39. The system of embodiment 34, wherein said baseband transmitter is configured with a digitally calibrated baseband output which overcomes on-chip process variation and reduces impedance mismatch of active devices and characteristic mismatch to said off-chip transmission line.
40. An apparatus for chip-to-chip memory interfacing, comprising: a memory controller having multiple cores configured for communicating with multiple memory devices; a baseband receiver in each of said multiple cores in said memory controller is coupled to at least one of a plurality of differential transmission lines; and a plurality of RF transmitters, configured for amplitude shift keying (ASK) of a carrier generated from a voltage controlled oscillator shared between said plurality of RF transmitter, with each of said plurality of RF transmitters coupled to at least one of said plurality of differential transmission lines.
41. A memory module, comprising: an interface router having a multiband interconnection with simultaneous baseband and amplitude shift keyed RF band transmissions for receiving data and address information from outside of said memory module; and a plurality of memory devices within said memory module coupled to said interface router; wherein said address and data signals are received over the multiband combination of baseband and RF band and communicated with said plurality of memory chips.
42. The memory module of embodiment 41, further comprising a plurality of differential transmission lines coupled to said memory module over which said address and data information is communicated.
43. The memory module of embodiment 41, wherein command and/or control information is received over said baseband and RF band by said interface router.
44. The memory module of embodiment 41, wherein said memories comprise dynamic random access memory (DRAM) devices.
45. The memory module of embodiment 41, wherein said memory module comprises a dual in-line memory module (DIMM).
46. The memory module of embodiment 41, wherein said interface router is configured for transmitting multiple RF bands.
47. The memory module of embodiment 41, wherein said memory devices are coupled to said interface router with RC interconnects.
48. The memory module of embodiment 41, wherein said interface router comprises: a parent multiband RF transceiver configured for connection to a plurality of transmission line pairs over which said simultaneous baseband and amplitude shift keyed RF band transmissions are received; a router coupled to said parent and adapted with a plurality of data rate converters configured for RC interfacing with each of said plurality of memory devices; and a child multiband RF transceiver configured for connection to a plurality of transmission line pairs over which said simultaneous baseband and amplitude shift keyed RF band transmissions are transmitted to at least one additional memory module.
49. The memory module of embodiment 41, further comprising a buffer between said router and said child multiband RF transceiver for buffering memory signals being directed to at least one additional memory module.
50. The memory module of embodiment 41: wherein said memory module is configured for incorporation within a tree architecture having a plurality of device levels; wherein each level of memory module is configured for performing said simultaneous baseband and amplitude shift keyed RF band transmissions of data and addressing to a plurality of memory modules at a next level of said tree architecture; and wherein latency increases by one as each level in the tree architecture is added, while the number of memory modules contained in the tree architecture goes up exponentially.
Although the description above contains many details, these should not be construed as limiting the scope of the invention but as merely providing illustrations of some of the presently preferred embodiments of this invention. Therefore, it will be appreciated that the scope of the present invention fully encompasses other embodiments which may become obvious to those skilled in the art, and that the scope of the present invention is accordingly to be limited by nothing other than the appended claims, in which reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural and functional equivalents to the elements of the above-described preferred embodiment that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Moreover, it is not necessary for a device or method to address each and every problem sought to be solved by the present invention, for it to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. No claim element herein is to be construed under the provisions of 35 U.S.C. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for.”
(a) RF carrier frequency = 23 GHz
(b) Communication Types: Bi = Bidirectional, Sim = Simultaneous
(c) Existing Memory Device Types are described in the following papers.
This application is a 35 U.S.C. §111(a) continuation of PCT international application number PCT/US2012/02132 filed on Feb. 14, 2012, incorporated herein by reference in its entirety, which is a nonprovisional of U.S. provisional patent application Ser. No. 61/442,557 filed on Feb. 14, 2011, incorporated herein by reference in its entirety, a nonprovisional of U.S. provisional patent application Ser. No. 61/443,154 filed on Feb. 15, 2011, incorporated herein by reference in its entirety, and a nonprovisional of U.S. provisional patent application Ser. No. 61/53/732 filed on Aug. 1, 2011, incorporated herein by reference in its entirety. Priority is claimed to each of the foregoing applications. The above-referenced PCT international application was published as PCT International Publication No. WO 2012/112618 on Aug. 1, 2011, which publication is incorporated herein by reference in its entirety.
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| Number | Date | Country |
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| 2012112618 | Aug 2012 | WO |
| Entry |
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| Chang, M.-C.F. ; Verbauwhede, I. ; Chien, C. ; Xu, Z. ; Jongsun Kim ; Jenwei Ko ; Qun Gu ; Bo-Cheng Lai' “Advanced RF/baseband interconnect schemes for inter- and intra-ULSI communications,” IEEE Transactions on Electron Devices, vol. 52 , Issue: 7, 2005 , pp. 1271-1285. |
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| Number | Date | Country | |
|---|---|---|---|
| 20140044157 A1 | Feb 2014 | US |
| Number | Date | Country | |
|---|---|---|---|
| 61442557 | Feb 2011 | US | |
| 61443154 | Feb 2011 | US | |
| 61513732 | Aug 2011 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/US2012/025132 | Feb 2012 | US |
| Child | 13965077 | US |
