The present application claims priority to European Application No. 14165967.2 filed Apr. 25, 2014, the disclosure of which is hereby incorporated by reference in its entirety.
The invention generally relates to a programmable charged-particle multi-beam apparatus for processing (in particular nanopatterning or semiconductor lithography) or inspection of a target.
In more detail, the invention generally relates to a charged-particle multi-beam processing apparatus for exposure of a target with a plurality of beams of electrically charged particles, comprising a plurality of particle-optical columns arranged parallel and configured for directing a respective particle beam towards the target, wherein each particle-optical column comprises an illumination system, a beam shaping device and a projection optics system. The illumination system serves to produce a respective beam and form it into a (preferably, substantially telecentric) beam illuminating the beam shaping device. The beam shaping device is configured to form the shape of the illuminating beam into a desired pattern composed of a multitude of sub-beams, and includes an aperture array device provided with a multitude of apertures, each of said apertures defining the shape of a respective sub-beam having a nominal path towards the target, as well as a deflection array device for deflecting (only) selected sub-beams off their respective nominal path so that sub-beams thus selected do not reach the target; the remaining sub-beams represent the desired pattern being imaged to the target. The projection optics system serves to project an image of the beam shape defined in the beam shaping device onto the target.
Furthermore, the invention also generally relates to a beam shaping device (also called pattern definition device) for use in a column of such a charged-particle multi-beam processing apparatus, configured to be irradiated by an illuminating beam of electrically charged particles and to form the shape of the illuminating beam into a desired pattern composed of a multitude of sub-beams. This type of multi-column (or “multi-axis”) configuration is described in U.S. Pat. No. 7,214,951 and U.S. Pat. No. 8,183,543 of the applicant.
Embodiments of several solutions and techniques suitable in the field of charged-particle multi-beam lithography and nanopatterning and pertinent technology have been developed, such as the following: when using ion multi-beams coined CHARPAN (charged particle nanopatterning) and when using electron multi-beams coined eMET (electron mask exposure tool) or MBMW (multi-beam mask writer) for mask writing, and coined PML2 (Projection Mask-Less Lithography) for direct write lithography on substrates, in particular silicon wafers. In this context, relevant patent documents in the name of the applicant are U.S. Pat. No. 7,199,373, U.S. Pat. No. 7,214,951, U.S. Pat. No. 8,304,749, U.S. Pat. No. 8,183,543, and U.S. Pat. No. 8,222,621.
The multi-column optics 2 comprises a plurality of sub-columns 9 (the sub-columns 9 correspond to the “columns” as claimed in the claims; the number of columns shown is reduced in the depiction for better clarity, and represent a much larger number of columns that are present in the multi-column apparatus in a realistic implementation). Preferably, the sub-columns 9 have identical setup and are installed side-by-side with mutually parallel axes. Each sub-column has an illuminating system 11 including an electron or ion source 11a, an extraction system 11b, and an electrostatic multi-electrode condenser optics 11c, delivering a broad telecentric charged-particle beam to a pattern definition device (PDD) 12 being adapted to let pass the beam only through a plurality of apertures defining the shape of sub-beam (“beamlets”) permeating said apertures, and a demagnifying charged-particle projection optics 16 comprising three lenses. In the embodiment shown, the first lens is an accelerating electrostatic multi-electrode lens 16a whereas the second and third lenses 16b, 16c are either magnetic lenses, in particular when using electrons, or electrostatic lenses, for instance in the case where the particles are ions, as outlined in U.S. Pat. No. 7,214,951.
The accelerating first lens of the projection charged-particle optics 16 provides the important advantage of operating the PDD 12 at low kinetic energy of the particles (e.g. 5 keV) whereas providing high beam energy (e.g. 50 keV) at the cross-overs of the demagnifying projection optics, thus minimizing stochastic Coulomb interactions. Further, the high beam energy at the substrate is beneficial to reduce forward scattering of the charged particles when exposing the target, in particular the charged-particle sensitive layer 8.
The first lens of the projection optics forms a first cross-over whereas the second lens forms a second cross-over. At this position in each sub-column there is a stopping plate 15 configured to filter out beams deflected in the PDD. The third lenses 16c of the sub-columns as well as the stopping plates 15 are mounted onto a reference plate 17 which is mounted by suitable fastening means 18 onto the column base plate 4. Mounted onto the reference plate 17 are parts 19 of an off-axis optical alignment system.
The reference plate is fabricated from a suitable base material having low thermal expansion, such as a ceramic material based on silicon oxide or aluminum oxide, which has the advantage of little weight, high elasticity module and high thermal conductivity, and may suitably be covered with an electrically conductive coating, at least at its relevant parts, in order to avoid charging (by allowing electrostatic charges being drained off).
As can be seen in the sectional detail of
The flat upper surface of AAP 20 forms a defined potential interface to the condenser optics/illumination system 11. The AAP may, e.g. be made from a square or rectangular piece of a silicon wafer (approx. 1 mm thickness) 21 with a thinned center part 22. The plate may be covered by an electrically conductive protective layer 23, which will be particularly advantageous when using hydrogen or helium ions (as in U.S. Pat. No. 6,858,118). When using electrons or heavy ions (e.g. argon or xenon), the layer 23 may also be silicon, provided by the surface section of 21 and 22, respectively, so that there is no interface between layer 23 and bulk parts 21/22, respectively.
The AAP 20 is provided with a plurality of apertures 24 formed by openings traversing the thinned part 22. In the embodiment shown the apertures 24 are realized having a straight profile fabricated into the layer 23 and a “retrograde” profile in the bulk layer of the AAP 20 such that the downward outlets 25 of the openings are wider than in the main part of the apertures 24. Both the straight and retrograde profiles can be fabricated with state-of-the-art structuring techniques such as reactive ion etching. The retrograde profile strongly reduces mirror-charging effects of the beam passing through the opening.
The DAP 30 is a plate provided with a plurality of openings 33, whose positions correspond to those of the apertures 24 in the AAP 20, and which are provided with electrodes 35, 38 configured for deflecting the individual sub-beams passing through the openings 33 selectively from their respective paths. The DAP 30 can, for instance, be fabricated by post-processing a CMOS wafer with an ASIC circuitry. The DAP 30 is, for instance, made from a piece of a CMOS wafer having a square or rectangular shape and comprises a thicker part 31 forming a frame holding a center part 32 which has been thinned (but may be suitably thicker as compared to the thickness of 22). The aperture openings 33 in the center part 32 are wider compared to 24 (by approx. 2 μm at each side for instance). CMOS electronics 34 is used to control the electrodes 35, 38, which are provided by means of MEMS techniques. Adjacent to each opening 33, a “ground” electrode 35 and a deflection electrode 38 are provided. The ground electrodes 35 are electrically interconnected, connected to a common ground potential, and comprise a retrograde part 36 to prevent charging and an isolation section 37 in order to prevent unwanted shortcuts to the CMOS circuitry. The ground electrodes 35 may also be connected to those parts of the CMOS circuitry 34 which are at the same potential as the silicon bulk portions 31 and 32.
The deflection electrodes 38 are configured to be selectively applied an electrostatic potential; when such electrostatic potential is applied to an electrode 38, this will generate an electric field causing a deflection upon the corresponding sub-beam, deflecting it off its nominal path. The electrodes 38 as well may have a retrograde section 39 in order to avoid charging. Each of the electrodes 38 is connected at its lower part to a respective contact site within the CMOS circuitry 34.
The height of the ground electrodes 35 is higher than the height of the deflection electrodes 38 in order to suppress cross-talk effects between the beams.
The arrangement of a PDD 12 with a DAP 30 having electrodes oriented upstream as shown in
The third plate 40 serving as FAP has a flat surface facing to the first lens part of the down-stream demagnifying charged-particle projection optics and thus provides a defined potential interface to the first lens 16a of the projection optics. The thicker part 41 of FAP 40 is a square or rectangular frame made from a part of a silicon wafer, with a thinned center section 42. The FAP 40 is provided with a plurality of openings 43, which correspond to the openings 24, 33 of the AAP 20 and DAP 30 but are wider as compared to the latter.
The PDD 12, and in particular the first plate of it, the AAP 20, is illuminated by a broad charged particle beam 50 (herein, “broad” beam means that the beam is sufficiently wide to cover the entire area of the aperture array formed in the AAP), which is thus divided into many thousands of micrometer-sized beams 51 when transmitted through the apertures 24. The beams 51 will traverse the DAP and FAP unhindered.
As already mentioned, whenever a deflection electrode 38 is powered through the CMOS electronics, an electric field will be generated between the deflection electrode and the corresponding ground electrode, leading to a small but sufficient deflection of the respective beam 52 passing through (
The reduction factor of the demagnifying charged-particle optics 16 is chosen suitably in view of the dimensions of the beams and their mutual distance in the PDD 12 and the desired dimensions of the structures at the target. This will allow for micrometer-sized beams at the PDD whereas nanometer-sized beams are projected onto the substrate.
The ensemble of (unaffected) beams 51 as formed by AAP is projected to the substrate with a predefined reduction factor R of the projection charged-particle optics. Thus, at the substrate a “beam array field” (BAF) is projected having widths BX=AX/R and BY=AY/R, respectively, where AX and AY denote the sizes of the aperture array field along the X and Y directions, respectively. The beam size of an individual beam at the substrate is given by bX=aX/R and by=aY/R, respectively, where aX and aY denote the sizes of the beam 51 as measured along the X and Y directions, respectively, at the level of the DAP 30.
It is worthwhile to note that the individual beams 51, 52 depicted in
The arrangement outlined in
The recent progress of integrated circuits, in particular microprocessors, was made possible not only by novel lithographic, deposition, and etching techniques, but also by innovative circuit design. A most powerful innovation was to proceed from a two-dimensional to a one-dimensional circuit design, as was described by Yan Borodovsky in “EUV, EBDW—ARF Replacement or Extension?”, KLA-Tencor Lithography User Forum, Feb. 21, 2010, San Jose, Calif., USA. For this end regular line patterns (
The current requirements of the semiconductor industry for various dimension parameters such as the minimum feature size CA, CB of the cutting pattern are listed in Table 1.
28 nm
14 nm
38 nm
28 nm
20 nm
10 nm
26 nm
20 nm
14 nm
17 nm
14 nm
The numbers in normal typeface in Table 1 were taken from the above-cited reference in KLA-Tencor Lithography User Forum as well as the slide presentation of Yan Borodovsky in “MPProcessing for MPProcessors”, SEMATECH Maskless Lithography and Multibeam Mask Writer Workshop, May 10, 2010, New York, N.Y., USA. The italic numbers are deduced values; e.g. it is indicated in the reference in KLA-Tencor Lithography User Forum that P and L scale with a factor of 0.71 from node to node.
The required Critical Dimension Uniformity (CDU) and the overlay (OL) of the minimum cutting pattern with the critical dimension CA are also indicated in Table 1. The minimum distance CC between cutting patterns and minimum periodicity CP of cutting patterns, as defined in
To date, development of EUV (extended ultra-violet) lithography, based on 13.5 nm wavelength, is delayed, and therefore, in 2015 there will be the necessity to expose the cutting pattern with 193 nm immersion optical lithography. The minimum pitch of the 193 nm immersion scanner lithographic technique is ca. 80 nm. As a consequence there is the need to expose the cutting pattern with 4 different masks, as outlined in the above-cited reference in KLA-Tencor Lithography User Forum as CP=40 nm for the 10 nm logic technology node (Table 1). EUV lithography with a numerical aperture of NA=0.25 provides better resolution capabilities. As a consequence, for the 10 nm logic technology node the EUV exposure of the cutting pattern could be possible with one mask. Therefore, there is continued strong industrial interest in EUV lithography. However, the entry of EUV lithography is likely to be pushed up to the 10 nm or 7 nm logic node. Still, there are major hurdles for EUV lithography to overcome, which is why semiconductor industry is increasingly and seriously interested in alternative lithographic possibilities for cutting pattern exposure. Nano-imprint lithography is one possibility, but there are several difficulties, such as master template fabrication, lifetime of working stamp replicas, defect inspection and repair of the stamps, and the possible occurrence of defect generation during imprinting. As another alternative, electron multi-beam direct write has obtained high industrial attention and interest because it offers sub-10 nm resolution potential and no masks are needed.
In view of the above, there is the need for an improved multi-beam tool allowing an efficient approach to write structures in a one-dimensional circuit design.
This aim is met by embodiments of a pattern definition device, as well as a charged-particle multi-beam processing apparatus incorporating such a pattern definition device layout, wherein, for a target comprising a line pattern oriented along a given line grid direction and in order to perform the exposure of the target with respect to this line grid direction, the pattern definition device includes
wherein the apertures in said array of apertures are configured to form an oblong shape as seen along the direction of the beam, said oblong shape having a short and a long side, with the long side being at least the double of the short side, wherein the oblong shape formed by the apertures is oriented traversing the line grid direction. For instance, the beam shaping device may be orientable with respect to said line grid direction such that the aperture oblong shape is oriented traversing the line grid direction.
With this solution the sub-beams are given a shape enabling the definition of cut shapes on the target. This will considerably reduce the processing time for the underlying layouts to be produced on the target. Generally, for a target to be processed, such as a silicon wafer with a line pattern as mentioned above, the orientation of the line pattern is known beforehand, i.e. prior to loading the target into the multi-beam processing apparatus. Methods to specify and determine the orientation are well known, for instance by means of a notch of a round wafer. Thus, the target is loaded into the multi-beam processing apparatus with a well-defined and predetermined orientation of the line grid direction. In addition, a “pre-aligner” may be used to achieve an adequate orientation, which detects the actual orientation of the wafer and adjusts it as required. As a variant, the line grid direction (for instance, along the X- or Y-direction of the apparatus) may be defined for each target to be processed, for instance as an input parameter to be specified at the start of each respective writing process.
With this solution the sub-beams are given a shape enabling the definition of cut shapes on the target. This will considerably reduce the processing time for the underlying layouts to be produced on the target.
Generally, for a target to be processed, such as a silicon wafer with a line pattern as mentioned above, the orientation of the line pattern is known beforehand from the printed layout, i.e. prior to loading the target into the multi-beam processing apparatus. The line grid direction (for instance, along the X- or Y-direction of the apparatus) may thus be defined for each target to be processed, for instance as an input parameter to be specified at the start of each respective writing process. Furthermore, methods to specify and determine the orientation of the substrate as well as the structures that it carries are well known. For example, well-defined structures written beforehand and the orientation thereof may be recorded by means of a signal of secondary electrons generated therefrom by the incoming primary lithography beam. Thus, the target may be loaded into the multi-beam processing apparatus with a well-defined and predetermined orientation of the line grid direction.
In a first aspect of embodiments of the invention, the apertures in the aperture array device directly define the shape of the respective sub-beams. Thus, in this case, the apertures in an array of apertures have an oblong shape, which may be formed according to the desired shape of a cut line, for instance. According to a suitable choice, the long side of the oblong shape will be at least the double of the short side of said oblong shape and oriented traversing a line grid direction of a line pattern of the target.
An alternative aspect realizes a composite aperture array device, which comprises two (or more) consecutive plates. These plates are suitably arranged parallel within the pattern definition device and preferably in immediate order to each other. Each plate may have an array of apertures with the apertures of the plates mutually corresponding and cooperating to form a shape of the corresponding sub-beam, said shape being defined by the relative position of the plates as seen along the direction of the beam. In a further development of this aspect, these plates may be provided with positioning devices to modify the relative position of the plates transversal to the direction of the beam, which will allow defining variable shapes with one composite aperture array device.
In a suitable development of the embodiments of the invention, the oblong shape of the apertures may be uniformly oriented along a specific direction for each array of apertures on the aperture array devices of each respective column. (Herein the term “columns” and “sub-columns” are used indiscriminately to denote the individual columns of the multi-column device.) Furthermore, the aperture array devices (or at least a number of them) may be provided with at least two interlacing arrays of apertures, wherein the oblong shapes within each array are uniformly oriented along a direction specific to the respective array, the specific directions of the arrays being mutually different. In particular, each of the aperture array device may be provided with two interlacing arrays of apertures, wherein the oblong shapes within a first array are uniformly oriented along a first direction, and within a second array along a second direction transversal to the first direction. This allows an efficient processing of target layouts comprising regions of different line orientations.
Another development combines embodiments of the invention with a general patterning procedure in a very flexibly manner. In this case, at least part of the aperture array devices may be additionally provided with an array of non-oblong apertures, said non-oblong aperture having a shape differing from the shape of the oblong apertures, preferably square, circular or hexagonal, said array of non-oblong apertures interlacing with the array of oblong apertures.
Another approach uses different orientations of the apertures for different columns. Thus, advantageously, while for each column the oblong shape of the apertures is uniformly oriented within the respective aperture array device, a first group of columns may have the oblong shapes oriented along a first direction, but a second group may have the oblong shapes oriented along a second direction transversal to the first direction. Preferably, the second direction may be orthogonal to the first direction.
Each column has a projection optics system which projects an image onto the target wherein the image may include an isotropic or anisotropic blur. Another development of the embodiments of the invention employs an anisotropic blur generated by the projection optics system and having an axis of maximum blur oriented along a direction corresponding to the long side of the oblong shape of the apertures in the respective aperture array device and an axis on minimum blur oriented along the opposite direction. This contributes to a high definition of the position of cut lines along the line direction, while ensuring that each cut line properly interrupts the respective line.
In conjunction with a stage for positioning the target with regard to the plurality of particle-optical columns, another possible advantage of the embodiment of the invention is the efficient use of the multi-column system for simultaneous multiple writing of the target. In particular, the target stage may be configured to move the target through a sequence of positions, such that each column produces a set of images on the target within a predefined respective column exposure area, wherein the column exposure areas of the columns combine into a covering of a target exposure area on the target. Thus, each column writes into a specific area on the target (only), which facilitates implementation and calculation of the corresponding writing patterns. For instance, the column exposure area of a column may correspond to the area of one die field on the target. Alternatively, the column exposure area of a column may correspond to an area of two adjacent die fields on the target; in subsequent writing steps, the association of two die fields, respectively, to one column may vary. With this, it is possible to realize a very compact tool configuration which is of high importance when aiming to cluster several tools within a given clean room area.
Furthermore, in order to facilitate the access to the individual columns for providing them with the pattern data for the writing process, the plurality of particle-optical columns may be arranged in a two-dimensional arrangement wherein along (at least) one direction of the two-dimensional arrangement the columns are spaced apart by a column offset forming aisles, said column offset being at least the doubled width of the minimal pitch between adjacent columns within the arrangement.
Another aspect of the embodiments of the invention improves the quality of the shape of the sub-beams by providing a clean interface between the pattern definition device and the other optical components. Namely, the respective pattern definition device may include (i) a first boundary device as the first element of the pattern definition device as seen along the direction of the beam, the first boundary device having a first surface oriented towards the illumination system, and (ii) a final plate device as the last element of the pattern definition device as seen along the direction of the beam, the final plate device having a final surface oriented towards the projection optics system. Advantageously, the first and final surfaces are flat—with the exception of a respective array of openings corresponding to the apertures of the aperture array device of the respective pattern definition device. In particular, the first boundary device may be realized by the aperture array device itself, or by a separate plate-shaped device.
In the following, embodiments of the present invention are described in more detail with reference to the drawings, which illustrate several embodiments of the invention given by way of example and representing suitable implementations of the invention, which are not to be construed as restrictive to invention. The drawings schematically show:
The embodiments shown in the following relate to a multi-beam tool for cutting patterns which is designed for mix-and-max lithography, where the substrate (e.g., silicon wafer) is exposed e.g. with a 193 nm immersion scanner tool with die-fields having length DX and width DY of typically DX=33 mm and DY=26 mm. One die field may, and typically will, comprise several chips. The embodiments are not limiting, and thus the invention may refer to other layouts and applications as well; in particular, the values DX and DY and other dimensions presented here may be adapted as deemed suitable. Within this disclosure, the terms “upper”, “lower” and related terms like “top” or “bottom” are to be understood with regard to the direction of the beam, which is thought to run downwards along a “vertical” axis. This vertical axis, in turn, is identified with the Z direction (longitudinal direction), to which the X and Y directions are transversal.
Examples of compact sub-columns arrangements 60 and 70 suitable for embodiments of the invention are shown in
Assuming DX=33 mm and DY=26 mm, then in case of
The aperture array field may also, in a variant, be chosen to be rectangular with the same diagonal length as a corresponding square aperture array field.
Based on detailed charged-particle optics simulations of the applicant, there is the possibility to generate sub-columns with an inner diameter of approx. 40 mm when using an aperture array field of approx. 16.4 mm×16.4 mm, and with an inner diameter of approx. 24 mm when using an approx. 8.2 mm×8.2 mm aperture array field. In both cases there is the possibility to obtain a very low (<5 nm 1 sigma) beam blur, in particular when using 50 keV electrons at the substrate and limiting the total current of the beams through the charged-particle projection optics to less than 1 pA.
In AAP devices of the state of the art the apertures have quadratic shape, and also the corresponding larger apertures in the DAP and FAP have quadratic shape. This makes it possible to write even very complex patterns. Such complex patterns are needed e.g. for multi-beam mask writing. For mask writing the density of the patterns is usually very high, reaching up to, for instance, 75% of the total area. When writing leading-edge masks as needed for sub-20 nm 193 nm immersion optical lithography there is the necessity to write highly complex mask patterns as e.g. serifs (additional patterns at the corners), “strong” or “aggressive” OPC (optical proximity correction) patterns and, in particular for sub-15 nm lithography, also ILT (inverse lithography technology) curvilinear patterns. Therefore, for such leading-edge masks the mask pattern density is well above 20%.
For complementary lithography at the substrate, the density of the cutting patterns is max. 10%, as outlined in Table 1. Further, the shape of the cuts are all rectangular, the smallest rectangle having dimensions of CA×CB with CA=L+2 nm and CB=2*CA, see Table 1. All larger rectangles are multiples of the smallest rectangle in the direction vertical to the regular line grid (see
Embodiments of the present invention proposes a pattern definition device (PDD) which is optimal for a multi-beam tool for cutting patterns. Furthermore, embodiments of the invention enable a maximum wafer throughput for a defined data path speed as provided to the PDD with a deflection array plate (DAP) with CMOS circuitry providing the switching speed as needed for the targeted throughput.
According to embodiments of the invention, a suitable value of the ratio aY/aX is in the range between 2 and 4 (inclusive), preferable between 2 (exclusive) and 2.5, and typically 2.5 as outlined in the example of
The openings in the FAP may have a square or rectangular shape of adequate width (see
As an example, an AAP with rectangular aperture openings having aX=1.6 μm and aY=4 μm may be used to generate a cutting pattern with e.g. CA=12 nm and CB=24 nm as needed for the 5 nm logic node (Table 1) with a line pattern of L=10 nm and P=20 nm. Using a projection optics with a reduction factor of R=200, rectangular beams will expose corresponding images at the substrate with bX=8 nm and bY=20 nm side lengths at the silicon wafer substrate. Due to the aberrations of the charged-particle projection optics, the beams will be blurred and will have rounded ends. Because of charged particle forward scattering in the resist, resist blur and resist processing of widening of the developed resist patterns takes place. Using 50 keV electrons and adequate resist materials and resist exposure dose (to minimize shot noise influences) a widening of typically 4 nm is observed. Thus, the developed resist pattern will comprise shapes corresponding to the shapes shown in
Depending on the pattern placement requirements, different multi-beam exposure modes may be chosen. Multi-beam exposure techniques using overlapping beam shots are discussed in U.S. Pat. No. 8,222,621 and U.S. Pat. No. 7,276,714.
As an example shown in
In contrast, embodiments of the invention shown in
When using a rectangular beam with shot overlap of half the beam size in X direction and Y direction, i.e. the physical grid size is half of the beam width in X and Y, respectively, a different address grid is obtained for placing the cutting pattern edges.
The bottom row frames of
For the 10 nm beam size simulations (profiles along cut direction D2) a better blur was assumed as compared to the simulations for the 20 nm beam size (i.e., along line grid direction D1). This reflects a further aspect of embodiments of the invention that by purpose the parameters of the charged-particle optical column are adjusted such that an improved resolution of the rectangular beam is achieved for bX. This improved resolution of the rectangular beam at the substrate in the small beam direction can be achieved by inducing an X-Y-astigmatism in the charged-particle optics, for instance by inducing a quadrupole field in electrostatic multipole electrodes positioned within the charged particle projection optics. This will cause that the resolution gets worse in the long beam direction and is improved in the direction of the small beam width. If the cut is to be produced in the other direction, then the quadrupole field is rotated by 90° to get the desired effect along the other direction.
Thus, it will be clear to the skilled person that embodiments of the multi-beam exposure techniques described herein are suitable to fulfill the 3 nm 3 sigma CDU and 3 nm 3 sigma OL targets for the example of cutting pattern exposure for the 5 nm Logic Node. Consequently, it will also be evident that the conditions can also be fulfilled for the 3 nm Logic Node and even smaller Logic Nodes.
It should be mentioned that there is also the possibility to use a multi-beam exposure mode where the overlap between exposures takes a different value, such as a quarter of the beam width. An implementation of such a finer multi-beam exposure mode may be needed in case of requirements higher than those listed in Table 1 for the technology nodes indicated therein.
As the sub-column exposures are done in parallel the movements necessary for writing the entire area of a 450 mm wafer are ±16.5 mm in X-direction (for the exposure stripes which are 33 mm long) and ±13 mm in Y-direction, covered during stepping from one stripe to the next. Only some small additional distances will have to be added for the stage returns in X-direction. Thus, since not the whole wafer area has to be scanned, the wafer stage for the multi-beam tool can be made in a very compact form, which is a significant advantage of embodiments of the present invention.
Of course, the above-stated numbers and dimensions may be modified and adapted to the individual application and node sizes, as will be clear to the skilled person. In particular, for the exposure of 300 mm silicon wafers a correspondingly smaller number of sub-columns will be needed.
Referring to
As the sub-column exposures are done in parallel the movements required for writing the area of a 450 mm wafer are ±33 mm in X-direction (for the exposure stripes of 66 mm length) and ±13 mm in Y-direction, resulting from stepping from one stripe to the next. Only some small additional distances will have to be added for the stage returns in X-direction. Thus again, since not the whole wafer are has to be scanned, the wafer stage for the multi-beam tool for cutting patterns can be made in a very compact form, which is a significant advantage of embodiments of the present invention.
Table 2 lists data for a multi-beam tool 450 mm wafer throughput performance for two exemplary cases made possible by embodiments of the invention. Case A denotes a configuration where a sub-column exposes the area of two die fields (66 mm×26 mm), and Case B a configuration where a sub-column exposes one die field area (33 mm×26 mm).
For a given data path speed, Case B can provide twice the throughput of Case A. With 25% overheads (wafer change and alignment, exposure overhead, stage return overhead), the resulting throughput is 4 WPH (300 mm or 450 mm silicon wafers per hour, with corresponding number of sub-columns).
Table 3 lists the data for a tool using this modified multi-beam exposure mode. As can be seen, the wafer throughput can be enhanced to 8 WPH (incl. 25% overhead), for Case B with 240 Gbits/s data path speed and 4 A/cm2 current density. Despite of having 20% of the programmable beams “on” the current through the column is <0.5 pA.
It should be mentioned that the above are illustrative examples of possible multi-beam tool column configurations and wafer exposure strategies, which are not meant as restricting the invention to the examples given above. The skilled person can easily derive suitable adaptions, such as for writing 300 mm silicon wafers. Further, the substrate may be a wafer of another material as e.g. GaAs or a substrate of square shape, such as e.g. a 6″ glass plate covered with a conductive layer and resist.
Further it should be mentioned that the die field dimensions of DX=33 mm and DY=26 mm are for exemplary purpose as well, even though they were chosen in accordance with state-of-the-art optical lithography tools for wafer exposure. The multi-beam tool configuration can be adapted to other die field dimensions in a straightforward manner.
A further aspect of embodiments of the invention addresses writing of cuts along more than one direction. Referring to
For example, in the case of sub-columns exposing one 33 mm×26 mm die-field on 450 mm silicon wafers,
The multi-beam tool throughput for cutting patterns in both dimensions is approximately half of the multi-beam tool throughput as compared to when cutting patterns are realized in one dimension only. As the wafer is maintained on the chuck for both exposures there is only one wafer change time and one wafer alignment time needed.
Multi-Beam Tool with In-Situ Change of Aperture Array Fields
22 illustrate a further development of embodiments of the invention. In the AAP 200, of which
In a variant embodiment as illustrated in
In accordance with this variant embodiment of the invention,
In another development of embodiments of the invention illustrates in
The shape of the apertures 410, 420 of the plate devices 411, 421 are, for instance, squares of a common side length. Suitably, this side length is longer than the maximum side length of the oblong shapes to be defined using the apertures 410, 420. Referring to
Multi-Beam Tool with Non-Compact Sub-Column Arrangement
This arrangement of sub-columns is not compact in at least one of the directions, for example along the X-direction, which offers the advantage of ease of providing the data path 463 to each sub-column as symbolized in
Depending on the multi-beam exposure task, the PDD 462 in
Number | Date | Country | Kind |
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14165967.2 | Apr 2014 | EP | regional |