The technical field of this invention is interprocessor communications.
In today's large SOCs that contain multiple compute cores, the cores can be running on different power domains (thus on separate PLLs) in order to gain full clock speed entitlement. However, there may be times when some of this compute power isn't necessary and could to be powered down in order to reduce the overall power consumption of the device.
If the unit being powered down is a cache coherent master in a cache coherent interconnect system, the transition of the master into a fully powered down non-responsive state needs to be well understood by the rest of the system and the interconnect. With regards to snoop transactions, the power down transition needs to ensure that hang situations are avoided:
An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain-master and interconnect. The bridge uses a partial powerdown mode where its master-side domain half is able to powerdown with the master and the interconnect-side domain half remains active to auto-respond to snoop requests from the interconnect both during the master's powerdown sequence and subsequently after the master has fully powered-down. The bridge's auto snoop response mode automatically turns off once the master powers back up and comes out of reset. Similarly, if the device and system interconnect come out of reset, but the master remains in reset and possibly powers downs, the bridge detects this and also enters its auto snoop response mode.
These and other aspects of this invention are illustrated in the drawings, in which:
The powerdown procedure implemented in the bridge is the following:
This solution provides a very simplistic approach to the powerdown of a cache coherent master in a coherent interconnect system that eliminates the need to make the interconnect aware of the powerdown mode the cache coherent master is about to enter. Having to make the interconnect aware of the master powering down, requires either that the interconnect has to resolve in-flight snoop transactions already sent before the interconnect has observed the powerdown hint from the master or that the master has to be able to service all snoop responses even during the powerdown sequence.
The described solution allows the interconnect to be simplified by never having to comprehend the powerdown nature of the cache coherent master and having the guarantee that snoop transactions will always be responded to. The master can also be simplified knowing that it can safely powerdown irrespective of whether there are still snoop transactions being serviced by its logic.
Lastly, on powerup, the interconnect and master do not need to share any powerup information between them, the bridge seamlessly transitioning back to the snoop transaction pass through mode when it detects that the master has powered-up and came out of reset.
This application claims priority under 35 U.S.C. 119(e) (1) to Provisional Application No. 61717823 filed 24 Oct. 2012.
Number | Date | Country | |
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61717823 | Oct 2012 | US |