Patent Application
20140091394
The disclosure relates generally to semiconductor devices, and more particularly, to a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin structure and methods of forming the same.
In manufacturing multi-gate field effect transistors (FETs) that include a plurality of fin structures (i.e., a FinFET), in order to operate properly, the fin structures must be isolated from the substrate if the FET is built on a bulk substrate. In contrast, a FinFET built on a silicon-on-insulator (SOI) substrate includes a buried oxide layer (BOX) that isolates the fin structures from each other and the substrate.
Various attempts have been made to isolate the fin structures from the substrate for FinFETs built on bulk substrates. For example, a high dose junction implant at the base of each fin may isolate the fin from the bulk substrate. Alternatively, oxide is grown across the bottom of each fin structure. However, the viability of each of these attempts in manufacturing the FinFETs on a bulk substrate is unknown and may be costly.
Aspects of the disclosure provide a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin and methods of forming the same. In one embodiment, the multi-gate FET includes: a plurality of silicon fin structures formed on the bulk substrate, each silicon fin structure including a body region, a source region, and a drain region; wherein a bottom portion the body region of each silicon fin structure includes a tipped shape to isolate the body region from the bulk substrate, and wherein the plurality of silicon fin structures are attached to the bulk substrate via at least a portion of the source region, or at least a portion of the drain region, or both.
A first aspect of the disclosure provides a multi-gate field effect transistor (FET) formed on a bulk substrate, comprising: a plurality of silicon fin structures formed on the bulk substrate, each silicon fin structure including a body region, a source region, and a drain region; wherein a bottom portion the body region of each silicon fin structure includes a tipped shape to isolate the body region from the bulk substrate, and wherein the plurality of silicon fin structures are attached to the bulk substrate via at least a portion of the source region, or at least a portion of the drain region.
A second aspect of the disclosure provides a method of fabricating a multi-gate field effect transistor (FET) in a bulk substrate manufacturing process, the method comprising: forming a plurality of silicon fin structures on a bulk substrate; depositing an oxide layer on the bulk substrate; removing a portion of the oxide layer, such that a first sidewall portion of each silicon fin structure is exposed; depositing a nitride spacer along the first exposed sidewall portion of each silicon fin structure; removing a remaining portion of the oxide layer, such that a second sidewall portion of each silicon fin structure below the nitride spacer is exposed; performing a plurality of etches, such that a bottom portion of a body region of each silicon fin structure includes a tipped shape; and depositing an oxide between the body region of each silicon fin structure and the bulk substrate to isolate the body region of each silicon fin structure from the bulk substrate.
A third aspect of the disclosure provides a method of fabricating a multi-gate field effect transistor (FET) in a bulk substrate manufacturing process, the method comprising: forming a plurality of silicon fin structures on a bulk substrate; depositing an oxide layer on the bulk substrate; removing a portion of the oxide layer, such that a first sidewall portion of each silicon fin structure is exposed; depositing a nitride spacer along the first exposed sidewall portion of each silicon fin structure; removing a remaining portion of the oxide layer, such that a second sidewall portion of each silicon fin structure below the nitride spacer is exposed; performing an isotropic reactive ion etching to etch a curved portion of the second sidewall portion of each silicon fin structure; performing a sigma silicon wet etch, such that a bottom portion of a body region of each silicon fin structure includes a tipped shape and a portion of the bulk substrate directly below the body region of each silicon fin structure includes a corresponding tipped shape; and depositing an oxide between the body region of each silicon fin structure and the bulk substrate to isolate the body region of each silicon fin structure from the bulk substrate.
The above and other aspects, features and advantages of the disclosure will be better understood by reading the following more particular description of the disclosure in conjunction with the accompanying drawings.
The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the disclosure. The drawings are intended to depict only typical embodiments of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements.
As mentioned above, the disclosure relates generally to semiconductor devices, and more particularly, to a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin structure and methods of forming the same.
In manufacturing multi-gate field effect transistors (FETs) that include a plurality of fin structures (i.e., a FinFET), in order to operate properly, the fin structures must be isolated from the substrate if the FET is built on a bulk substrate. In contrast, a FinFET built on a silicon-on-insulator (SOI) substrate includes a buried oxide layer (BOX) that isolates the fin structures from each other and the substrate.
Various attempts have been made to isolate the fin structures from the substrate for FinFETs built on bulk substrates. For example, a high dose junction implant at the base of each fin may isolate the fin from the bulk substrate. Alternatively, oxide is grown across the bottom of each fin structure. However, the viability of each of these attempts in manufacturing the FinFETs on a bulk substrate is unknown and may be costly.
Aspects of the disclosure provide a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin and methods of forming the same. In one embodiment, the multi-gate FET includes: a plurality of silicon fin structures formed on the bulk substrate, each silicon fin structure including a body region, a source region, and a drain region; wherein a bottom portion the body region of each silicon fin structure includes a tipped shape to isolate the body region from the bulk substrate, and wherein the plurality of silicon fin structures are attached to the bulk substrate via at least a portion of the source region, or at least a portion of the drain region, or both. Therefore, the body of each fin structure is effectively isolated from the bulk substrate. In the following descriptions, the exemplary figures show both source and drain regions attached to the bulk substrate.
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The plurality of silicon fin structures 10 each include a body region 20 that is directly below gate 22. A source region 24 and a drain region 26 of silicon fin structure 10 are adjacent to body region 20 (only shown in
However, it is understood that the plurality of fin structures 10 remain attached to the bulk substrate 102 via at least a portion of the source region 24, or at least a portion of the drain region 26, or both. That is, in one embodiment, only the body region 20 may be isolated from the bulk substrate 102. However, as seen in
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The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.
