Multi-layer semiconductor integrated circuits enabling stabilizing photolithography process parameters, the photomask being used, and the manufacturing method thereof

Abstract

A multi-layer semiconductor integrated circuits enabling stabilizing photolithography process parameters, the photomask being used, and the manufacturing method thereof is provided, which is to provide a formal pattern layout first, and to layout in coordination with a dummy pattern of the regulations, next combine the dummy pattern layout with the formal pattern layout by utilizing the logic operation so that the dummy pattern layout is added within the informal pattern spacing of the formal pattern layout, next to manufacture the photomask by utilizing the fused pattern layout so that it is applicable to various density change of the pattern structure layer of the multi-layer semiconductor integrated circuits with various logic process and further decrease the density variation between multi-layer pattern structures to simply the control of the photolithography process by utilizing the way of adding the dummy pattern layout as well as stabilizing the process.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to a method used to stabilize a photolithography process in semiconductor, especially relates to a method utilizing a dummy pattern to manufacture the integrated circuits of semiconductors as well as the layout of photomask being used to stabilize a photolithography process and to simply the control of photolithography process which also makes the photolithography process more smooth.

BACKGROUND OF THE INVENTION

[0002] As the progress of integrated circuits industry, the number of devices required to allocate inside a chip grows continuously with double and doubles which makes the line width shrink and shrink such that the photolithography imaging also must be finer and finer gradually. Thus, the minimum size of the patterns on the integrated circuits is always a representive pointer in the development history of the semiconductor technology; so it is more unelectable for the role plays by the line width control in photolithography process today with the semiconductor technology becomes the deep sub-micron fields and in the future with finer and finer continuously.

[0003] However, most of today's semiconductor technology exposes using conventional optical method. Since the vibration characteristic of optics limits the limits of exposure line width, if we want the finer line width we must use the light source with shorter wavelength. The wavelength of the light source used in today's semiconductor industry is as short as 248 nm; even, the wavelength of said light source reaches the limits of interference in some advance processes and the more complex Phase Shifting Mask Method must be used to let the light source being used in advanced deep sub-micron process.

[0004] Thus it is known that the photolithography process is in association with the line width being exposed, which means that the finer line width, the photolithography process with the shorter wavelength is required to avoid the diffraction phenomena and the exact pattern is acquired. So if we use the light source with the same wavelength to expose the devices with various line width, the exact exposure in some regions could be acquired, with some exceptions that there is diffraction phenomena in some regions. In addition to the special characteristic of the general logic devices product line which makes various pattern density of the multi-layer pattern structure due to the variation of products, such variation of the pattern density between layers will cause the line width change which does not obey the specification of the line width error; besides, since there is also deference of the photolithography process in the process of the same product, i.e., it is required to change the condition of the photolithography in each process. So, the engineers use fine-tuning the photolithography process to conform the requirements of the products in most conventional processes, which also causes the trouble in mass production and makes the mass production line more and more complex.

[0005] Thus, in order to solve the drawback caused by fine-tuning the photolithography process and avoid the trouble of mass production of the conventional logic devices, this invention provides a multi-layer semiconductor integrated circuits enabling, the photomask being used, and the manufacturing method thereof to solve the above-mentioned problems.

SUMMARY OF THE INVENTION

[0006] Therefore a main object of this invention is to provide a method which, by utilizing the special and regular dummy pattern, adds it on the formal pattern layout to increase the pattern density of the multi-layer semiconductor integrated circuits and the photomask being used to solve the trouble of the conventional logic devices in mass production and achieve the purpose of stabilizing the photolithography process.

[0007] Another object of this invention is to decrease the variation of the multiple pattern structure density between the products to simply the photolithography process and acquire a stable process.

[0008] To achieve the above-mentioned object, this invention comprises a formal pattern layout with a plurality of line and there is an informal pattern space between each line, and the dummy pattern layout of a plurality of block, which adds to the informal space by utilizing the logic operation, and it is apart with each adjacent line with a specified distance. Besides, each block is arranged in the informal pattern space with the regulation of mimicy states, whereas it is replaced by the formal pattern layout and the specified spacing when some regulation of mimicy states falls into the scope covered by the line and the specified spacing so that the pattern layout and density of the formal pattern layout and the dummy pattern layout could combine with each other and finally completes the fused pattern layout.

[0009] To make the audit commissioner further understand the above-mentioned purpose of this invention as well as the structure characteristic of this invention, the detail explanation with the figure attached is shown as below:

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is the cross-sectional view of the embodiment of the fused pattern structure layer according to the present invention;

[0011] FIG. 2A, FIG. 2B and FIG. 2C are the cross-sectional views of the steps of manufacturing the photomask according to the present invention; and

[0012] FIG. 3A through FIG. 3H are embodiments of the dummy pattern layout according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] This invention discloses a multi-layer semiconductor integrated circuits of the pattern structure of fusing the dummy pattern layout, the photomask being used, and the manufacturing method of the photomask of fusing the dummy pattern layout thereof, wherein it adds the special and regular dummy pattern layout to the informal pattern space on the formal pattern layout to increase the pattern density of the pattern structure layer by means of the method and achieve the purpose of stabling the parameters in the photolithography process.

[0014] On proceeding the process of exposure and photolithography, since the product characteristic of the general logic devices often causes the variations of the pattern density of each layer of the pattern density in semiconductor integrated circuits, it makes the change of the lithography condition in each process which not only makes the process more complex but also the degree of stability of the process is influenced and it often cause the trouble in mass production. To avoid from this, this invention combines the formal pattern layout layer with two different pattern densities with the dummy pattern layout and thus a pattern layer which obeys the requirements of the logic device products and it is acquired to be used to manufacture the photomask such that is is applicable to the pattern density of the multi-layer semiconductor integrated circuits of various logic device without changing the process condition of photolithography.

[0015] To give a detailed description, the semiconductor integrated circuits provided by this invention is the one with multiple pattern structure wherein one of the pattern structure layer is comprised of a formal pattern layout and the dummy pattern. Refer to Figure. The formal pattern layout 10 comprises a plurality of lines 12 and an informal pattern space 14 between each line 12; the dummy pattern layout 20 comprises a plurality of blocks 22 which is sited within the informal pattern space 14 of the formal pattern layout 10 and it keeps apart with a specified distance with each neighboring line 12, wherein each block 22 is arranged within the informal pattern space 14 with the regulation of mimicy states; whereas it is replaced by the formal pattern layout and the specified spacing when some regulation of mimicy states falls into the scope covered by the line and the specified spacing and a fused pattern structure layer is thus completed. The above-mentioned formal pattern layout 10 and the dummy pattern layout 20 are comprised of the same material.

[0016] Besides, except that the multi-layer pattern structure of the semiconductor integrated circuits having the fused pattern structure layer, the photomask being used on manufacturing the semiconductor integrated circuits also has the same characteristic; in other words, the semiconductor integrated circuits photomask having a pattern structure whereas the pattern structure is comprised of a formal pattern layout 10 and a dummy pattern layout 20 which detail structure is the same with the above-mentioned so that it is not to be repeated to mention it.

[0017] Next we explain the manufacture method of the semiconductor integrated circuits comprising the following steps: first, as shown in FIG. 2A, a layout 10 of one representing formal pattern for manufacturing on a photomask 40 is provided with a plurality of line 12, and there is an informal pattern space 14 between each line 12 within the scope of the photomask 40; next please refer to FIG. 2B, a layout of representing the dummy pattern is provided comprising a plurality of regularly arranged pattern block 22; next, map the dummy pattern layout 20 onto a region covered by the photomask 40, and to add to set up the corresponding dummy pattern layout 20 with a specified distance with each line 12 in the uninformal pattern space 14 and further complete a fused pattern layout 30 as shown in FIG. 2C; finally using the fused pattern layout 30 to complete the manufacture of the photomask.

[0018] For example, a logic device product of the semiconductor integrated circuits has three layers of pattern structure layer wherein the density of the formal pattern layout of the pattern structure layer of the first layer is 64% (pattern/total area, dark/total), the density of the formal pattern layout of the pattern structure layer of the second layer is 52%, the density of the formal pattern layout of the pattern structure layer of the third layer is 28%. Due to the variation of the pattern density between the multi-layer pattern structures, it could utilize the dummy pattern layout to fill up the spacious informal pattern space of the pattern structure layer so that the variation of the pattern density of the three-layer pattern structure of the logic device product is lowered.

[0019] Let's take the manufacture of the first layer of pattern structure layer and the third layer of pattern structure layer as an example: the density of the formal pattern layout of the pattern structure layer of the third layer is 28%, in order to lower the variation of the pattern density between the first layer of pattern structure layer and the third layer of pattern structure layer, it must layout with a dummy pattern, to combine the dummy pattern layout with the formal pattern layout of the third layer of pattern layer structure layer by utilizing logic operation to let the dummy pattern added onto the informal pattern space of the formal pattern layout such that the density of new pattern layout in combination will increase from 28% to close to the required 64% and we could utilize the photolithography condition of the first pattern structure layer to put in use the third pattern structure layer without further change the photolithography process condition. This way of utilizing the fused pattern layout photomask acquired by a formal pattern layout in combination with a dummy pattern layout to manufacture various pattern structure layer of multiple layer of the semiconductor integrated circuits or the logic device with various product could avoid the trouble of fine-tuning the photolithography process and further simply the photolithography process and acquire a stable process.

[0020] Among which, the block pattern of the above-mentioned dummy pattern layout 20 is comprised of the rectangular shaped block with the side length proportion 1:1 staggered arranged; or is formed from the cross shaped formed by staggering the rectangular block with the side length proportion 2:1 arranged according to the matrix way arrangement or arranged according to the matrix way arrangement; it could also be the pattern of cross shaped formed by staggering the rectangular block with the side length proportion 3:1 arranged and according to the matrix way arrangement. Besides, the proportion of the block pattern of the dummy pattern layout with each kinds of arrangement pattern is between 25%˜45% (pattern/total area, dark/total), please refer to FIGS. 3A˜3H, the pattern density of the FIG. 3A is 25%; the pattern density of the FIG. 3B is 25%; the pattern density of the FIG. 3C is 31.25%; the pattern density of the FIG. 3D is 33.3%; the pattern density of the FIG. 3E is 33.5%; the pattern density of the FIG. 3F is 40%; the pattern density of the FIG. 3G is 41.66%; the pattern density of the FIG. 3H is 44.4%, so that the user could select various dummy pattern layout according to the requirement of various logic product (multi-pattern structure layer).

[0021] Thus, this invention uses the method of dummy pattern layout to even the density of the multi-layer pattern structure layer which not only lowers the variation of the pattern density of the logic product but also simply the parameters in the photolithography process and make its process more stable, most important it solve the trouble on mass production of device product. After the dummy pattern layout fill into the informal pattern space of the formal pattern layout, it could make the density of the pattern structure layer between the products more uniform and thus greatly lower the density variation of the pattern structure layer between the products.

[0022] To sum up, this invention is one with novel ness, progressiveness, and utilization for industries which conforms the regulations of patent pending by the patent law of R.O.C. so that we apply this pending of patent and hope that it is allowed to be a patent by you as soon as possible which is our honor.

[0023] However, the mentioned as above is just one of the preferred embodiments of this invention which is used to limit the claims of this invention in practice, all the subject change and modification according to the shape, structure, characteristic and spirit mentioned according to the claims of this invention should be included within the claims of this invention.

Claims

1. A semiconductor integrated circuit having a multi layer of pattern structure and one of the pattern structure layer comprising: a formal pattern layout having a plurality of lines and having an informal pattern space between each lines; and a dummy pattern layout comprising a plurality of blocks and sited within said informal pattern space and apart a specified distance with each neighboring line, wherein each block is arranged in said informal pattern space with the regulation of mimicy states, and is replaced by said formal pattern layout and said specified spacing when some regulation of mimicy states falls into the scope covered by said line and the specified spacing.

2. The semiconductor-integrated circuits as mentioned in claim 1, wherein said formal pattern layout and said dummy pattern layout are consisted of the same material.

3. The semiconductor integrated circuits as mentioned in claim 1, wherein said block is added to said informal pattern space by utilizing the logic operation.

4. The semiconductor integrated circuits as mentioned in claim 1, wherein said pattern is formed by staggered arrangement of the rectangular shaped block with its side's length in a 1:1 proportion.

5. The semiconductor integrated circuits as mentioned in claim 1, wherein said pattern is formed by matrix arrangement of the cross-shaped staggered rectangular shaped block with its sides length in a 2:1 proportion.

6. The semiconductor integrated circuits as mentioned in claim 1, wherein said pattern is formed by matrix arrangement of the cross-shaped staggered rectangular shaped block with its sides length in a 3:1 proportion.

7. The semiconductor integrated circuits as mentioned in claim 1, wherein said pattern is formed by matrix arrangement of the quadrate shaped block with its sides length in a 1:1 proportion.

8. The semiconductor integrated circuits as mentioned in claim 1, wherein said pattern is formed by matrix arrangement of the rectangular shaped block with its side's length in a 2:1 proportion.

9. The semiconductor integrated circuits as mentioned in claim 1, wherein the proportion of the block pattern of said dummy pattern layout is within 25%˜45% of the photomask.

10. A semiconductor integrated circuits photomask having a pattern structure and said pattern structure layer comprising: a formal pattern layout having a plurality of lines and having an informal pattern space between each lines; and a dummy pattern layout comprising a plurality of blocks and sited within said informal pattern space and apart a specified distance with each neighboring line, wherein each block is arranged in said informal pattern space with the regulation of mimicy states, and is replaced by said formal pattern layout and said specified spacing when some regulation of mimicy states falls into the scope covered by said line and the specified spacing.

11. The semiconductor integrated circuits photomask as mentioned in claim 10, wherein said formal pattern layout and said dummy pattern layout are consisted of the same material.

12. The semiconductor integrated circuits as mentioned in claim 1, wherein said block is added to said informal pattern space by utilizing the logic operation.

13. The semiconductor integrated circuits photomask as mentioned in claim 10, wherein said pattern is formed by staggered arrangement of the rectangular shaped block with its sides length in a 1:1 proportion.

14. The semiconductor integrated circuits photomask as mentioned in claim 10, wherein said pattern is formed by matrix arrangement of the cross-shaped staggered rectangular shaped block with its sides length in a 2:1 proportion.

15. The semiconductor integrated circuits photomask as mentioned in claim 10, wherein said pattern is formed by matrix arrangement of the cross-shaped staggered rectangular shaped block with its sides length in a 3:1 proportion.

16. The semiconductor integrated circuits photomask as mentioned in claim 10, wherein said pattern is formed by matrix arrangement of the quadrate shaped block with its sides length in a 1:1 proportion.

17. The semiconductor integrated circuits photomask as mentioned in claim 10, wherein said pattern is formed by matrix arrangement of the rectangular shaped block with its side's length in a 2:1 proportion.

18. The semiconductor integrated circuits photomask as mentioned in claim 10, wherein said proportion of the block pattern of the dummy pattern layout is within 25%˜45% of the photomask.

19. A manufacture method of semiconductor integrated circuits photomask comprising the following steps: providing a layout of representing the formal pattern for manufacture on the photomask having a plurality of line, and having an informal pattern space between each line within the scope of said photomask; providing a layout of representing the dummy pattern comprising a plurality of regular arranged block; mapping said dummy pattern layout onto a region covered by said photomask, and adding to set up the corresponding dummy pattern layout with a specified distance with each line in said uninformal pattern space and further complete a fused pattern layout; and completing the manufacture of the photomask with said fused pattern layout.

20. The manufacture method of semiconductor integrated circuits photomask as mentioned in claim 19, wherein said formal pattern layout and said dummy pattern layout are consisted of the same material.

21. The manufacture method of semiconductor integrated circuits as mentioned in claim 19, wherein said block is added to said informal pattern space by utilizing the logic operation.

22. The manufacture method of semiconductor integrated circuits photomask as mentioned in claim 19, wherein said pattern is formed by matrix arrangement of the cross-shaped formed by of the rectangular shaped block with its side's length in a 2:1 proportion.

23. The manufacture method of semiconductor integrated circuits photomask as mentioned in claim 19, wherein said pattern is formed by staggered arrangement of the cross-shaped staggered rectangular shaped block with its sides length in a 3:1 proportion.

24. The manufacture method of semiconductor integrated circuits photomask as mentioned in claim 19, wherein said pattern is formed by matrix arrangement of the quadrate shaped block with its sides length in a 1:1 proportion.

25. The manufacture method of semiconductor integrated circuits photomask as mentioned in claim 19, wherein said pattern is formed by matrix arrangement of the quadrate shaped block with its sides length in a 2:1 proportion.

26. The manufacture method of semiconductor integrated circuits photomask as mentioned in claim 19, wherein said proportion of the block pattern of the dummy pattern layout is within 25%˜45% of the photomask.