MULTICHIP DEVICE

Abstract

A multichip device, which achieves a normal operation and a testing operation without the needs for terminals dedicated for the testing and/or an interposer substrate, is provided. The peripheral chip also includes a switching unit for providing a switching between a normal mode that provides a first connection condition and a testing mode that provides a second coupling connection condition. The switching unit, in turn, provides connections of at least some of a plurality of outside terminals to the functional circuits, respectively, in the normal mode, and connects at least some of a plurality of outside terminals to the inside terminals in the testing mode. Thus, the normal operation and the testing operation can be carried out without the needs for the external terminals and/or the interposer substrate, which are employed for the purpose of only the testing.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic block diagram, illustrating an internal structure of a multichip device of an embodiment according to the present invention;

FIG. 2 is a detailed block diagram, illustrating the internal structure of the multichip device;

FIG. 3 is a timing chart, showing various types of signals entered to a peripheral chip during an initial setup in a normal mode;

FIG. 4 is a schematic diagram, illustrating a condition that an internal connection of the peripheral chip is controllably switched;

FIG. 5 is a schematic circuit diagram, illustrating a substantial part of the peripheral chip of the multichip device;

FIGS. 6A and 6B are schematic diagrams, illustrating a connection relation between the supplying power electrodes of the peripheral chip and the receiving power electrodes of the main chip; and

FIG. 7 is a block diagram, illustrating an internal structure of a conventional multichip device.

Claims

1. A multichip device, comprising: a first terminal;a first circuit chip having a second terminal; anda second circuit chip having a third terminal connected to said first terminal, a fourth terminal connected to said second terminal, and a first functional circuit,wherein said second circuit chip includes a switching unit that provides a switching between a first connection status and a second connection status, said first connection status providing a condition that said third terminal is connected to said first functional circuit, and said second connection status providing a condition that said third terminal is connected to said fourth terminal.

2. The multichip device according to claim 1, wherein said switching unit connects between said second terminal and said first functional circuit in said first connection status.

3. The multichip device according to claim 2, wherein said second circuit chip has additionally a second functional circuit,wherein said switching unit connects said third terminal to said first functional circuit and connects said fourth terminal to said second functional circuit in said first connection status, andwherein said switching unit connects said third terminal to said fourth terminal in said second connection status.

4. The multichip device according to claim 3, wherein said multichip device includes a plurality of said first terminals,wherein said first circuit chip has a plurality of said second terminals,wherein said second circuit chip includes a plurality of said third terminals, a plurality of said fourth terminals a plurality of said first functional circuits and a plurality of said second functional circuits,wherein said switching unit connects at least some of a plurality of said third terminals to said first functional circuit respectively and connects at least some of a plurality of said fourth terminals to said second functional circuits respectively in said first connection status, andwherein said switching unit connects at least some of a plurality of said third terminals having cancelled the connection with said first functional circuits to said fourth terminals having cancelled the connection with said second functional circuits respectively in said second connection status.

5. The multichip device according to claim 1, wherein said switching unit provides a switching a direction of a signal transmission between said third terminal and said fourth terminal that are connected in at least said second connection status.

6. The multichip device according to claim 1, wherein a signal for switching between said first connection status and said second connection status is entered to said switching unit from said first terminal through said third terminal.

7. The multichip device according to claim 6, wherein a first setup data for said first connecting status is entered to said switching unit from said second terminal through said fourth terminal by said first circuit chip, and a second setup data for said second connecting status is entered to said switching unit from said first terminal through said third terminal.

8. The multichip device according to claim 7, wherein said multichip device selectively includes multiple types of said first circuit chips mounted thereon that output said first setup data corresponding to types of the setup.

9. The multichip device according to claim 8, wherein said second circuit chips include a plurality of supplying power electrodes in positions opposite to said first circuit chips,wherein said multiple types of said first circuit chips include receiving power electrodes in positions opposite to said second circuit chips, andwherein a plurality of said supplying power electrodes are selectively connected to said receiving power electrodes corresponding to types of said first circuit chips.

10. The second circuit chip mounted on the multichip device according to claim 1, wherein said second circuit chip includes: said third terminal connected to said first terminal;said fourth terminal connected to said second terminal;said first functional circuit; andsaid switching unit that provides a switching between said first connection status and said second connection status, said first connection status providing a condition that said third terminal is connected to said first functional circuit, and said second connection status providing a condition that said third terminal is connected to said fourth terminal.

11. A device base member including said first circuit chip of the multichip device according to claim 8, wherein said device base member comprises said first terminal, and said second circuit chip mounted thereon,wherein said first terminal is connected to said third terminal of said second circuit chip, andwherein multiple types of said first circuit chip are selectively mounted thereon.

12. The first circuit chips mounted on the multichip device according to claim 8, wherein said first circuit chip includes said second terminal, andwherein multiple types of said first circuit chips are provided, and said first circuit chips output said first setup data to said second circuit chips corresponding to the types thereof.

13. A multichip set, comprising: said device base member according to claim 11; andsaid multiple types of first circuit chips according to claim 12 selectively mounted on said device base member.

14. A method for testing said multichip device according to claim 7, including: entering a signal for switching to said second connection status to said second circuit chip from at least one of said first terminals;entering said second setup data for providing said second connection status to said second circuit chip from at least one of said first terminals; andtesting said first circuit chip through said first terminal connected to said second terminal via said second circuit chip, corresponding to said signal for switching and said second setup data.

15. A method for driving the multichip device according to claim 7, including: entering a signal for switching to said first connection status to said second circuit chip from at least one of said first terminals; andentering said first setup data to said second circuit chip from at least one of said second terminals by said first circuit chip.

16. A method for manufacturing the multichip device according to claim 8, comprising: selectively mounting said multiple types of first circuit chips on the device base member;appropriately connecting said second terminals of said first circuit chip mounted on said device base member to said first terminal and said second circuit chip; andsetting up said first setup data in said first circuit chip.