This application is based upon and claims the benefit of priority of Japanese Patent Application No. 2010-176126, filed on Aug. 5, 2010, the entire contents of which are incorporated herein by reference.
Embodiments discussed herein are related to a multilayer wiring board and a method for evaluating a multilayer wiring board.
In recent years, the wiring density of printed wiring boards mounted in electronic devices has become higher. In addition, in a printed wiring board in which multilayer interconnection is adopted, the thickness of interlayer insulation films has become smaller. For mounting of such a printed wiring board in an electronic device, it is necessary to evaluate the reliability of the printed wiring board in a short period of time.
Until now, a method has been used in which the reliability of a printed wiring board is evaluated by applying voltage between wires that are insulated from each other and by measuring a decrease in the insulation resistance using patterns for evaluating the reliability of printed wiring boards.
Now, a method for evaluating the reliability of printed wiring boards in the related art will be described with reference to
In an evaluation method in the related art, an insulation resistance tester is connected between the test patterns 2A and 2B, and the insulation resistance between the test patterns 2A and 2B is measured. Next, voltage is applied between the test patterns 2A and 2B for a certain period of time using the power supply 4. After that, the insulation resistance tester is connected between the test patterns 2A and 2B, and the insulation resistance between the test patterns 2A and 2B is measured. In the evaluation method in the related art, the reliability of the printed wiring board 10 is evaluated by measuring the insulation resistance before and after voltage is applied between the test patterns 2A and 2B. In JP-A-2000-304801, a method is disclosed in which a test apparatus is stopped if a failure is detected during an insulation test such as that described above.
In addition, in JP-A-3-33665, a method is disclosed in which time-domain reflectometry (TDR) measurement is adopted in order to inspect conductors formed on a printed wiring board.
In the evaluation method in which comb-shaped test patterns are used, which is illustrated in
In addition, even if a TDR method is performed using the comb-shaped test patterns illustrated in
According to an embodiment of the invention, a method for evaluating a multilayer wiring board is provided. The multilayer wiring board includes an inner-layer on which a test pattern is disposed. The method includes arranging a plurality of first patterns and a second pattern of the test pattern such that the first patterns have a comb-like shape opposed to one another, and the second pattern has an unbranched shape extending between the opposed first patterns. A voltage is applied between the first patterns and the second pattern. An impedance of the second pattern is measured.
Certain objects and advantages of certain embodiments of the invention will be realized and attained at least by the elements, features, and combinations particularly pointed out in the claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are not restrictive of the invention.
An evaluation board used to evaluate the insulation performance of a board included in a printed wiring board, and a method for evaluating the board using the evaluation board will be described on the basis of an embodiment.
First, an evaluation board (hereinafter referred to as a “board”) will be described with reference to
Now, the test pattern layer 20 according to this embodiment will be described with reference to
In addition, in the test pattern layer 20, first through holes 50 and 52, a second through hole 54, and a third through hole 56 are formed. The first through holes 50 and 52 are connected to the first test patterns 22. The second through hole 54 is connected to the second test pattern 24. The third through hole 56 is used, as described below, to electrically connect the continuous solid pattern layers 30 and 40, which sandwich the test pattern layer 20. The third through hole 56 is disposed not to be electrically connected to the first test patterns 22 or the second test pattern 24 formed on the test pattern layer 20.
Surfaces of inner walls of the first through holes 50 and 52, the second through hole 54, and the third through hole 56 are through-hole plated.
Next, the continuous solid pattern layers 30 and 40 according to this embodiment will be described with reference to
Around the first through holes 50 and 52, and the second through hole 54, the gaps 50a, 52a and 54a, respectively, can be provided. Therefore, the first through holes 50 and 52, and the second through hole 54 are not electrically connected to the solid pattern electrodes 32 and 42. On the other hand, no gap is provided around the third through hole 56, and therefore the third through hole 56 is electrically connected to the solid pattern electrodes 32 and 42.
Next, the through-hole connecting layer 60 according to this embodiment will be described with reference to
As illustrated in
Now, the layered structure of the board 10 according to this embodiment will be described with reference to
Although the board 10 includes a single test pattern layer 20, a method for evaluating a board, which will be described below, may be applied in a case where the board 10 includes multiple test pattern layers 20.
Next, a method for evaluating a board using the above-described board 10 will be described. In the method according to this embodiment, a defect in the test pattern layer 20 is located using a TDR method. Now, the outline of the method will be described with reference to
First, voltage is applied between the first test patterns 22 and the second test pattern 24 (S101). As an example of specific test conditions, a voltage of 60 V is applied between the first test patterns 22 and the second test pattern 24 for 500 hours under a temperature of 85° C. and a humidity of 85%.
Now, a method for applying voltage between the first test patterns 22 and the second test pattern 24 will be described with reference to
The test apparatus 80 applies voltage to the terminals 72 and has a pulse generator and an oscilloscope in order to measure the impedance of the second test pattern 24 using the TDR method as described below.
The three terminals 72 are inserted into the first, second, and third through holes 50, 54, and 56, respectively, in the board 10, which has been described with reference to
The description returns to
Next, a location of a defect is specified based on the impedance variations measured by the TDR method (S103 of
Now, changes (variations) in the impedance measured using the TDR method will be described with reference to
Specifically, when an insulation failure has not occurred in the second test pattern 24, the value of the measured impedance is within a certain range. Therefore, as illustrated in
On the other hand, when an insulation failure has occurred in the second test pattern 24, the value of the measured impedance is not within an acceptable range. Therefore, as illustrated in
Therefore, by measuring the impedance of the second test pattern 24 using the TDR method, it is possible to determine whether or not an insulation failure has occurred in the second test pattern 24.
Furthermore, as illustrated in
As described above, in the method for evaluating a board according to this embodiment, the insulation performance is evaluated using the second test pattern 24, which is formed on the test pattern layer 20 and has no branches. Therefore, in a case where the test pattern layer 20 is sandwiched between the solid pattern layers 30 and 40 and therefore it is difficult to visually inspect an insulation failure that has occurred in the test pattern layer 20, it is possible to locate a defect point at which the insulation failure has occurred.
Although the TDR method is used in the above-described embodiment to locate a defect in the test pattern layer 20, the method for locating a defect is not limited to the TDR method. In the following modification, another example of locating a defect will be described.
First, impedance corresponding to the distance from an end of the second test pattern 24 is measured (S201). In S201, for example, a curve can be obtained that represents the relationship between the impedance and the distance from the end of the second test pattern 24.
Next, a voltage is applied between the first test patterns 22 and the second test pattern 24 (S202). As an example of specific test conditions, a voltage of 60 V is applied between the first test patterns 22 and the second test pattern 24 for 500 hours under a temperature of 85° C. and a humidity of 85%.
In addition, at the same time as S202, current flowing between the first test patterns 22 and the second test pattern 24 is measured (S203). For example, when the insulation resistance between the first test patterns 22 and the second test pattern 24 has a normal value (for example, 100 MΩ or more), the current flowing between the first and second test patterns has a certain maximum value (for example, 0.6 μA or less).
Now, suppose that an insulation failure has occurred between the first test patterns 22 and the second test pattern 24. In this case, the insulation resistance between the first and second test patterns has a certain maximum value (for example, 100 kΩ or less), and the current flowing between the first and second test patterns has a certain maximum value (for example, 0.6 mA or more). Therefore, if the current flowing between the first and second test patterns has a certain value or a value higher than the certain value, it can be determined that an insulation failure has occurred between the first and second test patterns.
Next, as is the case with S201, impedance corresponding to the distance from an end of the second test pattern 24 is measured (S204). As a result of S204, for example, a curve can be obtained that represents the relationship between the impedance and the distance from the end of the second test pattern 24.
Next, the impedances measured in steps S201 and S204 are compared in order to locate a defect at which an insulation failure has occurred (S205). Specifically, the curves obtained in steps S201 and S204 are compared.
If no insulation failure has occurred in S202, the curves obtained in steps S201 and S204 are substantially the same. If an insulation failure has occurred in S202, when a measured point is further from the end of the second test pattern 24 than the defect point, the curves are different from each other, while the curves are substantially the same when a measured point is closer to the end of the second test pattern 24 than a defect point. Therefore, by comparing the curves obtained in steps S201 and S204, it is possible to locate a defect point at which an insulation failure has occurred.
In S203, if the value of the current flowing between the first test patterns 22 and the second test pattern 24 is within a certain range (for example, 0.6 μA or less), it can be determined that no insulation failure has occurred, and steps S204 and S205 may be omitted.
As described above, by a method in which the impedance corresponding to the distance from an end of the second test pattern 24 is measured before and after application of voltage and the impedance curves are compared as in this modification, too, it is possible to locate a defect point as in the above-described embodiment.
All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the invention and the concepts contributed by the inventors to further the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Although the embodiments of the invention have been described in detail, it will be understood by those of ordinary skill in the relevant art that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention as set forth in the claims.
Number | Date | Country | Kind |
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2010-176126 | Aug 2010 | JP | national |