Claims
- 1. A digital signal processor for processing digital signals in response to instruction data, where said digital signals include a set of comprising:
first data bus for reading and writing data between a first memory and a register bank; second data bus for reading and writing data between a second memory and said register bank; third data bus for reading and writing data between a third memory and said register bank, wherein said first data bus, said second data bus, and said third data bus are simultaneously controllable with a single instruction.
- 2. The digital signal processor as set forth in claim 1 further comprising a processing unit for processing data stored in said register bank.
- 3. The digital signal processor as set forth in claim 1 further comprising:
instruction fetch unit for fetching instructions of variable length, said instructions requesting a set of operations; instruction decoder for decoding said instructions of variable length and for causing said set of operations to be performed.
- 4. The digital signal processor as set forth in claim 1 further comprising:
second processing unit for processing data in said register bank simultaneously with said first processing unit.
- 5. A digital signal processor for processing a digital signal comprising:
a plurality of processing units for generating result data in response to first input data and second input data; first data bus for transmitting said first input data to said processing unit; second data bus for transmitting second input data to said processing unit; and third data bus for transmitting said result data, wherein, through control by a single instruction, respective ones of said first, second, and third data buses may be simultaneously coupled individually to respective ones of said plurality of processing units by a register bank.
- 6. The digital signal processor as set forth in claim 5 further comprising:
first memory system coupled to said first bus for reading said first input data; second memory system coupled to said second bus for reading said second input data; and third memory system coupled to said third bus for writing said result data.
- 7. The digital signal processor as set forth in claim 5 wherein said first bus is narrower than said third bus.
- 8. The digital signal processor as set forth in claim 5 wherein said first bus and second bus are narrower than said third bus.
- 9. The digital signal processor as set forth in claim 5 further comprising:
first register coupled to said first bus, said second bus, said third bus, and said processing unit, for storing said first data and said second data; second register for storing said result data; and second processing unit coupled to said second register for processing said result data.
- 10. The digital signal processor as set forth in claim 9 further comprising a control system, for controlling said first data bus, said second data bus, and said third data bus.
- 11. The digital signal processor as set forth in claim 9 wherein said first processing unit is a multiply-accumulate unit, and said second processing unit is a arithmetic logic unit.
Parent Case Info
[0001] The present application is a divisional of U.S. patent application Ser. No. 09/044,086, filed on Mar. 18, 1999, and assigned to the assignee of the present application.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09044086 |
Mar 1998 |
US |
Child |
09876189 |
Jun 2001 |
US |