Patent Application
20250211170
Embodiments of the subject matter described herein relate generally to radio frequency (RF) amplifiers, and more particularly to multiple-path amplifiers (e.g., Doherty amplifiers) and amplifier modules.
The Doherty power amplifier is ubiquitous within cellular base station transmitters because the Doherty power amplifier architecture is known to improve back-off efficiency for spectrally efficient modulations, when compared with other types of amplifiers. The high efficiency of the Doherty power amplifier makes the architecture desirable for current and next-generation wireless systems. However, the trends toward higher and higher operational frequencies (e.g., in the gigahertz (GHz) range) and increased system miniaturization presents challenges to conventional Doherty power amplifier architectures, particularly in the area of semiconductor package design. As frequencies continue to increase, effective Doherty power amplifier implementations are needed that enable high efficiency operation in low cost and small footprint solutions.
A more complete understanding of the subject matter may be derived by referring to the detailed description and claims when considered in conjunction with the following figures, wherein like reference numbers refer to similar elements throughout the figures.
Embodiments of the inventive subject matter described herein include multiple-stage, multiple-path power amplifiers (e.g., including but not limited to Doherty amplifiers), which are configured to amplify radio frequency (RF) signals. According to one or more embodiments, a multiple-stage, multiple-path power amplifier includes an amplifier substrate and a packaged power amplifier device (or more generally, a “packaged semiconductor device”) coupled to a top surface of the amplifier substrate. The packaged power amplifier device includes a first amplifier die (e.g., a driver amplifier die) corresponding to a first amplification stage (e.g., a driver stage), and a set of second amplifier dies (e.g., carrier and peaking amplifier dies) that together correspond to a second amplification stage. The packaged power amplifier device also includes an interface for signal communication with an external power splitter that is coupled to the top surface of the amplifier substrate. More specifically, the package interface includes a plurality of leads, where a first one of these leads is coupled to the output of the first amplifier die (e.g., the output of the driver amplifier die). Second and third ones of these leads are coupled to the inputs to the second amplifier dies (e.g., the inputs of the carrier and peaking dies). On the amplifier substrate, an input of the power splitter is coupled to the first lead, and outputs of the power splitter are coupled to the second and third leads, respectively.
Accordingly, the arrangement may provide a power amplifier lineup with an in-package driver amplifier that provides a pre-amplified signal through the first lead to the splitter input. The splitter divides the power of the pre-amplified signal into first and second signals (e.g., carrier and peaking signals), and provides those signals through the second and third leads to the in-package carrier and peaking amplifiers. Accordingly, the power amplifier lineup is “partially integrated” in that the first and second amplification stages (or the driver, carrier, and peaking dies) all are integrated within a single packaged semiconductor device, while the interstage power splitter is located outside of the packaged semiconductor device and accessed through leads of the packaged semiconductor device. In some embodiments, an output transformer at the output of the amplifier also may be located outside of the packaged semiconductor device on the amplifier substrate.
This arrangement enables the size of a packaged power amplifier device to be reduced (e.g., by about 30 percent, more or less) when compared with a power amplifier in which the power splitter and/or the output transformer are integrated within the power amplifier package with the driver, carrier, and peaking amplifier dies. By moving the power splitter and/or the output transformer outside of the power amplifier package, the cost of the packaged power amplifier device also is reduced.
The multiple-stage power amplifier embodiments described herein may be utilized to implement any of a variety of different types of power amplifiers. To provide concrete examples that will help to convey the details of the inventive subject matter, two examples of Doherty power amplifiers are described herein. Each Doherty amplifier embodiment includes an in-package driver amplifier stage, which is coupled through an external power splitter to in-package final carrier and peaking amplifier stages. However, those of skill in the art will understand, based on the description herein, that the inventive subject matter may be utilized in systems that implement other types of multiple-stage amplifiers, as well. Accordingly, the use of Doherty power amplifiers in the example embodiments below is not meant to limit application of the inventive subject matter only to Doherty power amplifiers, as the inventive subject matter may be used in other types of multiple-stage power amplifiers, as well.
Prior to describing various physical implementations of power amplifiers, reference is made to
Power amplifiers 100, 200 each essentially include a multiple-stage Doherty amplifier implemented on an amplifier substrate 180 (e.g., amplifier substrate 680,
As will be discussed in more detail later, each Doherty amplifier 100, 200 includes circuitry disposed on an amplifier substrate 180 or disposed within a packaged power amplifier device 182, 282. Importantly, according to one or more embodiments, the amplification components (e.g., driver, carrier, and peaking dies 114, 132, 152) of the Doherty amplifier 100, 200 are included within the packaged power amplifier device 182, 282, while an interstage power splitter 120 is disposed on the amplifier substrate 180. As will be explained in more detail later, the external, interstage power splitter 120 is electrically coupled to the amplification components through an interface for signal communication that includes a plurality of device terminals (e.g., device terminals 104-108, 302, 304-308,
The amplifier substrate 180 may include, for example, a printed circuit board (PCB) or other suitable substrate. The packaged power amplifier device 182, 282 may be a discrete, surface-mountable device that is configured to be coupled to a mounting surface of the amplifier substrate 180. More particularly, distal ends of conductive device leads 104-109 (e.g., leads 302, 304-312,
Each Doherty amplifier 100, 200 includes an amplifier input terminal 101 on the amplifier substrate 180, an amplifier output terminal 102 on the amplifier substrate 180, a driver amplifier that includes a driver amplifier die 114 (e.g., die 314,
When incorporated into a larger RF system, the amplifier input terminal 101 is coupled to an RF signal source, and the amplifier output terminal 102 is coupled to a load 190 (e.g., an antenna or other load). The RF signal source provides an input RF signal, which is an analog signal that includes spectral energy that typically is centered around one or more carrier frequencies. Fundamentally, the Doherty amplifier is configured to amplify the input RF signal received at the amplifier input terminal 101, and to produce an amplified output RF signal at the amplifier output terminal 102.
According to an embodiment, the input RF signal received at the amplifier input terminal 101 is conveyed through a first impedance matching circuit 110 on the amplifier substrate 180 to a device input lead 104 of the packaged power amplifier device 182, 282. The input RF signal is then amplified through a driver amplifier within the packaged power amplifier device 182, 282. The driver amplifier corresponds to a first amplifier stage of the Doherty amplifier 100, 200.
The driver amplifier includes a driver input impedance matching circuit 113, the driver amplifier die 114, and a driver output impedance matching circuit 117. The driver input impedance matching circuit 113 is coupled to the device substrate 183 between the device input lead 104 and an input terminal 115 (e.g., gate terminal) of the driver amplifier die 114. Together, the first impedance matching circuit 110, a small inductance provided by the device input lead 104, and the driver input impedance matching circuit 113 (collectively considered to be a “driver input impedance matching circuit”) are configured to transform the gate impedance of the power transistor within die 114 to a more desirable system level impedance (e.g., 50 ohms).
According to one or more embodiments, the driver amplifier die 114 is coupled to a first heat dissipation structure 161 (e.g., heat dissipation structure 361,
Now back on the amplifier substrate 180, the pre-amplified RF signal is conveyed through an additional impedance matching circuit 118 on the amplifier substrate 180 to an input 121 of the power splitter 120. The power splitter 120 is configured to divide the pre-amplified RF signal received at input 121 into first and second pre-amplified RF signals (or carrier and peaking signals), which are provided at power splitter outputs 122, 123, respectively. According to an embodiment, the power splitter 120 is configured to impart a phase difference (e.g., about a 90 degree phase difference) between the first and second pre-amplified RF signals. In such an embodiment, at outputs 122 and 123, the carrier and peaking signals may be about 90 degrees out of phase from each other.
When Doherty amplifier has a symmetrical configuration (i.e., a configuration in which the power transistors in dies 132, 152 are substantially identical in size), the power splitter 120 may divide or split the input RF signal received at the input 121 into two signals that are very similar with, in some embodiments, equal power. Conversely, when Doherty amplifier has an asymmetrical configuration (i.e., a configuration in which one of the power transistors, typically the power transistor in the peaking amplifier die 152, is significantly larger), the power splitter 120 may output carrier and peaking signals having unequal power.
The outputs 122, 123 of the power splitter 120 are connected through phase shifting circuits 124, 126 on the amplifier substrate 180 to a carrier input lead 106 and a peaking input lead 107 of the packaged power amplifier device 182, 282. Now back within the packaged power amplifier device 182, 282, the carrier input lead 106 is coupled to the carrier amplifier path 130, and the peaking input lead 107 is coupled to the peaking amplifier path 150. As will be described in more detail below, the carrier amplifier path 130 is configured to amplify the pre-amplified carrier signal from the power splitter 120, resulting in an amplified carrier signal. Similarly, the peaking amplifier path 150 is configured to amplify the pre-amplified peaking signal from the power splitter 120, resulting in an amplified peaking signal. The carrier and peaking amplifiers correspond to second amplifier stages of the Doherty amplifier 100, 200.
The carrier amplifier path 130 includes first and second carrier impedance matching circuits 127, 131 and the carrier amplifier die 132. The first and second carrier impedance matching circuits 127, 131 are coupled between the carrier input lead 106 and an input terminal 138 (e.g., gate terminal) of the carrier amplifier die 132. More specifically, the first carrier impedance matching circuit 127, which is coupled to the device substrate 183, represents a first portion of an overall input impedance matching circuit for the carrier amplifier die 132, and the second carrier impedance matching circuit 131, which is coupled to a second heat dissipation structure 162 (e.g., heat dissipation structure 362,
According to one or more embodiments, the carrier amplifier die 132 also is coupled to the second heat dissipation structure 162, which is configured to convey heat produced by the carrier amplifier die 132 to the above-mentioned system heat sink (e.g. heat sink 916 or 1016,
The peaking amplifier path 150 includes first and second peaking impedance matching circuits 128, 151 and the peaking amplifier die 152. The first and second peaking impedance matching circuits 128, 151 are coupled between the peaking input lead 107 and an input terminal 158 (e.g., gate terminal) of the peaking amplifier die 152. More specifically, the first peaking impedance matching circuit 128, which is coupled to the device substrate 183, represents a first portion of an overall input impedance matching circuit for the peaking amplifier die 152, and the second peaking impedance matching circuit 151, which is coupled to the first heat dissipation structure 161 (e.g., heat dissipation structure 361,
According to one or more embodiments, the peaking amplifier die 152 also is coupled to the first heat dissipation structure 161, which is configured to convey heat produced by the peaking amplifier die 152 to the above-mentioned system heat sink (e.g. heat sink 916 or 1016,
According to an embodiment, the peaking amplifier die 152 and the carrier amplifier die 132 are coupled to the first and second heat dissipation structures 161, 162 so that signal paths through the peaking amplifier die 152 and the carrier amplifier die 132 extend in a first direction, indicated by arrows 130 and 150, that is parallel to a first axis 197 of Cartesian coordinate system 194. Conversely, the driver amplifier die 114 may be coupled to the first heat dissipation structure 161 so that the signal path through the driver amplifier die 114 extends in a second direction that is parallel to a second axis 195 of Cartesian coordinate system 194 (i.e., an axis orthogonal to the first axis 197). This arrangement of dies 114, 132, 152 facilitates a compact arrangement of the components of the packaged power amplifier device 182, 282. Further, coupling the driver and peaking amplifier dies 114, 152 to the same heat dissipation structure 161 enables a relatively compact device by eliminating the need for separate heat dissipation structures for such dies.
Each amplifier die 114, 132, 152 includes one or more integrated power transistors, where each power transistor includes a control terminal (e.g., a gate terminal) and first and second current-carrying terminals (e.g., a drain terminal and a source terminal). In a single-stage device, which would include a single power transistor, the control terminal is electrically connected to the input terminal 115, 138, 158, one of the current-carrying terminals (e.g., the drain terminal) is electrically connected to the output terminal 116, 139, 159, and the other current-carrying terminal (e.g., the source terminal) is electrically connected through the first or second heat dissipation structure 161, 162 to a ground reference (or another voltage reference). Conversely, a two-stage amplifier would include two power transistors coupled in series between each input terminal 115, 138, 158 and each output terminal 116, 139, 159.
In Doherty power amplifiers 100 and 200, the output terminal 139 of the carrier amplifier die 132 and the output terminal 159 of the peaking amplifier die 152 are coupled to a power combining node 176 or 276 through an output combining network 170 or 270, in accordance with various embodiments. Referring first to amplifier 100 in
According to an embodiment, output combining network 170 includes one or more transmission lines 172 formed on or within the device substrate 183, along with connections 171, 175 between opposite ends of the transmission line(s) 172 and the carrier and peaking output terminals 139, 159. For example, the total electrical length of the output combining network 170 may be about lambda/4 (λ/4) (i.e., about 90 degrees) at the fundamental frequency of operation, f0, of the amplifier 100. Accordingly, the output combining network 170 is configured to impart about a 90 degree relative phase shift to the amplified carrier signal between the RF output terminal 139 and the power combining node 176 at the fundamental frequency.
According to the embodiment illustrated in
Referring now to amplifier 200 in
The carrier-side phase delay circuit includes connection 271 and one or more first transmission lines 272 between the carrier output terminal 139 and the combining node 276. Similarly, the peaking-side phase delay circuit includes connection 274 and one or more second transmission lines 273 between the peaking output terminal 159 and the combining node 276. The first and second transmission lines 272, 273 are formed on or within the device substrate 183. According to an embodiment, the total electrical length of the carrier-side phase delay circuit may be about lambda/4 (λ/4) (i.e., about 90 degrees) at the fundamental frequency of operation, f0, of the amplifier 200. Accordingly, the carrier-side phase delay circuit is configured to impart about a 90 degree relative phase shift to the amplified carrier signal between the RF output terminal 139 and the power combining node 276 at the fundamental frequency. Conversely, the total electrical length of the peaking-side phase delay circuit may be about lambda/2 (λ/2) (i.e., about 180 degrees) at the fundamental frequency of operation, f0, of the amplifier 200. Accordingly, the peaking-side phase delay circuit is configured to impart about a 180 degree relative phase shift to the amplified peaking signal between the RF output terminal 159 and the power combining node 276 at the fundamental frequency.
Again, in amplifier 200, the output combining network 270 is configured so that the amplified carrier and peaking RF signals combine in phase at the combining node 276. Because the output combining network 270 imparts about a 90 degree relative phase shift to the amplified carrier signal between the carrier output terminal 139 and the combining node 276, while also imparting about a 180 degree relative phase shift to the amplified peaking signal between the peaking output terminal 159 and the combining node 276, the combining topology shown in
According to one or more alternate embodiments, in amplifier 200, the output combining network 270 alternatively may be configured so that the total electrical length of the carrier-side phase delay circuit (e.g., connection 271 and transmission line 272) may be between about lambda/8 (λ/8) (i.e., about 45 degrees) and about lambda/4 (λ/4) (i.e., about 90 degrees), and the total electrical length of the peaking-side phase delay circuit (e.g., connection 274 and transmission line 273) may be between about 3×lambda/2 (3λ/4) (i.e., about 145 degrees) and about lambda/2 (λ/2) (i.e., about 180 degrees) at the fundamental frequency of operation, f0, of the amplifier 200. In such embodiments, the combing node impedance may be a complex number. Such a topology may be referred to as a A-CCL topology. Compared with the above-described 90/0 topology, this topology may exhibit better wideband performance, while keeping the footprint of the amplifier 200 smaller than the above-described 90/180 topology.
In both Doherty power amplifiers 100, 200, the combining node 176, 276 is electrically coupled to an output lead 108 of the packaged power amplifier device 182, 282. Back on the amplifier substrate 180, an output impedance transformer 178 is coupled between the output lead 108 and the RF output terminal 102. Ultimately, the output transformer 178 functions to present proper load impedances to each of the carrier and peaking amplifier dies 132, 152. The resulting amplified RF output signal is produced at RF output terminal 102, to which an output load 190 (e.g., an antenna) is connected.
In addition to the above-described and illustrated components, power amplifier 100 also may include gate and/or drain bias circuitry 192 on the amplifier substrate 180. The gate and/or drain bias circuitry 192 may receive bias voltages from external sources through additional * 103 on the amplifier substrate 180, and may convey those bias voltages to additional leads 109 of the packaged power amplifier device 182, 282. Although not shown in
Each Doherty power amplifier 100, 200 is configured so that the carrier amplifier path 130 provides amplification for relatively low level input signals, and both the carrier and peaking amplification paths 130, 150 operate in combination to provide amplification for relatively high level input signals. This may be accomplished, for example, by biasing the carrier amplifier 132 so that the carrier amplifier 132 operates in a class AB mode, and biasing the peaking amplifier 152 so that the peaking amplifier 152 operates in a class C mode. Accordingly, the bias voltages provided to the gates and/or drains of the driver amplifier die 114 may configure the driver amplifier to operate in a class AB mode, while the bias voltages provided to the gates and/or drains of the carrier and peaking amplifier dies 132, 152 may be provided to configure the carrier and peaking amplifiers to operate in class AB mode and class C mode, respectively.
Although not shown in
An example of a physical implementation of the packaged power amplifier device 282 of
Packaged power amplifier device 300 includes a device substrate 383 (e.g., substrate 183,
As will be described in more detail below, the leads 302, 304-312 and a plurality of components are coupled to the mounting surface 384 of the device substrate 383, and the power amplifier dies 314, 332, 352 are coupled to the heat dissipation structures 361, 362. As shown in
Lower or proximal ends of the leads 302, 304-312 are coupled to conductive features on the mounting surface 384 of the device substrate 383. The leads 302, 304-312 extend perpendicularly from the mounting surface 384 to their upper or distal ends. The upper or distal ends of the leads 302, 304-312 are exposed at the contact surface 381 (i.e., leads 302, 304-312 are exposed at the top surface of the encapsulant material 386). Conductive attachment material 399 (e.g., solder balls, solder paste, or conductive adhesive) is disposed on the exposed distal ends of the leads 302, 304-312 to facilitate electrical and mechanical attachment of the device 300 to a system substrate (e.g., amplifier substrate 180 or 680,
In the embodiment illustrated in
As depicted in
Each of the various conductive layers 394-398 may have a primary purpose, and also may include conductive features that facilitate signal and/or voltage/ground routing between other layers. Although the description below may indicate a primary purpose for each of the conductive layers 394-398, it should be understood that the layers (or their functionality) may be arranged differently from the particular arrangement best illustrated in
For example, in an embodiment, the patterned conductive layer 394 at the mounting surface 384 of the device substrate 383 may primarily function as a signal conducting layer. More specifically, layer 394 includes a plurality of conductive features (e.g., conductive bond pads and traces) that serve as attachment points for various discrete components, and also provide electrical connectivity between the dies 314, 332, 352 and the other discrete components. In addition, layer 394 may include a plurality of conductive bond pads that are specifically designated for attachment of electrically conductive signal, bias, and/or ground leads (e.g., leads 302, 304-312).
Other patterned conductive layers 395-397 may function as an RF ground layer, a signal routing layer, and/or a layer that conveys bias voltages to the power transistors within the dies 314, 332, 352, in various embodiments. According to an embodiment, the conductive layer 398 at the bottom surface 385 of the device 300 may function as a system ground layer. Conductive vias extend through the dielectric layers 390-393 to electrically connect the various conductive layers 394-398.
According to an embodiment, the device substrate 383 also includes one or more heat dissipation structures 361, 362, which extend between the top and bottom surfaces 384, 385 of the device substrate 383. In some embodiments, the heat dissipation structures 361, 362 may be joined together by a thermal base structure 363 to form a single integrated thermal structure 360. In such an embodiment, the thermal structure 360 includes the thermal base structure 363 and two pedestals corresponding to the two portions of the heat dissipation structures 361, 362 that extend from the base structure 363 to the mounting surface 384 of the device substrate 383. In an alternate embodiment, heat dissipation structures 361, 362 may be separate structures (e.g., thermal base structure 363 may be excluded), as indicated in
Either way, the first heat dissipation structure 361 has a first thermal surface 365 that is exposed at the mounting surface 384 of the device substrate 383, the second heat dissipation structure 362 has a second thermal surface 367 that is exposed at the mounting surface 384 of the device substrate 383, and the first and second thermal surfaces 365, 367 are physically separated by a portion of the mounting surface 384 of the device substrate 383 that is present between the first and second thermal surfaces 365, 367. Sidewalls (not numbered) of the heat dissipation structures 361, 362 are separated by portions of the device substrate 383 (e.g., portions of dielectric layers 390-393, as shown in
According to an embodiment, driver and peaking amplifier dies 314 and 352 (e.g., dies 114, 152,
The driver amplifier die 314 includes a power transistor that is integrally formed within the die 314, and that functions as a driver amplifier. The driver amplifier die 314 has an input terminal 315 coupled to the control terminal (e.g., gate terminal) of the integrated power transistor, and an output terminal 316 that is coupled to the output terminal (e.g., drain terminal) of the integrated transistor. The driver amplifier die 314 is coupled to the first thermal surface 365 so that a first signal path through the driver amplifier die 314 (i.e., a signal path between terminals 315, 316) extends in a first direction that is parallel to the first axis 195 of Cartesian coordinate system 194.
Further, the peaking amplifier die 352 includes a power transistor that is integrally formed within the die 352, and that functions as a first final-stage amplifier. The peaking amplifier die 352 has an input terminal 358 coupled to the control terminal (e.g., gate terminal) of the integrated power transistor, and an output terminal 359 that is coupled to the output terminal (e.g., drain terminal) of the integrated power transistor. The peaking amplifier die 352 is coupled to the first thermal surface 365 so that a peaking signal path through the peaking amplifier die 352 (i.e., a signal path between leads 358, 359) extends in a second direction that is parallel to the second axis 197 of Cartesian coordinate system 194. As mentioned previously, coupling the driver and peaking amplifier dies 314, 352 to the same heat dissipation structure 361 enables a relatively compact module by eliminating the need for separate heat dissipation structures for such dies.
Similarly, the carrier amplifier die 332 includes a power transistor that is integrally formed within the die 332, and that functions as a second final-stage amplifier, where the first and second final-stage amplifiers are arranged in parallel with each other. The carrier amplifier die 332 has an input terminal 338 coupled to the control terminal (e.g., gate terminal) of the integrated power transistor, and an output terminal 339 that is coupled to the output terminal (e.g., drain terminal) of the integrated power transistor. The carrier amplifier die 352 is coupled to the second thermal surface 367 so that a carrier signal path through the carrier amplifier die 332 (i.e., a signal path between leads 338, 339) also may extend in the second direction, which is parallel to the second axis 197 of Cartesian coordinate system 194. In an alternate embodiment, the carrier amplifier die 332 may be rotated by 90 degrees so that the carrier signal path extends in the first direction (i.e., a direction parallel to the first axis 195).
According to various embodiments, the above-referenced power transistors that are integrally formed within the driver amplifier die 314, the carrier amplifier die 332, and the peaking amplifier die 352 each may be implemented, for example, using a field effect transistor (FET), such as laterally-diffused metal oxide semiconductor (LDMOS) FETs or high electron mobility transistors (HEMTs). For example, the power transistors within the dies 314, 332, 352 each may be implemented with a III-V field effect transistor (e.g., a HEMT), such as a gallium nitride (GaN) FET (or another type of III-V transistor, including a GaAs FET, a GaP FET, an InP FET, or an InSb FET). In addition or alternatively, the power transistors within the dies 314, 332, 352 may be implemented with a silicon-based FET (e.g., a laterally diffused metal oxide semiconductor (LDMOS) FET) or a silicon germanium (SiGe) FET, in some embodiments. Further, the semiconductor technology of the driver amplifier die 314, the carrier amplifier die 332, and the peaking amplifier die 352 may be the same, or the driver amplifier die 314 may utilize one semiconductor technology, while the carrier and peaking amplifier dies 332, 352 utilize a different semiconductor technology.
The description and claims may refer to each transistor as including a control terminal and two current-conducting terminals. For example, using terminology associated with FETs, a “control terminal” refers to a gate lead of a transistor, and first and second current-conducting terminals refer to drain and source terminals (or vice versa) of a transistor. Although the below description may use terminology commonly used in conjunction with FET devices, the various embodiments are not limited to implementations the utilize FET devices, and instead are meant to apply also to implementations that utilize bipolar junction transistors (BJT) devices or other suitable types of transistors.
As described above and best shown in
The bottom surfaces of the heat dissipation structures 361, 362 and the bottom surface of base structure 363, when included, are exposed at the bottom surface 385 of the device substrate 383. Alternatively, the bottom surfaces of the heat dissipation structures 361, 362 may be covered with the bottom conductive layer 398 and/or a plating layer. Either way, the heat dissipation structures 361, 362 are configured to provide a thermal pathway between the dies 314, 332, 352 and the bottom surfaces of the heat dissipation structures 361, 362 (and thus the bottom surface 385 of the device substrate 383).
In some embodiments, and particularly when base structure 363 is excluded, the heat dissipation structures 361, 362 may include separate conductive metallic coins that are press-fit and/or attached into through-holes that extend between the surfaces 384, 385 of the device substrate 383. Alternatively, when base structure 363 is included, structures 361-363 may be integrally formed together and/or machined from a single block of thermally conductive material. Either way, as will be described in more detail in conjunction with
Now that the general physical construction of device 300 has been described, the amplifier circuitry embedded within device 300 will now be described in additional detail. In particular, the packaged power amplifier device 300 includes an RF signal input lead 304 (e.g., RF input lead 104,
Lead 304 functions as the RF input lead for the device 300. According to an embodiment, lead 304 is coupled to an RF signal input pad (not numbered) at the mounting surface 384 of the device substrate 383. Through one or more conductive structures of the substrate 383 (e.g., vias, traces, and/or wirebonds), the RF input lead 304 is electrically coupled through a driver input matching circuit 313 (e.g., circuit 113,
The driver amplifier die 314 is configured to amplify the input RF signal received from the input matching circuit 313, in order to produce a pre-amplified RF signal at the output terminal 316 (e.g., drain terminal) of the driver amplifier die 314. Using terminology associated with FETs, the driver amplifier die 314 includes a power transistor with a gate terminal electrically coupled to the input terminal 315, a drain terminal electrically coupled to the output terminal 316, and a source terminal electrically coupled to a conductive layer (not numbered) on a bottom surface of the die 314. Because the conductive layer is connected to the first heat dissipation structure 361, which in turn may be coupled to a system ground, the conductive layer on the bottom surface of the die 314 may provide a ground node for the source terminal.
A driver output matching circuit 317 (e.g., circuit 117,
As discussed above, during operation of device 300, the pre-amplified signal produced by the driver amplifier die 114 is transferred off the device 300 (and onto the amplifier substrate) through the driver output terminal 305. On the amplifier substrate (e.g., substrate 180,
On the amplifier substrate (e.g., substrate 183,
The carrier amplifier path 330 (e.g., carrier amplifier path 130,
However they are implemented, the carrier input terminal 306 and the carrier input matching circuits 327, 331 are configured to transform the impedance between one output (e.g., output 122,
The carrier amplifier die 332 is configured to receive, at input terminal 338, the pre-amplified carrier signal produced at a first output (e.g., output 122,
The peaking amplifier path 350 (e.g., peaking amplifier path 150,
However they are implemented, the peaking input terminal 307 and the peaking input matching circuits 328, 351 are configured to transform the impedance between a second output (e.g., output 123,
The peaking amplifier die 352 is configured to receive, at input terminal 358, the pre-amplified peaking signal produced at a second output (e.g., output 123,
The output terminals 339, 359 of the carrier and peaking amplifier dies 332, 352 are coupled through an output combining network 370 (e.g., network 270,
The first portion of the output combining network 370 includes a plurality of elements that are configured to impart about a 90 degree phase shift to the amplified carrier signal between the output lead 339 of the carrier amplifier die 332 and the power combining node 376. In other words, the total electrical length of the first portion of the output combining network 370 may be about lambda/4 (λ/4) (i.e., about 90 degrees) at the fundamental frequency of operation, f0, of the amplifier. Accordingly, the output combining network 370 is configured to impart about a 90 degree relative phase shift to the amplified carrier signal between the output lead 339 and the power combining node 376 at the fundamental frequency.
In one or more embodiments, the first portion of the output combining network 370 includes a first connection 371 (e.g., a wirebond array), and a first transmission line 372 that has a first end and a second end. In the illustrated embodiment, the first connection 371 is coupled between the output terminal 339 of the carrier amplifier die 332 and the first end of the first transmission line 372.
Conversely, the second portion of the output combining network 370 includes a plurality of elements that are configured to impart about a 180 degree phase shift to the amplified peaking signal between the output lead 359 of the peaking amplifier die 352 and the power combining node 376. In other words, the total electrical length of the second portion of the output combining network 370 may be about lambda/2 (λ/2) (i.e., about 180 degrees) at the fundamental frequency of operation, f0, of the amplifier. Accordingly, the output combining network 370 is configured to impart about a 180 degree relative phase shift to the amplified peaking signal between the output lead 359 and the power combining node 376 at the fundamental frequency.
In one or more embodiments, the second portion of the output combining network 370 includes a second connection 374 (e.g., a wirebond array), and a second transmission line 373 with a first end and a second end. In the illustrated embodiment, the second connection 374 is coupled between the output terminal 359 of the peaking amplifier die 352 and a first end of the second transmission line 373. A second end of the second transmission line 373 is coupled to the second end of the first transmission line 372. The intersection of the ends of the first and second transmission lines 372, 373 corresponds to the power combining node 376. During operation of device 300, the amplified carrier and peaking signals combine in phase at the power combining node 376.
The power combining node 376 is electrically coupled to the device output terminal 308 (e.g., terminal 108,
As discussed previously in conjunction with
As discussed in conjunction with
According to one or more embodiments, the packaged power amplifier device 300 is mounted on the amplifier substrate 680 by first applying conductive attachment material (e.g., material 399,
As indicated previously, the amplifier substrate 680 may include, for example, a PCB or other suitable substrate. An amplifier input terminal 601 (e.g., input terminal 101,
According to an embodiment, the input RF signal received at the amplifier input terminal 601 is conveyed through a first impedance matching circuit 610 (e.g., circuit 110,
The driver amplifier die produces a pre-amplified RF signal, which is conveyed through a driver output impedance matching circuit (e.g., circuit 117, 317,
The driver output lead (e.g., lead 105, 305,
According to one or more embodiments, the overall impedance matching circuit between the output terminal of the driver amplifier die (e.g., terminal 316 of die 314,
The overall impedance matching circuit also includes a series inductance associated with the driver output terminal 305. According to an embodiment, an inductance value for the driver output terminal 305 may be in a range of about 0.25 nanohenries (nH) to about 0.75 nH, although the inductance may be smaller or larger, as well.
Further still, the overall impedance matching circuit also includes an additional impedance matching circuit 618 (e.g., circuit 118,
Referring again to
The outputs 622, 623 of the power splitter 620 are connected through phase shifting circuits 624, 626 (e.g., circuits 124, 126,
Now back within the packaged power amplifier device 300, the carrier input lead is coupled to the carrier amplifier path (e.g., path 130, 330,
Along the carrier amplifier path, the carrier signal is conveyed from the carrier input lead (e.g., lead 106, 306,
According to one or more embodiments, the overall impedance matching circuits between the outputs 622, 623 of the power splitter 620 (e.g., outputs 122, 123, of splitter 120,
The overall impedance matching circuit for the carrier amplifier path also includes a series inductance associated with the carrier input terminal 306. According to an embodiment, an inductance value for the carrier input terminal 306 may be in a range of about 0.25 nH to about 0.75 nH, although the inductance may be smaller or larger, as well.
Further still, the overall impedance matching circuit for the carrier amplifier path includes first and second carrier input impedance matching circuits 327, 331 (
The overall impedance matching circuit for the peaking amplifier path may be substantially similar to the overall impedance matching circuit for the carrier amplifier path. Briefly, and as described above, the overall impedance matching circuit for the peaking amplifier path includes a second phase shifting circuit 628 (e.g., circuit 128,
The overall impedance matching circuit for the peaking amplifier path also includes a series inductance associated with the peaking input terminal 307. According to an embodiment, an inductance value for the peaking input terminal 307 may be in a range of about 0.25 nH to about 0.75 nH, although the inductance may be smaller or larger, as well.
Further still, the overall impedance matching circuit for the peaking amplifier path includes first and second peaking input impedance matching circuits 328, 351 (
Within device 300, the carrier and peaking signals are amplified (by carrier and peaking dies 132, 152, 332, 352,
In addition to the various features discussed above, the power amplifier system 600 also may include a plurality of additional terminals 611, 612, 613, 614, 615, 616 on the amplifier substrate 680, which are configured to receive driver amplifier gate and drain bias voltages, carrier amplifier gate and drain bias voltages, and peaking amplifier gate and drain bias voltages, respectively. These terminals 611-616 are coupled through additional traces and bias circuitry on the amplifier substrate 680 to additional substrate bond pads, which in turn are connected to bias terminals (e.g., terminals 109, 304, 305, 309-312,
Referring now to
In order to connect device 300 to the amplifier substrate 680, each of the terminals 302 of device 300 are aligned and brought into contact with corresponding pads 902 on the mounting surface 909 of the amplifier substrate 680. The conductive attachment material 392 then is reflowed or otherwise cured to physically connect the device terminals 302 to their corresponding pads 902 on the mounting surface 909 of the amplifier substrate 680. In other embodiments, conductive attachment material also or alternatively may be disposed on the conductive pads 902 of the amplifier substrate 680, and an appropriate reflow or curing process may be performed to connect the device 300 to the amplifier substrate 680.
In this orientation, the bottom surface of the heat dissipation structure 360 of the device 300 is facing upward and outward. This enables the heat generated by the dies 314, 332, 352 within the device 300, which is absorbed by the heat dissipation structure 360 (including structures 361, 362), to be removed through the top of the system 600. Again, this is referred to as “top side cooling” the device 300. The top side cooling topology described and illustrated herein may have significant benefits associated with heat dissipation, because this topology allows heat produced by both the driver stage amplifier die (e.g., die 314) and the final stage carrier and peaking amplifier dies (e.g., dies 332, 352) to be removed through the same heat dissipation structure, which may not be possible with a discrete solution in which the driver stage amplifier die is not integrated in the manner described herein and depicted in the figures.
More specifically, a heat sink 916 may be physically and thermally coupled to the upward facing surface of the packaged power amplifier device 300, and specifically to the upward facing surface of the heat dissipation structure 360. The heat sink 916 is formed from a thermally-conductive material, which also may be electrically-conductive. For example, the heat sink 916 may be formed from copper or another bulk conductive material. To couple the heat sink 916 to the packaged power amplifier device 300, a thermally conductive material 998 (e.g., thermal grease) may be dispensed on the exposed surface of the heat dissipation structure 360 (or on the surfaces of heat dissipation structures 361, 362) and/or on the heat sink 916, and the heat sink 916 may be brought into contact with the surface of the heat dissipation structure 360. The heat sink 916 may then be clamped, screwed, or otherwise secured in place.
During operation of the power amplifier system 600, input RF signals are provided through the RF input terminal 601 (
During operation, significant thermal energy (heat) may be produced by the power transistor(s) within the power transistor dies 314, 332, 352. As indicated by arrows 999, the thermal energy produced by the power transistor dies is conveyed through the heat dissipation structure 360 (including structures 361, 362,
The amplifier system 1000 generally includes the amplifier substrate 1080, the packaged power amplifier device 300′, and a heat sink 1016. According to an embodiment, the amplifier substrate 1080 includes a multi-layer PCB or other suitable substrate. The amplifier substrate 1080 has a mounting surface 1009, and an opposed bottom surface. The amplifier substrate 1080 also includes a plurality of dielectric layers (e.g., formed from FR-4, ceramic, or other PCB dielectric materials), in an alternating arrangement with a plurality of conductive layers.
The packaged power amplifier device 300′ is coupled to the mounting surface 1009 of the amplifier substrate 1080 in the same orientation as the orientation depicted in
According to an embodiment, a heat sink 1016 is embedded in the amplifier substrate 1080, and when the device 300′ is coupled to the amplifier substrate 1080, the heat sink 1016 is physically and thermally coupled to the bottom surface 385 of the packaged power amplifier device 300′, and more specifically to the exposed surface of the embedded heat dissipation structure 360 (including structures 361, 362) of device 300′. The heat sink 1016 is formed from a thermally-conductive material, which also may be electrically-conductive. For example, the heat sink 1016 may be formed from copper or another bulk conductive material. To couple the heat sink 1016 to the packaged power amplifier device 300′, a thermally conductive material 1098 (e.g., thermal grease) may be dispensed on the surface of the heat dissipation structure 360 (or the surfaces of structures 361, 362) and/or on the heat sink 1016, and the heat sink 1016 may be brought into contact with the device 300′.
During operation of the power amplifier system 1000, input RF signals are provided through the RF input terminal (not shown) of the amplifier substrate 1080 and subsequently through the RF input terminal (one of terminals 302′, not shown) of the packaged power amplifier device 300′. The input RF signals are then amplified, as discussed previously. The amplified output RF signals are produced at an RF output terminal (another one of terminals 302′, not shown) of the packaged power amplifier device 300′, which is electrically coupled to the RF output terminal (not shown) on the amplifier substrate 1080.
Again, during operation, significant thermal energy (heat) may be produced by the power transistor(s) within the power transistor dies 314, 332, 352. As indicated by arrows 1099, the thermal energy produced by the power transistor dies is conveyed through the heat dissipation structure 360 (including structures 361, 362,
An embodiment of a packaged semiconductor device includes a device substrate, an interface for signal communication with an external power splitter, and a first and second stages of a multiple-stage amplifier. The device substrate has a mounting surface and a bottom surface. The interface for signal communication with an external power splitter includes first, second, and third leads coupled to the device substrate. The first stage of the multiple-stage amplifier includes a first amplifier die with a first input, a first output, and a first power transistor that functions as a driver amplifier. The first output is coupled to the first lead. The second stage of the multiple-stage amplifier includes first and second amplifier paths. The first amplifier path has a second amplifier die with a second input, a second output, and a second transistor that functions as a first final stage amplifier. The second input is coupled to the second lead. The second amplifier path has a third amplifier die with a third input, a third output, and a third transistor that functions as a second final stage amplifier. The third input is coupled to the third lead.
An embodiment of a multiple-stage multiple-path power amplifier includes an amplifier substrate, a packaged semiconductor device, and a power splitter. The amplifier substrate has a top substrate surface and first, second, and third device interconnects at a top substrate surface. The packaged semiconductor device is coupled to the top substrate surface, and the packaged semiconductor device includes a device substrate, an interface for signal communication with a power splitter, and first and second stages of a multiple-stage amplifier. The device substrate has a mounting surface and a bottom surface. The interface for signal communication with the power splitter includes first, second, and third leads coupled to the device substrate and coupled to the first, second, and third device interconnects, respectively. The first stage of a multiple-stage amplifier includes a first amplifier die with a first input, a first output, and a first power transistor that functions as a driver amplifier. The first output is coupled to the first lead. The second stage of the multiple-stage amplifier that includes first and second amplifier paths. The first amplifier path has a second amplifier die that has a second input, a second output, and a second transistor that functions as a first final stage amplifier. The second input is coupled to the second lead. The second amplifier path has a third amplifier die with a third input, a third output, and a third transistor that functions as a second final stage amplifier. The third input is coupled to the third lead. The power splitter is coupled to the top substrate surface. The power splitter has a splitter input coupled to the first device interconnect, a first splitter output coupled to the second device interconnect, and a second splitter output coupled to the third device interconnect. The power splitter is configured to receive a first signal characterized by a first signal power at the splitter input, to provide a first portion of the first signal power at the first splitter output, and to provide a second portion of the first signal power at the second splitter output.
The preceding detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or detailed description.
The connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in an embodiment of the subject matter. In addition, certain terminology may also be used herein for the purpose of reference only, and thus are not intended to be limiting, and the terms “first”, “second” and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.
As used herein, a “node” means any internal or external reference point, connection point, junction, signal line, conductive element, or the like, at which a given signal, logic level, voltage, data pattern, current, or quantity is present. Furthermore, two or more nodes may be realized by one physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished even though received or output at a common node).
The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with, electrically or otherwise) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in an embodiment of the depicted subject matter.
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope defined by the claims, which includes known equivalents and foreseeable equivalents at the time of filing this patent application.
