Patent Application
20190377025
In a semiconductor material, deviations from the crystalline lattice structure may correspond to physical defects. Certain types of these physical defects have an impact on the electrical characteristics of the semiconductor material, such as in the form of a charge carrier trap that affects the mobility of charge carriers such as free electrons or electron holes. Some traps are referred to as deep traps because the energy to free a charge carrier from the deep trap exceeds the characteristic thermal energy. The impeded mobility of charge carriers impacts the operation of transistors, light emitting diodes, photovoltaic cells, and so forth. As one example, a failure mode of metal oxide semiconductor field effect transistors (MOSFETs) relates to Bias Temperature Instability (BTI), which occurs when traps cause the operating threshold voltage of the transistor to shift when traps are filled with charge carriers. As another example, Copper-Indium-Gallium-Selenide (CIGS) solar cells can have a class of defects with metastable behavior, such as in response to light or hysteresis effects, thereby complicating CIGS device characterization.
Deep-level transient spectroscopy (DLTS) is a capacitance-based device characterization method used widely in semiconductor and photovoltaic (PV) applications to determine the number and type of charge-trapping defects in the active area of a solar or semiconductor device. High-speed CV (HSCV) is another method for profiling charge distributions in semiconductor devices, sometimes with greater precision than a DLTS system. In HSCV, a voltage sweep occurs in a short time interval such that charge-trapping defects can neither trap free carriers nor release their trapped carriers, thereby avoiding associated capacitance transients.
DLTS and HSCV are versatile semiconductor device characterization methods. Conventionally, however, they have been performed sequentially, requiring separate analyses that potentially represent different device states. For instance, in CIGS solar cells, due to their particular set of defect characteristics, it is common that a DLTS measurement changes the state of the device such that a HSCV measurement yields different results before and after the DLTS measurement. How the CIGS device changes during DLTS is not directly measurable because the HSCV and DLTS methods are conventionally performed sequentially.
One aspect of the subject matter described herein relates to an apparatus including: a first input configured to interface to a semiconductor device; a first output configured to interface to the semiconductor device; first circuitry configured to generate a set of waveform cycles at the first output, each cycle having: a first temporal portion having a first signal configured to fill a set of charge-trapping defects in the semiconductor device with free carriers; a second temporal portion having a second signal configured to cause a subset of the free carriers to retract from the set of charge-trapping defects based on a time constant; a first subset of cycles corresponding to less than the entire set of waveform cycles further having: a third signal and a fourth signal during the second temporal portion, the third signal and the fourth signal being configured to cause a corresponding number of free carriers filled and/or retracted from the set of charge-trapping defects to be within a constraint, the third signal occurring earlier than the second signal, the fourth signal occurring later than the second signal. The apparatus also includes second circuitry configured to measure a first set of capacitance characteristics at the first input based in part on the third signal and a second set of capacitance characteristics at the first input based in part on the fourth signal for determining a change in charge depth profiles in the semiconductor device at different times during the second temporal portion.
In some implementations, the semiconductor device is a photovoltaic cell. In some implementations, the photovoltaic cell is a copper-indium-gallium-selenide (cigs) photovoltaic cell. In some implementations, a time duration for the third signal is selected such that a difference between a first sample value from a capacitance transient during the third signal and a second sample value from a second capacitance transient during the second temporal portion of a cycle not included in the first subset of cycles is below a threshold value. In some implementations, the threshold value is about 3 pf. In some implementations, the third signal has: a time duration of about 1 ms; about 25 voltage steps; and a voltage range of about −1 v to about −0.2 v. In some implementations, the third signal and the fourth signal have the same time duration, number of voltage steps, and voltage range. In some implementations, a single cycle in the first subset of cycles follows a single cycle not in the first subset of cycles. In some implementations, each cycle in the first subset of cycles includes three voltage ramps for measuring capacitance characteristics at the first input for determining changes in charge depth profiles in the semiconductor device during the second temporal portion, the three voltage ramps including the third signal and the fourth signal. In some implementations, a first subset of the set of charge-trapping defects corresponds to metastable defects that are responsive to at least one of light or hysteresis effects. Implementations of the described techniques may include hardware, a method or process, or computer software on a computer-accessible medium.
Another aspect of the subject matter described herein relates to a method including: generating a set of waveform cycles at a first output configured to interface to a semiconductor device, each cycle having: a first temporal portion having a first signal configured to fill a set of charge-trapping defects in the semiconductor device with free carriers; a second temporal portion having a second signal configured to cause a subset of the free carriers to retract from the set of charge-trapping defects based on a time constant; a first subset of cycles corresponding to less than the entire set of waveform cycles further having: a third signal and a fourth signal during the second temporal portion, the third signal and the fourth signal being configured to cause a corresponding number of free carriers filled and/or retracted from the set of charge-trapping defects to be within a constraint, the third signal occurring earlier than the second signal, the fourth signal occurring later than the second signal. The method also includes measuring at a first input configured to interface to the semiconductor device a first set of capacitance characteristics based in part on the third signal and a second set of capacitance characteristics at the first input based in part on the fourth signal for determining a change in charge depth profiles in the semiconductor device at different times during the second temporal portion.
In certain implementations, the semiconductor device is a photovoltaic cell. In certain implementations, the photovoltaic cell is a copper-indium-gallium-selenide (cigs) photovoltaic cell. In certain implementations, a time duration for the third signal is selected such that a difference between a first sample value from a capacitance transient during the third signal and a second sample value from a second capacitance transient during the second temporal portion of a cycle not included in the first subset of cycles is below a threshold value. In certain implementations, the threshold value is about 3 pf. In certain implementations, the third signal has: a time duration of about 1 ms; about 25 voltage steps; and a voltage range of about −1 v to about −0.2 v. In certain implementations, the third signal and the fourth signal have the same time duration, number of voltage steps, and voltage range. In certain implementations, a single cycle in the first subset of cycles follows a single cycle not in the first subset of cycles. In certain implementations, each cycle in the first subset of cycles includes three voltage ramps for measuring capacitance characteristics at the first input for determining changes in charge depth profiles in the semiconductor device during the second temporal portion, the three voltage ramps including the third signal and the fourth signal. In certain implementations, a first subset of the set of charge-trapping defects corresponds to metastable defects that are responsive to at least one of light or hysteresis effects.
Another aspect of the subject matter described herein relates to a computer program product comprising computer-readable program code to be executed by one or more processors when retrieved from a non-transitory computer-readable medium, the program code including instructions configured to cause: generating a set of waveform cycles at a first output configured to interface to a semiconductor device, each cycle having: a first temporal portion having a first signal configured to fill a set of charge-trapping defects in the semiconductor device with free carriers; a second temporal portion having a second signal configured to cause a subset of the free carriers to retract from the set of charge-trapping defects based on a time constant; a first subset of cycles corresponding to less than the entire set of waveform cycles further having: a third signal and a fourth signal during the second temporal portion, the third signal and the fourth signal being configured to cause a corresponding number of free carriers filled and/or retracted from the set of charge-trapping defects to be within a constraint, the third signal occurring earlier than the second signal, the fourth signal occurring later than the second signal. The method also includes measuring at a first input configured to interface to the semiconductor device a first set of capacitance characteristics based in part on the third signal and a second set of capacitance characteristics at the first input based in part on the fourth signal for determining a change in charge depth profiles in the semiconductor device at different times during the second temporal portion.
These and other aspects are described further below with reference to the drawings.
This disclosure describes systems and techniques for a multiplexed DLTS and HSCV measurement system. For example, when a CIGS solar cell is being characterized using the DLTS method, how the CIGS device changes during DLTS is measured using the HSCV method.
Deep-level transient spectroscopy (DLTS) is a capacitance-based device characterization method that can be used in semiconductor and PV applications to determine the number and type of charge-trapping defects in the active area of a solar or semiconductor device. Methods exist for the interpretation of DLTS spectra to obtain the activation energy of recombination-active defects, their capture cross-section, and their concentration. DLTS can be operated in digital mode, whereby the output of a fast capacitance meter is sampled digitally at a high rate during a capacitance transient that is induced by changing applied voltage to the device under test (DUT), such as a CIGS solar cell. The capacitance transients result from the evolving trapped charge profile in the device.
In DLTS, the temperature of the DUT can be varied, causing a change in the capacitance transient time constant. The relationship between the temperature and the time constant can be analyzed to determine the kinetics of emission of trapped charge in the device. By varying the voltage applied to the DUT, it is possible to control the depth of the injected carriers into the active area of the device. By repeating DLTS measurements at different voltage settings, it is possible to infer the location of the charge-trapping defects by comparing the magnitude of the DLTS response among different discrete voltage values. In this way, a concentration (e.g., charge depth) profile can be produced. In some scenarios, the DLTS method involves repeating measurements to perform a temperature sweep.
The capacitance-voltage (CV) technique is an example of another method for profiling charge distributions in semiconductor devices. In the CV technique, capacitance for a DUT is recorded over a range of applied voltage in a static device in times ranging from several seconds to a few minutes. From this capacitance-voltage relationship, it is possible to calculate the shallow dopant profile in the DUT. In some scenarios, the presence of charge-trapping defects that can induce capacitance transients and accumulate trapped charge in the active region complicates the interpretation of CV results.
The method of high-speed CV (HSCV) eliminates some of the problems with conventional CV in some devices. In HSCV, a voltage sweep occurs in as little as, for example, one millisecond. In some scenarios, for such a time interval, the charge-trapping defects do not trap free carriers nor release their trapped carriers, thereby there is no corresponding capacitance transient (e.g., the charge distribution is essentially frozen in place). The measured HSCV profile represents the total charge density (e.g., dopants plus ionized defects) based on a straightforward interpretation, and is useful to diagnose changing charge profiles in a device, and in certain scenarios, can help reveal the origin of the changes.
This disclosure describes systems and techniques for a multiplexed DLTS and HSCV measurement system. In certain implementations, because HSCV can diagnose changing charge profiles in a device, HSCV measurements performed during a DLTS measurement can reveal with precision the changing charge profile that yields the capacitance transient that DLTS processes and analyzes. The disclosed techniques integrate both DLTS and HSCV measurements simultaneously in a measurement on, for example, a digital data acquisition platform.
In a class of implementations, DLTS measurements are configured to employ a repeating pulse cycle, or waveform cycle, in which the capacitance transient can be continuously monitored and analyzed, each HSCV voltage sweep is configured to last, for example, about one millisecond, HSCV voltage sweeps are inserted periodically into the repeating DLTS pulse sequence, and the DLTS and HSCV signals can be processed independently.
It should be appreciated that the disclosed techniques can provide both a DLTS measurement as well as a simultaneous series of temperature-dependent charge profiles in approximately the same amount of time as the DLTS measurement itself. It should be noted that multiplexing DLTS and HSCV measurements can enable observation of the changing charge and/or effective doping profile that occurs during a DLTS measurement (e.g., use of HSCV to study charge evolution during capacitance transients in DLTS measurements). Examples of the voltage pulse sequence and the analysis of the recorded capacitance values are illustrated through the figures discussed below.
The particular signs (e.g., positive, negative) for voltage and capacitance values in the following figures are for example purposes, and the particular sign for a voltage or capacitance value may differ based on the configuration of the DUT and/or measurement set up. It should further be appreciated that the specific values and units for voltage and capacitance in the following figures are for example purposes, and values may be expressed as a relative change (e.g., ratios, percentages, delta values, and so forth), and/or the unit may differ based on the configuration of the DUT and/or measurement set up. It should also be appreciated that in some implementations, a current source can be used instead of a voltage source.
In a subset of cycles, the flow also includes generating a third signal (164) and a fourth signal (166) during the second temporal portion (e.g., the relaxation phase), the third signal and the fourth signal (e.g., different HSCV voltage ramps) being configured to cause a corresponding number of free carriers filled and/or retracted from the set of charge-trapping defects to be within a constraint (e.g., the perturbation in a relaxation phase capacitance transient being constrained to, for example, less than 3 pF). As further described in detail in relation to the discussions of
The flow also includes measuring at a first input configured to interface to the semiconductor device a first set of capacitance characteristics based in part on the third signal (168) and a second set of capacitance characteristics at the first input based in part on the fourth signal (170). These different sets of capacitance characteristics, in relation to the respective third signal and fourth signal, are used at 172 for determining a change in charge depth profiles in the semiconductor device at different times during the second temporal portion. The examples discussed below in relation to
In
In certain implementations, repeated pulsing and data acquisition are used to increase the signal-to-noise ratio as the temperature (and therefore, the capacitance transient time constant) continuously changes over time. For example, depicted in
An example illustrating the method 300 to multiplex DLTS and HSCV measurements is depicted in
For the DLTS pulse cycles, the capacitance transient is acquired and analyzed according to the DLTS method as discussed for
During these HSCV pulse cycles the DLTS analysis can be idle and not processing data, and instead each individual HSCV voltage ramp (e.g., voltage ramp 312a) can be used to acquire, store, and process C-V data for that particular pulse cycle. In certain implementations, changes across different sets of C-V data corresponding to different HSCV voltage ramps provide snapshots of the evolving charge profile during a DLTS capacitance transient. For example, the evolving charge profile during the capacitance transient 310 can be observed using C-V data for voltage ramp 312a and C-V data for voltage ramp 312b. Furthermore, differences in the evolving charge profiles for different capacitance transients, such as between capacitance transient 310 and capacitance transient 311, can be observed. It should be appreciated that the evolving charge profile is determined for the particular conditions for a particular DLTS pulse cycle (e.g., temperature, etc.) and at the same time the overall DLTS measurement process is being performed.
The evolving charge profile can also be represented as in charge (in units of N, the number of units of electron charge e, per centimeter cubed) versus spatial depth (in units of microns) plots 405. The temporal sequence of traces 406, 407, and 408, corresponding to 5, 450, and 875 ms, respectively, illustrates that over time, during the capacitance transient, there is a transition to a greater charge density (e.g., arrow 403 in the direction of increasing charge density) in a shallower region of the DUT (e.g., arrow 404 in the direction of decreasing depth). Observing the evolving charge profile can provide information on the characteristics of the defects in the DUT. For example, some types of defects may trap and/or release charge carriers over a rapid timescale that cannot be determined using the disclosed techniques, therefore observation of an evolving charge profile can indicate the presence of particular types of defects.
It should be appreciated that the duration of interval 334 for the HSCV voltage ramp(s) are of a duration relative to the duration of the DLTS pulse phase (e.g., pulse 301) such that the HSCV measurements have a limited effect on the overall capacitance transient relative to pulse cycles without HSCV measurements. For example, the duration of the HSCV voltage ramp is selected to be shorter than a timing threshold based on the shorter of the times required to fill the charge-trapping defects during the pulse phase or the relaxation time constant during the relaxation phase. If the duration of the HSCV voltage ramp exceeds the timing threshold, the HSCV ramp may induce additional defect charging or relaxation.
Plot 600 indicates that as the HSCV voltage ramp timing duration increases, the magnitude of the capacitance transient perturbations increase, and vice versa. For example, when reducing the HSCV voltage ramp timing duration to 0.1 ms, as indicated by marker 620, the magnitude of the capacitance transient perturbations have a limited effect of about 2.5 pF of capacitance delta, capacitance perturbation range 610. In other words, for a DLTS pulse width of 100 ms, each voltage ramp duration of 1 ms during the relaxation phase of about 900 ms can create capacitance transient perturbations (e.g., capacitance deltas 521, 525, 530) of about 2.5 pF. It should be appreciated that plot 600 indicates that even small HSCV voltage ramp timing durations (e.g., 0.1 ms) induce a small step in capacitance (e.g., charge capture occurs). However, the overall capacitance transient characteristics are maintained, and the HSCV measurements can provide information on the change in charge profile from the beginning to the end of the capacitance transient.
Various implementations described herein may be implemented using any in a variety of standard or proprietary discrete electronics or integrated semiconductor processes. In addition, it should be noted that implementations are contemplated that may employ a much wider range of semiconductor materials and manufacturing processes including, for example, CMOS, CIGS, GaAs, SiGe, etc.
As indicated above, in some implementations, the apparatus and methods may be employed for characterization of photovoltaic materials and cells. For example, in addition to CIGS cells, aspects of the disclosure may be applied to cadmium-telluride (Cd—Te) cells, amorphous silicon (a-Si) cells, micro-crystalline silicon (Si) cells, crystalline silicon (c-Si) cells, and gallium arsenide (GaAs) multi-junction cells.
The multiplexed DLTS and HSCV measurement system as described herein may be represented (without limitation) in software (object code or machine code in non-transitory computer-readable media), in varying stages of compilation, as one or more netlists (e.g., a SPICE netlist), in a simulation language, in a hardware description language (e.g., Verilog, VHDL), by a set of semiconductor processing masks, and as partially or completely realized semiconductor devices (e.g., an ASIC). Some implementations may be a standalone integrated circuit, while others may be embedded as part of larger system, module, data acquisition platform, or test and measurement set up (e.g., SULA, SEMETROL).
It will be understood by those skilled in the art that changes in the form and details of the implementations described above may be made without departing from the scope of this disclosure. In addition, although various advantages have been described with reference to some implementations, the scope of this disclosure should not be limited by reference to such advantages. Rather, the scope of this disclosure should be determined with reference to the appended claims.
