Patent Application
20240363683
The present invention relates generally to semiconductor devices and fabrication, and, more particularly, to enhanced edge termination structures for use in a semiconductor device, and methods of fabricating such structures.
Vertically conducting semiconductor devices in an integrated circuit (IC) include an active region that is surrounded by an edge termination region. In such vertical devices, the edge of the die is invariably at the same or similar voltage potential as that of a bottom of the device due primarily to saw damage when the device is singulated, or lack of a blocking junction at the edge of the device. Therefore, an edge termination region is an important part of the device design to ensure lateral blocking of potentially damaging voltages between the active region and the edge of the die.
While the active region only needs to withstand the blocking voltage in the vertical direction, the edge termination region must be able to withstand the blocking voltage in both the lateral and vertical directions. The requirement of an edge termination region to maintain a voltage blocking capability in both the vertical and lateral directions makes the design of the edge termination region of the device a critical factor in determining the performance and cost effectiveness of the device.
For semiconductor devices employing charge balance in the active region of the device, the design of the edge termination region is further complicated by a requirement to “charge balance” a last active cell of the device.
The present invention, as manifested in one or more embodiments, beneficially provides an enhanced edge termination structure for use in a charge balanced semiconductor device. In one or more embodiments, the edge termination structure is configured to isolate an active region in the semiconductor device by surrounding the active region with insulating material. Furthermore, while planar edge termination structures are more traditional, aspects of the present inventive concept beneficially provide both vertical and lateral voltage blocking.
In accordance with an embodiment of the invention, a method of forming an edge termination structure in a semiconductor device is provided. The method includes: forming an epitaxial layer on a semiconductor substrate, the epitaxial layer extending laterally across active and edge termination regions in the device; forming active trenches in the active region and at least one outer trench in the edge termination region, each of the outer and active trenches extending vertically through at least a portion of the epitaxial layer; at least partially filling each of the outer and active trenches with a first insulating material; forming a moat by etching an area of the epitaxial layer in the edge termination region proximate to a last one of the plurality of active trenches in the active region; and at least partially filling the moat with a second insulating material to form a moat structure as an edge termination structure in the semiconductor device.
In accordance with another embodiment, a semiconductor device is provided having an active region and an edge termination region, the edge termination region being laterally adjacent to the active region. The semiconductor device includes an epitaxial layer formed on a semiconductor substrate, the epitaxial layer extending laterally across the active and edge termination regions. The semiconductor device further includes a plurality of active trench structures and at least one active device formed in the active region, each of the active trench structures extending vertically through at least a portion of the epitaxial layer and being at least partially filled with a first insulating material. At least one outer trench structure is formed in the edge termination region of the semiconductor device, the outer trench structure extending vertically through at least a portion of the epitaxial layer and being at least partially filled with the first insulating material. The outer trench structure is proximate to a last one of the plurality of active trench structures in the active region. The semiconductor device further comprises a moat structure extending vertically through at least a portion of the epitaxial layer in the edge termination region, the moat structure having a sidewall defined by the at least one outer trench structure, the moat structure being at least partially filled with a second insulating material. The moat structure forms an edge termination structure in the semiconductor device configured to laterally isolate the active region from a reverse voltage in the semiconductor device.
As the term may be used herein, “facilitating” an action includes performing the action, making the action easier, helping to carry the action out, or causing the action to be performed. Thus, by way of example only and without limitation, in the context of a processor-implemented method, instructions executing on one processor might facilitate an action carried out by instructions executing on a remote processor, by sending appropriate data or commands to cause or aid the action to be performed. For the avoidance of doubt, where an actor facilitates an action by other than performing the action, the action is nevertheless performed by some entity or combination of entities.
Techniques of the present invention can provide substantial beneficial technical effects. By way of example only and without limitation, techniques according to embodiments of the invention may provide one or more of the following advantages, among other benefits:
These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The following drawings are presented by way of example only and without limitation, wherein like reference numerals (when used) indicate corresponding elements throughout the several views, and wherein:
It is to be appreciated that elements in the figures are illustrated for simplicity and clarity. Common but well-understood elements that may be useful or necessary in a commercially feasible embodiment are not necessarily shown in order to facilitate a less hindered view of the illustrated embodiments.
Principles of the present invention, as manifested in one or more embodiments thereof, will be described herein in the context of illustrative edge termination structures configured to withstand a blocking voltage in both lateral and vertical directions, and methods for fabricating such structures. The novel edge termination structures according to embodiments of the invention are suitable for use in a charge balanced semiconductor device, and may have beneficial application, for example, in a power device or power system environment for providing direct current (DC)-DC or alternating current (AC)-DC conversion. It is to be appreciated, however, that the present inventive concepts are not limited to the specific structures and/or methods illustratively shown and described herein. Rather, it will become apparent to those skilled in the art given the teachings herein that numerous modifications can be made to the embodiments shown that are within the scope of the claimed invention. That is, no limitations with respect to the embodiments shown and described herein are intended or should be inferred.
In vertically conducting devices, an edge of the IC die 100 is invariably at the same or similar voltage potential as that of a bottom surface of the device, due primarily to saw damage when the device is singulated (i.e., separated) or lack of a blocking junction at the edge of the device. Therefore, there is a need to not only block voltages between the top and bottom surfaces of the vertical device, but also to block voltages laterally between the active region 102 of the device and edge of the IC die 100; the edge termination region 104 is the region in the device that provides this lateral voltage blocking capability.
The active region 102 may include a plurality of active trench structures 108. Each of the active trench structures 108 may extend at least partially through the epitaxial layer 106 in a substantially vertical direction (z direction). In one or more embodiments, the active trench structures 108 extend at least twenty-five percent (25%) through the epitaxial layer 106; in some embodiments, the active trench structures 108 may extend entirely through the epitaxial layer 106 and into an underlying substrate (not explicitly shown, but implied) on which the epitaxial layer may be formed. A first metal layer 110 may be formed over an upper surface of the active trench structures 108. In one or more embodiments, the active trench structures 108 may be used for charge balancing at least a portion of the active region 102.
The edge termination region 104 may include at least one outer trench structure 112. The outer trench structure 112 may be formed at least partially through the epitaxial layer 106 in a substantially vertical direction (z direction) and may extend along a y direction, orthogonal to the z direction. Although not required, the same trench processing, which may include etching, trench filling, etc., is preferably used to form both the active trench structures 108 and the outer trench structure 112; that is, the same mask and trench etch process can be used to form the active trench structures 108 and the outer trench structure 112, thus reducing costs.
Optionally, one or more boundary trench structures 114 may be formed in the edge termination region 104 at least partially through the epitaxial layer 106 in a substantially vertical direction (z direction). The boundary trench structures 114 may be spaced laterally (e.g., in an x direction) from the outer trench structure 112 by a “moat” structure 118 formed therebetween in the epitaxial layer 106. The term “moat” as used herein is intended to refer broadly to a region adjacent to an active region (e.g., 102) where part of the epitaxial silicon is removed and at least partially filled with an insulating material. The term “filled” (or “filling,” “fill,” or like terms), as may be used herein, is intended to refer broadly to either completely filling a defined space (e.g., the moat structure 118) or partially filling the defined space; that is, the defined space need not be entirely filled but may, for example, be partially filled or have voids or other spaces throughout. The moat structure 118 may be formed as a RESURF (reduced surface field) structure, in one or more embodiments.
Generally, the moat will surround the active region, but configurations are contemplated where the moat may be present on less than all sides of the active region (e.g., a couple of sides only). The term “surround” (or “surrounds,” or like terms), as may be used herein, is intended to broadly refer to an element, structure or layer that extends around, envelops, encircles, or encloses another element, structure or layer on all sides, although breaks or gaps may also be present. Thus, for example, a material layer having voids or gaps therein may still “surround” another layer which it encircles. Although not critical, in one or more embodiments, a width (in the x direction) of the outer trench structure 112 and the boundary trench structures 114 may be larger relative to a width (in the x direction) of the active trench structures 108. For example, in some embodiments, the width of the outer trench structure 112 is about twice (2×) the width of the active trench structures 108. Preferably, the width of the outer trench structure 112 is about 2 microns (μm) and the width of each of at least a subset of the active trench structures 108 is about 1 μm, although embodiments are not limited thereto. This allows the outer trench structure 112 to be etched deeper, which thereby beneficially provides more process margin in forming the edge termination structure. A spacing between adjacent active trench structures 108 (i.e., pitch) may be about 4 μm, although embodiments of the invention are not limited thereto.
The moat structure 118 may be defined by a trench 120, which may be formed by removing a portion of the epitaxial layer 106 in the edge termination region 104, between the outer trench structure 112 and one of the boundary trench structures 114. A vertical depth of the trench 120 in the z direction (relative to an upper surface of the epitaxial layer 106) may generally be similar to a vertical depth of the active trenches, and is preferably less than a depth of the outer trench structure 112 (e.g., about 20 μm). By way of example only, in the exemplary IC die 100, the trench 120 and trench structures 108 may be formed having a depth of about 20 μm and the trench structures 112 and 114 may be formed having a depth of about 22 μm, although embodiments are not limited thereto. An insulating layer 122 may be formed on at least sidewalls and a bottom of the trench 120. The insulating layer 122 may conformally cover inner surfaces of the trench 120. The term “conformally” (or “conformal,” or like terms), as may be used herein in the context of a material layer or coating, is intended to refer broadly to a material layer or coating having a substantially uniform cross-sectional thickness relative to the contour of a surface to which the material layer is applied. The term “cover” (or “covering,” or like terms), as may be used herein, is intended to broadly refer to an element, structure or layer that is on or over another element, structure or layer, either directly or with one or more other intervening elements, structures or layers therebetween.
The insulating layer 122 may extend along sidewalls of the trench 120 and at least partially into the active region 102, such as over at least a subset of the active trench structures 108. Additionally or alternatively, the insulating layer 122 may extend at least partially into the edge termination region 104, such as over at least a subset of the boundary trench structures 114. In one or more embodiments, the insulating layer 122 may comprise, for example, silicon oxynitride (SiOxNy), silicon nitride (SiN), etc., although embodiments are not limited thereto.
The trench 120 may be at least partially filled with an insulating material 124, such as, for example, polyimide or another polymer or organic material, to ultimately form the moat structure 118. A standard deposition process may be used to fill the trench 120. The insulating material 124 may at least partially extend onto an upper surface of the IC die 100, over an upper end of one or more of the active trench structures 108 in the active region 102 and/or one or more of the boundary trench structures 114 in the edge termination region 104.
The moat structure 118, including the insulating layer 122 and insulating material 124, in conjunction with the outer and boundary trench structures 112, 114, beneficially forms an edge capacitor that may be used for edge termination; the outer and boundary trench structures 112, 114 proximate opposing sidewalls of the moat structure 118, enclose the edge capacitor in the edge termination region 104. Edge terminations are generally either capacitive (i.e., voltage blocked across an insulator) or may use a blocking junction in the semiconductor (e.g., a p-n diode). In some embodiments, a combination of these two options may be employed, where some of the voltage is dropped laterally (i.e., horizontally, parallel to the upper surface of the substrate) via a depletion region/blocking junction followed by a moat structure to block the remaining voltage.
Edge termination in the IC die 100 may be configured such that the induced charge due to the edge capacitor is minimal. Charge balance in the IC die 100 may be achieved by configuring a width of a last active mesa 126 (i.e., a region of the epitaxial layer 106 between a last one of the plurality of active trench structures 108 in the active region 102 and a first (or only) outer trench structure 112 in the edge termination region 104) to account for additional charge due to the edge capacitor and charges in the insulating material 124. The plates of the edge capacitor may comprise a sidewall of the outer trench structure 112 adjacent to the moat structure 118 and a sidewall of the boundary trench structure 114 adjacent to the moat structure 118, with the insulating material 124 serving as the dielectric layer between the two capacitor plates.
In one or more embodiments, the IC die 100 may include a second metal layer forming an inner field plate 128 on at least a portion of an upper surface of the first metal layer 110 and over at least a portion of an upper surface of the insulating layer 124 of the moat (e.g., RESURF) structure 118. The inner field plate 128 may comprise a conductive material, such as, for example, a metal. The first metal layer 110 and the inner field plate 128 may, in some embodiments, be formed of the same material, although in other embodiments, the first metal layer 110 and the inner field plate 128 may be formed of different materials. It is to be appreciated that although the exemplary IC die 100 is shown as including two levels of metal, with the inner field plate 128 being formed of the second metal layer, in one or more alternative embodiments, the inner field plate 128 may be formed as an extension of the first metal layer.
The inner field plate 128 may be electrically connected to at least a subset of the active trench structures 108 and/or to a voltage source (e.g., ground) and is configured to control an electric field distribution in the edge termination region 104. Specifically, the inner field plate 128 may be configured as an electrode disposed over at least a portion of the moat structure 118 to redistribute the electric field away from the active region 102 and to mitigate a peaking of the electric field in the edge termination region 104 and in the active region 102 proximate the edge termination region 104, such as in or near the last active mesa 126. In general terms, field plates help reduce the maximum electric field, achieve a desirable electrical field profile across a defined region (e.g., moat structure 118), and increase breakdown voltage of the device. The amount of lateral (i.e., horizontal) extension of the inner field plate 128 over the moat structure 118, in the x-direction and/or y-direction, may be adjusted to control a profile of the electric field distribution in the edge termination region 104 and in the region of active area adjacent to the moat structure 118.
Optionally, the IC die 100 may further include an outer field plate 130 formed over at least a portion of the upper surface of the insulating layer 124, proximate the boundary trench structures 114. The outer field plate 130 may be electrically connected to one or more of the boundary trench structures 114, and may be configured to confine the electric fields to inside the insulating materials (e.g., insulating layer 124) of the moat structure 118. In a manner consistent with the configuration of the inner field plater 128, the amount of extension of the outer field plate 130 over the moat structure 118 (in the x-direction and/or y-direction) may be adjusted to control the electric field distribution in the edge termination region 104.
With reference to
Next, a first metal layer process 210 may be performed. The first metal layer process 210 may be used to form electrodes for providing electrical connection to the active region devices. In process step 212, an etch may be performed outside of a last active trench structure in the active region (adjacent to an edge termination region of the device) to form a wide trench (e.g., 120 in
The illustrative fabrication method 200 can be beneficially employed for various different types of active region devices (e.g., metal-oxide semiconductor (MOS) transistors, Schottky devices, etc.). Accordingly, it is to be understood that integration of edge termination structures according to aspects of the present inventive concept with the various active region devices may involve some of the processes necessary for the active device fabrication being interspersed between processes required for fabricating the novel edge termination structure, depending on the type of active device(s) being formed.
For example, one or more implants requiring a high thermal budget (e.g., greater than about 1000° C.) may be performed at a start of the fabrication process. A gate trench formation process may be performed either before or after the deep trench etch and fill process. Shallow implants (e.g., as may be used in creating source and drain regions in the active region of the device) requiring minimal thermal budgets (e.g., less than about 1000° C.) may be performed following the trench fill process. Forming active trenches (e.g., 108 bin
With reference to
The semiconductor die 300 may include an edge termination region 306, in which an edge termination structure according to embodiments of the invention is formed, and an active region 308, in which one or more active devices (e.g., Schottky device, MOSFET, etc.) may be formed. The edge termination region 306 preferably includes at least one outer trench 310 and, optionally, at least one boundary trench 312; the active region 308 may include a plurality of active trench 313. Each of the trenches preferably extends substantially vertically (i.e., perpendicular to an upper surface of the substrate 302) at least partially into or through the drift region 304, and may extend partially into the substrate 302, in one or more embodiments.
The outer trench 310 may also be considered a “boundary” trench, since it is disposed in the edge termination region 306 of the device. Therefore, the outer trench 310 may be referred to herein as an “inner boundary trench,” and the boundary trench 312 may be referred to as an “outer boundary trench;” these terms may be used interchangeably throughout the specification.
In one or more embodiments, the trenches 310, 312, 313 may be formed using a high aspect ratio deep trench etch process, such as, for example, deep reactive ion etching (DRIE). Advantageously, the same trench mask and etch process may be used for forming the trenches in both the edge termination region 306 and the active region 308. For the trench etch process, a trench mask may be used which comprises a photoresist mask or hard mask (e.g., a thin film of silicon dioxide (SiO2) and/or silicon nitride (SiN) that is patterned using a standard photolithographic process). The outer trench 310 may be formed having the same dimensions as the active trenches 313, although in one or more embodiments, the outer trench 310 (and the boundary trench 312, if present) may be formed wider (in a horizontal direction) than the active trenches 313. This enables the outer trench 310 to be etched deeper, which in turn allows more process margin for forming a moat structure used in the edge termination structure, since the moat structure should not be deeper than the outer trench 310. For example, in some embodiments, a width (in the horizontal direction) of each of at least a subset of the active trenches 313 may be about 1 μm and a width of the outer trench 310 may be about 2 μm, although the present inventive concept is not limited to any specific dimensions for the trenches.
A last mesa 314 in the active region 308 may be defined as a region of the epitaxial layer 304 between a last active trench of the plurality of active trenches 313 and the outer trench 310 in the edge termination region 306. In one or more embodiments, a width of the last mesa 314 may be configured to beneficially control (i.e., optimize) charge balance in the last mesa, to thereby account for a difference in charge due to the moat structure (to be formed between the outer trench 310 and the boundary trench 312) in the edge termination region 306. Optionally, the boundary trench 312 will define an outer boundary of the moat structure; if the boundary trench 312 is omitted, the outer trench of an adjacent die formed on the same wafer (before dicing) effectively becomes the boundary trench for defining a width of the moat structure. Although only one boundary trench 312 is shown in the illustrative embodiment of
With reference to
Although not explicitly shown (but implied), the trench fill process may also incorporate the deposition of layers that introduce fixed charge to create a charge balance structure; that is, the insulating layer(s) 316 may comprise one or more fixed charge layers. For example, alumina (Al2O3), which has a net negative static charge associated therewith, may be deposited inside at least a subset of the active trenches 313, for example using an atomic layer deposition (ALD) process. Alternatively, for a device using n-type epitaxial layer 304, thin doped epitaxial layers could be grown on the sidewalls of the trenches prior to filling, or a p-type species (i.e., dopant) may be diffused into the mesas (e.g., mesa 314) between adjacent active trenches 313 via the trench sidewalls prior to the trench fill process.
The outer and boundary trenches 310, 312 may be formed concurrently with the active trenches 313 using the same process. In this manner, the outer and boundary trenches 310, 312 may have the same fixed charge as the active trenches 313. Using the same processing to form the outer and boundary trenches 310, 312 as the active trenches 313 may have advantages, at least from a cost perspective. It is to be appreciated, however, that embodiments are contemplated in which the outer and boundary trenches 310, 312 are processed differently compared to the active trenches 313, particularly if it is desirable to avoid adding fixed charge to the outer and boundary trenches or to form outer and boundary trenches 310, 312 having a different fixed charge (or no fixed charge) relative to the active trenches 313. Once filled, each of the trenches 310, 312, 313 may be referred to herein as a “trench structure,” which may be used interchangeably with the term “trench” depending on the context in which the term is used.
Following the trench fill process, some of the insulating layer material 316 may extend laterally (i.e., horizontally) onto at least a portion of an upper surface of the epitaxial layer 304. This portion of the insulating layer material extending on the upper surface of the epitaxial layer 304 may be removed, such as, for example, by chemical mechanical polishing (CMP) and/or etching (wet and/or dry etching), such that the upper surface of the semiconductor die 300 is substantially planar. Alternatively, the insulating layer 316 extending on the upper surface of the epitaxial layer 304 may be patterned and partially etched (e.g., using photolithography) and used as part of the device structure, in accordance with one or more embodiments.
With reference now to
By way of example only and without limitation, in the case of forming a Schottky device, the metallization process may involve depositing a first metal layer 318 on an upper surface of the active region 308, including upper surfaces of the active trench structures 313 and upper surfaces of the mesas (e.g., 314) between adjacent active trench structures. At least a portion of the first metal layer 318 may be patterned and configured to act as a Schottky barrier layer of the device. In one or more embodiments, the first metal layer 318 may extend (horizontally) on a portion of the upper surface of the epitaxial layer 304 in the edge termination region 306, including on an upper surface of the outer trench structure 310. However, the first metal layer 318, in the illustrative embodiment shown, does not extend over the boundary trench structure 312, so that at least a portion of the upper surface of the epitaxial layer 304 between the outer trench 310 and the boundary trench 312 is exposed. The term “exposed” (or “expose,” or like terms) may be used herein to describe relationships between elements and/or with reference to intermediate processes in fabricating a semiconductor device, but may not require exposure of a particular element in the completed device. Likewise, the term “not exposed” may be used to described relationships between elements and/or with reference to intermediate processes in fabricating a semiconductor device, but may not require a particular element to be unexposed in the completed device.
A thin insulating layer 320 (e.g., about 0.1 μm thick, although embodiments are not limited thereto) may be formed over an upper surface of the die 300, including on at least a portion of an upper surface of the first metal layer 318 in the active region 308 and on at least a portion of the upper surface of the epitaxial layer 304 and first metal layer 318 in the edge termination region 306. This thin insulating layer 320, which may comprise, for example, silicon dioxide (or an alternative insulating material) formed using a deposition process or the like, may be used to protect the first metal layer 318 from subsequent processing and/or as an adhesion or stress relief layer for subsequent layers that may be provided on the first metal layer.
The first metal layer 318 and thin insulating layer 320 may act as a mask to protect the active region 308 during subsequent etching of the moat structure, as will be described in further detail below. During the moat etch process, the outer trench 310 and boundary trench 312 will preferably act as an etch stop for defining sidewalls of the moat structure. When an isotropic etch is used to form the moat structure (i.e., a process that selectively etches both laterally and vertically), then a field plate can be created by allowing the first metal layer 318 to extend partially into the edge termination region 306 between the outer trench 310 and boundary trench 312, since an isotropic etch will remove the silicon underneath the metal layer, stopping only when the etchant reaches the outer trench 310; if an isotropic etch is employed, the first metal layer 318 would preferably cover the last mesa 314 and all or at least part of the outer trench 310. Note, that it is possible to create the moat structure prior to the metallization process if a suitable moat fill material is used that can withstand the processes associated with deposition and etching of the metal.
Referring to
Note, that a width and depth of the moat 322 will be a function of one or more factors, such as, for example, a desired voltage blocking requirement of the device, field plate length (i.e., extension) over the moat 322, and properties of the material(s) used to line and/or fill the moat 322. Preferably, the depth of the moat 322 (in a vertical direction) may be close to a depth of the outer and boundary trenches 310, 312. Note, that if an isotropic etch is used to form the moat 322, the moat depth should not be greater than the depth of the outer trench 310, since the etch may remove material underneath the outer trench 310, which is undesirable. For at least this reason, it is advantageous (although not strictly necessary) for the outer and boundary trenches 310, 312 to be deeper than the active trenches 313. As previously stated, the outer and boundary trenches 310, 312 can be etched deeper by making them wider. In one or more embodiments, the width of the outer and boundary trenches 310, 312 is at least twice the width of the active trenches 313 (e.g., about 1 μm wide for the active trenches 313 and at least about 2 μm wide for the outer and boundary trenches 310, 312), although embodiments are not limited to any specific ratio of widths of the outer and boundary trenches 310, 312 to the active trenches 313.
In one or more illustrative embodiments, an extension of the first metal layer 318 over the moat 322 (in a horizontal direction) may be about equal to a depth (in a vertical direction) of the moat 322. For example, the moat 322 depth may be about 20 μm and an extension of the first metal layer 318 over the moat 322 may be about 18 μm, although the present inventive concept is not limited to any specific dimensions of the moat 322 and/or horizontal extension of the first metal layer 318 over the moat 322. The moat 322 may be etched vertically through the epitaxial layer 304 and partially into the substrate 302, although embodiments of the invention contemplate that the moat 322 may be etched only partially through the epitaxial layer 304 without extending into the substrate 302.
With reference to
For a typical power device, it may be known to have a silicon dioxide layer above the metal, followed by a silicon nitride or silicon oxynitride layer, followed by polyimide. In the integration according to aspects of the present inventive concept, those same materials may be employed. For example, in some embodiments, silicon dioxide may be deposited prior to the moat etch process (although the silicon dioxide may also be deposited after the moat etch). Following the moat etch process, a layer of silicon oxynitride may be deposited, followed by a polyimide deposition.
As shown in
Although the upper surface of the second insulating layer 326 over the moat 322 is shown as being planar with the upper surface of the second insulating layer lying outside of the moat area, there may be a dip in the upper surface of the second insulating layer 326, represented by dotted contour line 332. This dip 332 in the upper surface of the second insulating layer 326 over the moat 322 may result, for example, from the moat fill process; that is, an upper surface of the second insulating layer 326 in the moat 322 may not be planar, and therefore the second metal layer 328, which may follow a contour of the upper surface of the second insulating layer 326, may be non-planar. Accordingly, an end portion of the second metal layer forming the second field plate 330 may follow this dip 332 in the upper surface of the second insulating layer 326, which may influence, to some extent, the electric field distribution in the moat area. Creating such a dip 322 in the moat fill process to reduce the height of the metal field plate can be beneficial in optimizing the electric field curvature.
As will be described in further detail in conjunction with the illustrative embodiments shown in
By way of example only and without limitation or loss of generality,
With reference to
In a similar manner, the semiconductor device 420 may be further configured such that a second part of the second metal layer 328 is formed on at least a portion of the epitaxial layer 304 in the edge termination region 306 and over the second insulating layer 326 proximate the boundary trench 312. The second part of the second metal layer 328 preferably extends laterally over the moat structure from the boundary trench 312 edge towards the outer trench 310 edge of the moat structure. The extension of the second metal layer 328 over the moat structure forms a primary outer field plate. An amount of extension of the first and second parts of the second metal layer 328 over the moat structure may be controlled to achieve a desired electric field distribution in the moat structure. However, the first and second parts of the second metal layer 328 are not electrically connected to one another.
The semiconductor device 440 may be further configured having the second metal layer 328 formed on at least a portion of the first metal layer 318 and extending laterally on the second insulating layer 326 over a portion of the moat structure in the edge termination region 306, in a manner consistent with the arrangement of the second metal layer 328 shown in
With reference now to
In the semiconductor device 460, a first part of the second metal layer 328 may be formed on at least a portion of the first metal layer 318 and may extend laterally on the second insulating layer 326 over a portion of the moat structure in the edge termination region 306, proximate the outer trench 310, to form a secondary inner field plate. The semiconductor device 460 may be further configured such that a second part of the second metal layer 328 is formed on at least a portion of the epitaxial layer 304 in the edge termination region 306 and over the second insulating layer 326 proximate the boundary trench 312. The second part of the second metal layer 328 preferably extends laterally over the moat structure from the boundary trench 312 edge towards the outer trench 310 edge. The extension of the second part of the second metal layer 328 over the moat structure forms a primary outer field plate. An amount of extension of the first and second parts of the second metal layer 328 over the moat structure may be selectively varied to achieve a desired electric field distribution in the moat structure.
The use of a moat termination structure (e.g., including moat 322 and materials lining and/or filling the moat), created either using a single trench 310 or bounded by multiple separate trenches 310, 312, may create an imbalance in the charge seen in the last mesa 314 (sec
In general, in a charge balanced device, there is a charge balance region where a charge in the charge balance region, QP, matches a charge in the mesa region, QN.
If the charge QPE in the boundary trench 310 and the fixed charge in the moat, Qmoat, does not equal the charge QNE in the last mesa 314, then charge balance may not be achieved and a reduced breakdown voltage will likely result (i.e., QPE+Qmoat≠QNE). In this case, the charge in the last mesa QNE may be modified, according to one or more embodiments, to accommodate this difference in charge. This can be achieved in several ways, including by varying the width (in a horizontal (x) or lateral direction) of the last mesa 314, among other approaches (e.g., modifying the material in the last mesa 314 or moat structure, varying the dimensions of the moat structure, etc.). For example, if QPE+Qmoat>QNE, then the width of the last mesa 314 can be increased to thereby increase the charge associated with the last mesa. Likewise, if QPE+Qmoat<QNE, then the width of the last mesa 314 can be decreased to reduce the charge associated with the last mesa.
A further consideration is that the moat structure functions essentially as a capacitor that may induce an additional charge on an inside edge of the outer trench 310. This induced charge will be proportional to the applied voltage according to expression Q=CV, where Q is the charge in Coulombs, C is the capacitance in Farads, and V is the potential difference between the plates of the capacitor in volts. The capacitance being proportional to the lateral width (in a horizontal (x) direction) of the moat structure and a relative permittivity of the insulting material(s) (e.g., first and second insulating layers 324, 326) within the moat, the following expression may be obtained:
where CEDGE is the capacitance at an edge of the moat structure, ε0 is a constant representing the permittivity of free space, εmoat is the permittivity of the insulating materials in the moat, and w is the width of the moat 322 (i.e., the distance between an inside edge of the inner boundary trench 310, facing towards the active region 308, and an outside edge of the outer boundary trench 312, facing away from the active region).
At the device corner, the area of the moat with respect to the active area will be larger and hence the capacitive effect (and impact of fixed charge within the moat) will be greater. The capacitance at the corner of the device, CCORNER, can be determined in accordance with the following expression:
where R1 is an inner radius of the moat, as defined by the outer trench 310, and R2 is an outer radius of the moat, as defined by the boundary trench 312. The inner radius R1 and outer radius R2 are conceptually illustrated in
By way of example only and without limitation or loss of generality,
Generally, a series of parallel active trench structures 313 may be formed in the active region 308 of the device, surrounded by (i.e., extending around) an inner boundary trench structure 702, as shown in
In this embodiment, the last active trench structure 722 extends proximate an inner edge of the inner boundary trench structure 702 in both a first direction and a second direction, the first and second directions being parallel to an upper surface of a substrate of the semiconductor device 720 (i.e., in a horizontal plane), the second direction intersecting the first direction. The other active trench structures 313 may be parallel to one another, all extending in either the first direction or the second direction.
One or more of the concentric rings of active trench structures 722, 732, 734, 736 may optionally be formed with breaks or gaps 738 therein, which may aid in fabrication and/or charge balancing of the device. Specifically, the use of long trenches can add stress to the device causing wafer bow and other manufacturing difficulties, so adding gaps 738 in the trench structures can alleviate this stress. A further benefit of the gaps 738 in the active trench structures 722, 732, 734 and/or 736 is that they can promote current flow between the active trench structures to thereby alleviate current crowding and potentially help reduce hot spots in the device, as heat can also spread more effectively (since the active trench structures may be filled with an insulating material that may be a poor conductor of heat). In the extreme, islands of charge balance regions are better than stripes.
Referring to
In this example embodiment, the active area trench structures 313 are parallel to one another in a first horizontal direction and are spaced apart from one another in a second horizontal direction perpendicular to the first horizontal direction. The active area trench structures 313 extend continuously in the first horizontal direction into the inner boundary trench structure 702, without a gap, although embodiments are not limited thereto. This layout may be most suitable for when there is no charge QPE in the wider edge termination.
With reference to
Note, that due to the corner of the semiconductor device 1000 potentially having different compensating charge, the horizontal width of the gap “D” between the end of the last active area trench structure 722 (i.e., the active trench structure closest to the corner) and the inner boundary trench structure 702 may be different than the horizontal width of the gap “C” between other active area trench structures 313 and the inner boundary trench structure 702.
In
A width of the gaps “C” and “D” between ends of the active area trench structures 313, 722 and the inner boundary trench structure 702, when viewed in a plan view (i.e., in a horizontal plane), may be adjusted for optimizing charge balance in the semiconductor device 1100, according to one or more embodiments. Alternatively or additionally, the horizontal width WB of the last mesa 904 may be adjusted, relative to the horizontal width WA of the mesas 314 between the other active area trench structures 313, for optimizing charge balance in the semiconductor device 1100.
In
The active trench structures 313, 722, like the active trench structures 313, 722 shown in
With reference to
In the embodiment shown in
The active trench structures 313 in the semiconductor device 1500 of
The inner boundary trench structure 702 may be a straight-line structure having a prescribed slope (e.g., about 45-degrees), as depicted in the semiconductor device 1500 of
Referring to
Referring to
Although the present disclosure provides several non-limiting examples of illustrative edge termination structures for use in a charge balanced semiconductor device, various modifications and changes can be made thereto without departing from the scope of the disclosure as set forth in the claims below, as may become apparent to those skilled in the art given the teachings herein. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure. Any benefits, advantages, or solutions to problems that are described herein with regard to a specific example are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
Although the overall fabrication methods and the structures formed thereby are entirely novel, certain individual processing steps required to implement the method may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tooling. These techniques and tooling will already be familiar to those having ordinary skill in the relevant arts given the teachings herein. Moreover, many of the processing steps and tooling used to fabricate semiconductor devices are also described in a number of readily available publications, including, for example: P. H. Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008; and R. K. Willardson et al., Processing and Properties of Compound Semiconductors, Academic Press, 2001, which are both hereby incorporated herein by reference in their entireties for all purposes. It is emphasized that while some individual processing steps are set forth herein, those steps are merely illustrative, and one skilled in the art may be familiar with several equally suitable alternatives that would also fall within the scope of the invention.
It is to be appreciated that the various layers and/or regions shown in the accompanying figures may not be drawn to scale. Furthermore, one or more semiconductor layers of a type commonly used in such semiconductor devices may not be explicitly shown in a given figure to facilitate a clearer description. This does not imply that the semiconductor layer(s) not explicitly shown are omitted in the actual device.
In one or more embodiments, formation of the exemplary device structures described herein may involve deposition of certain materials and layers by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), or any of the various modifications thereof, including, for example, plasma-enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), electron-beam physical vapor deposition (EB-PVD), and plasma-enhanced atomic layer deposition (PE-ALD). The depositions can be epitaxial processes, and the deposited material can be crystalline. In one or more embodiments, formation of a layer can be achieved using a single deposition process or multiple deposition processes, where, for example, a conformal layer is formed by a first process (e.g., ALD, PE-ALD, etc.) and a fill is formed by a second process (e.g., CVD, electrodeposition, PVD, etc.); the multiple deposition processes can be the same or different.
As used herein, the term “semiconductor” may refer broadly to an intrinsic semiconductor material that has been doped, that is, into which a doping agent has been introduced, giving it different electrical properties than the intrinsic semiconductor material, or it may refer to intrinsic semiconductor material that has not been doped. Doping may involve adding dopant atoms to an intrinsic semiconductor material, which thereby changes electron and hole carrier concentrations of the intrinsic semiconductor material at thermal equilibrium. Dominant carrier concentration in an extrinsic semiconductor material determines the conductivity type of the semiconductor material.
The term “metal,” as used herein, is intended to refer to any electrically conductive material, regardless of whether the material is technically defined as a metal from a chemistry perspective or not. Thus “metals” as used herein will include such materials as, for example, aluminum, copper, silver, gold, etc., and will include such materials as, for example, graphene, germanium, gallium arsenide, highly-doped polysilicon (commonly used in most MOSFET devices), etc. This is to be distinguished from the definition of a “metal” from a physics perspective, which usually refers to those elements having a partially filled conduction band and having lower resistance toward lower temperature.
As used herein, the term “insulating” may generally denote a material having a room temperature conductivity of less than about 10−10 (Ω-m)−1. Suitable insulating materials may include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, boron nitride, high-dielectric constant (high-k) materials, or any combination of these materials. Non-limiting examples of high-k materials may include, for example, metal oxides, such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, ceramics, etc. High-k materials may further include dopants such as lanthanum, aluminum, etc.
As used herein, “p-type” may refer broadly to the addition of impurities to an intrinsic semiconductor material that creates deficiencies of valence electrons. In a silicon-containing material, non-limiting examples of p-type dopants (i.e., impurities) include boron, aluminum, gallium and indium.
As used herein, “n-type” may refer broadly to the addition of impurities that contribute free electrons to an intrinsic semiconductor material. In a silicon-containing material, non-limiting examples of n-type dopants include antimony, arsenic and phosphorous.
It will also be understood that when an element such as a layer, region or substrate is referred to as being “atop,” “above,” “on” or “over” another element, it is broadly intended that the element be in direct contact with the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, it is intended that there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Furthermore, positional (i.e., directional) terms such as “above,” “below,” “upper,” “lower,” “under,” and “over” as may be used herein, are intended to indicate relative positioning of elements or structures to each other as opposed to absolute position.
At least a portion of the techniques of the present invention may be implemented in an integrated circuit. In forming integrated circuits, identical die are typically fabricated in a repeated pattern on a surface of a semiconductor wafer. Each die includes a device described herein, and may include other structures and/or circuits. The individual die are cut or diced from the wafer, then packaged as an integrated circuit. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Any of the exemplary structures illustrated in the accompanying figures, or portions thereof, may be part of an integrated circuit. Integrated circuits so manufactured are considered part of this invention.
Those skilled in the art will appreciate that the exemplary structures discussed above can be distributed in raw form (i.e., a single wafer having multiple unpackaged chips), as bare dies, in packaged form, or incorporated as parts of intermediate products or end products that benefit from having enhanced edge termination structures therein (e.g., power IC devices) formed in accordance with one or more embodiments of the invention.
An integrated circuit in accordance with aspects of the present disclosure can be employed in essentially any application and/or electronic system involving enhanced breakdown voltage structures, such as, but not limited to, power metal-oxide semiconductor field-effect transistors (MOSFETs), Schottky diodes, etc. Suitable systems and applications for implementing embodiments of the invention may include, but are not limited to, AC-DC and DC-DC conversion, motor control, and power supply OR-ing (“OR-ing” is a particular type of application that parallels multiple power supplies to one common power bus in a redundant power system architecture). Systems incorporating such integrated circuits are considered part of this invention. Given the teachings of the present disclosure provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.
The illustrations of embodiments of the invention described herein are intended to provide a general understanding of the various embodiments, and they are not intended to serve as a complete description of all the elements and features of apparatus and systems that might make use of the structures and semiconductor fabrication methodologies described herein. Many other embodiments will become apparent to those skilled in the art given the teachings herein; other embodiments are utilized and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of this disclosure. The drawings are also merely representational and are not necessarily drawn to scale. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Embodiments of the invention are referred to herein, individually and/or collectively, by the term “embodiment” merely for convenience and without intending to limit the scope of this application to any single embodiment or inventive concept if more than one is, in fact, shown. Thus, although specific embodiments have been illustrated and described herein, it should be understood that an arrangement achieving the same purpose can be substituted for the specific embodiment(s) shown; that is, this disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will become apparent to those of skill in the art given the teachings herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step-plus-function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the various embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the various embodiments with various modifications as are suited to the particular use contemplated.
The abstract is provided to comply with 37 C.F.R. § 1.72 (b), which requires an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the appended claims reflect, inventive subject matter lies in less than all features of a single embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.
Given the teachings of embodiments of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of embodiments of the invention. Although illustrative embodiments of the invention have been described herein with reference to the accompanying drawings, it is to be understood that embodiments of the invention are not limited to those precise embodiments, and that various other changes and modifications are made therein by one skilled in the art without departing from the scope of the appended claims.
This application claims the benefit of and priority under 35 U.S.C. § 119 to U.S. Provisional Application No. 63/498,962, filed on Apr. 28, 2023, entitled “Non-conducting Edge Termination Structures for a Semiconductor Device and Methods of Fabricating the Same,” the disclosure of which is incorporated by reference herein in its entirety for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 63498962 | Apr 2023 | US |
