Patent Application
20060278913
The present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory devices.
Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
As computers become smaller and their performance increases, the computer memories have also gone through a corresponding size reduction and performance increase. However, flash memory devices present a challenge in scalability due, at least in part, to the high programming voltages typically required. Additionally, due to required real estate for contacts and other memory circuitry, the density of a memory device is also limited.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a more scalable, higher density non-volatile memory device.
The above-mentioned problems with scalable memory and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
The embodiments of the present invention encompass a memory device fabricated on a substrate. A plurality of memory cell stacks are formed over the substrate. Each memory cell stack is coupled to adjacent memory cell stacks only through an electric field generated by each stack.
In one embodiment, the substrate is comprised of a p-type silicon in which an n-layer is implanted near the top. The memory cells are fabricated over the n-layer. The memory cell stacks can be comprised of a tunnel dielectric, a floating gate, a gate dielectric, and a control gate.
Further embodiments of the invention include methods and apparatus of varying scope.
In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof. The terms wafer or substrate used in the following description include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and terms wafer or substrate include the underlying layers containing such regions/junctions.
Each memory cell 109-112 is comprised of a floating gate 121 that stores the charge for the cell. The floating gate 121 is formed over a tunnel dielectric layer 119 and substantially between a pair of source/drain diffusion areas 101-104.
A gate dielectric layer 122 is formed over the floating gate 121 to isolate the control gate 120 from the floating gate 121. The floating gate 121 and the control gate 120 can be comprised of silicon material and the gate dielectric layer 122 is an interpoly dielectric.
For purposes of clarity, not all of the elements of a memory column in a memory array are shown. In one embodiment, a series string of memory is comprised of 32 memory cells. However, alternate embodiments can use other quantities of memory cells such as 8 or 16. The series string of memory cells illustrated in
The memory cells 209-212 are fabricated on a silicon substrate 200. In one embodiment, the substrate 200 is a p-type silicon. However, the present invention is not limited to any one conductivity substrate or material.
A tunnel dielectric layer 223 is formed over the substrate 200. This layer can be comprised of an oxide such as silicon dioxide (SiO2) or another material such as a high dielectric constant (high-K) material. In one embodiment, a high dielectric constant is considered to be a dielectric constant that is greater than that of SiO2. For example, LaAlO can be used as the high-k tunneling gate dielectric 223 instead of SiO2. Alternate embodiments may use other dielectrics having other dielectric constants.
The floating gate layer 222 is formed over the tunnel dielectric layer 223. In one embodiment, this charge storage layer 222 is a polysilicon material and is thinner than the prior art floating gate. In one embodiment, the floating gate layer 222 is formed less than 2000 Å. Alternate embodiments use other thicknesses. In another embodiment, the charge storage layer 222 and the dielectric layers 223, 221 are formed as an oxide-nitride-oxide (ONO) film.
An intergate dielectric layer 221 is formed over the floating gate 222. The intergate layer 221 and the tunnel dielectric isolate the floating gate 222 from the control gate 220 and the substrate 200, respectively. The intergate dielectric layer 221 can be comprised of an oxide material or some other type of insulator. A polysilicon layer 220 is formed over the intergate dielectric layer 221 to act as the control gate 220 for each cell. In an alternate embodiment, the control gate 220 can be formed from a metal layer.
The above-described layers, in one embodiment, use a known hard mask and spacer etch process to form the individual memory cells 209-212 of the memory column. The distance between the memory cells 209-212 of the embodiments of the present invention is substantially reduced from the prior art. A typical distance between memory cells of the prior art is in a range of 50 to 180 nm, depending on minimum lithography size and etching methods used in fabrication. The lack of diffusion areas in the present invention allows the memory cell stacks to be formed closer together. In one embodiment, the stacks can be formed within a range of 5-90 nm apart. This permits the electric fields 250-255 generated by each floating gate to be coupled to an adjacent electric field 250-255. The reduced distance permits a greater number of memory cells to fit in each column, thus increasing the density of the flash memory device. The present invention, however, is not limited to any one distance or range of distances between memory cell stacks. Alternate embodiments may use other distances or ranges.
In one embodiment, an n-layer 230 is implanted on the surface of the substrate 200. This layer 230 is not required for proper operation of the memory cells. However, such a layer 230 increases the conductivity of the channels under each gate. Such a layer may be less than 0.1 μm from the top of the substrate.
Each end of each series string of memory cells 209-212 is coupled to a select transistor 213, 214 that controls access to the string of cells 209-212. One end has a select gate drain transistor 213 and the other end a select gate source transistor 214. Each transistor 213, 214 couples the respective end to the bit line or the source line.
In one embodiment, the right drain diffusion region and the left source diffusion region are not needed. The right memory cell 212 is formed close enough to the select gate drain transistor 213 so that the electric field of the floating gate interacts with the electric field of the select gate transistor 213. Similarly, the left memory cell is formed close enough to the select gate source transistor 214 such that the electric field of the floating gate interacts with the electric field of the select gate transistor 214. Such an embodiment enables the transistors to be formed even closer together.
The memory device of the present invention is programmed in a substantially similar way as prior art memory devices. This method includes a series of programming pulses on a selected word line and an inhibit voltage (e.g., VCC) on the array bit lines that are not to be programmed. The bit lines with memory cells to be programmed are typically biased at ground potential. The series of programming voltages may start at an initial high voltage (e.g., 16V) and increment by predetermined voltages until either the cell or cells are programmed or an error condition exists.
However, since the embodiments of the present invention do not use diffusion regions, the physical mechanism of a program inhibit operation is different than the prior art mechanism. In a prior art NAND device, the program inhibit occurs when bit lines to be inhibited are biased at VCC and the string inversion layer and diffusions experience channel bootstrap or coupling to a high voltage by the unselected word lines. In the present invention of the string of cells with no diffusion regions, the program inhibit is ensured by the formation of a deep depletion area in the substrate under the string of cells using substantially similar bias conditions. This leads to a suppression of electron tunneling by reduction of the tunnel oxide field due to an increased voltage drop in the channel region under the memory cell stack.
The array is comprised of an array of floating gate cells 301 arranged in series strings 304, 305. Each of the floating gate cells 301 are coupled drain to source in each series chain 304, 305. A word line (WL0-WL31) that spans across multiple series strings 304, 305 is coupled to the control gates of every floating gate cell in a row in order to control their operation. The embodiment of
In operation, the word lines (WL0-WL31) select the individual floating gate memory cells in the series chain 304, 305 to be written to or read from and operate the remaining floating gate memory cells in each series string 304, 305 in a pass through mode. Each series string 304, 305 of floating gate memory cells is coupled to a source line 306 by a source select gate 316, 317 and to an individual bit line (BL1-BLN) by a drain select gate 312, 313. The bit lines (BL1-BLN) are eventually coupled to sense amplifiers (not shown) that detect the state of each cell.
The source select gates 316, 317 are controlled by a source select gate control line SG(S) 318 coupled to their control gates. The drain select gates 312, 313 are controlled by a drain select gate control line SG(D) 314.
Each cell can be programmed as a single bit per cell (SBC) or multiple bits per cell (i.e., multilevel cell—MLC). Each cell's threshold voltage (Vt) determines the data that is stored in the cell. For example, in a single bit per cell, a Vt of 0.5V might indicate a programmed cell while a Vt of −0.5V might indicate an erased cell.
During a typical prior art programming operation, the selected word line for the flash memory cell to be programmed is biased with a programming pulse at a voltage that is greater than 16V. A verification operation with a word line voltage (e.g., 0.5V) is then performed to determine if the cell threshold voltage has been increased to the corresponding level of 0.5V in the program operation. The unselected word lines for the remaining cells are typically biased at approximately 10V during the program operation. Each of the memory cells is programmed in a substantially similar fashion.
The cells of
Therefore, simulation shows that gate-controlled fringing electric field can provide excellent on-off characteristics. Additionally, the present invention provides enough margin with regard to “programmed” (floating voltage around −1V, current less than 1 pA per bit line) and “erased state” (floating gate voltage around +1V, current more than 1 μA per bit line).
The memory device includes an array of memory cells 730 that can be comprised of the non-volatile memory cells previously illustrated. The memory array 730 is arranged in banks of rows and columns as illustrated in
An address buffer circuit 740 is provided to latch address signals provided on address input connections A0-Ax 742. Address signals are received and decoded by a row decoder 744 and a page decoder 746 to access the memory array 730. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array 730. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.
The memory device 700 reads data in the memory array 730 by sensing voltage or current changes in the memory array columns using read/write page latch circuitry 750. This circuitry 750, in one embodiment, is coupled to read and latch a page of data from the memory array 730 and includes the sense amplifiers of the memory device 700. Data input and output buffer circuitry 760 is included for bi-directional data communication over a plurality of data connections 762 with the controller 710.
Control circuitry 770 decodes signals provided on control connections 772 from the processor 710. These signals are used to control the operations on the memory array 730, including data read, data write (program), and erase operations. The control circuitry 770 may be a state machine, a sequencer, or some other type of controller.
The memory device illustrated in
The embodiments of the present invention provide the ability to fabricate denser memory devices due to the lack of diffusion areas between the cells of a series string. The fabrication is also made easier since the step for implanting the diffusion areas is no longer required.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.
