The present invention relates to integrated nonvolatile memories.
Bitlines 160 are connected to a circuit 180 which performs bitline selection, driving and sensing as needed for the memory operation. Wordline driving circuitry (not shown) is also provided.
Cell 110 is programmed by channel hot electron injection. During the programming, the cell's wordline 104 is at a high voltage (12V), one of the cell's source/drain regions 160 (one of the bitlines) is at 8˜9V, and the other source/drain region is grounded. To read the cell, the corresponding wordline is driven to 5V, one of the corresponding bitlines 160 is driven to 2V, and the other bitline is grounded. The array is erased by ultraviolet light.
This section summarizes some features of the invention. Other features are described in the subsequent sections. The invention is defined by the appended claims which are incorporated into this section by reference.
In some embodiments of the present invention, a memory cell includes two floating gates between each pair of adjacent bitlines. One embodiment is shown in
The memory structure is in some respects similar to one proposed in U.S. Pat. No. 6,897,517 issued on May 24, 2005 to Van Houdt et al., but there are important differences. In the memory of
The invention is not limited to the features and advantages described above. Other features and advantages are described below. The invention is defined by the appended claims.
The embodiments described in this section illustrate but do not limit the invention. The invention is defined by the appended claims.
In the drawings, all the vertical cross sections are along a wordline unless specifically noticed otherwise.
As shown in
In each cell 110, each transistor 110L, 110R has two states, so the cell has four states: State 1 is when both the left bit (110L) and the right bit (110R) are programmed; State 2 is when the left bit is programmed and the right bit is erased; State 3 is when the left bit is erased and the right bit is programmed; State 4 is when both the left bit and the right bit are erased. In some embodiments, the following voltages and currents are believed to be achievable.
Option 1. In this option, the cells are programmed by hot hole (HH) injection: hot holes are injected from a floating gate 120 (i.e. 120L or 120R) into substrate 130. The cells are erased by FN tunneling of electrons from channel region 170 into the floating gates 120. A whole row of cells is erased in one erase operation (a row consists of the cells sharing a wordline 104). The voltages are as follows.
The reading operation is described below.
Option 2. In this option, the cells are programmed by channel hot electron injection (CHEI): hot electrons are injected from substrate 130 into floating gates 120. The cells are erased by FN tunneling of electrons from floating gates 120L, 120R into the respective channel regions 220L, 220R.
The read operation (Table 6) can be identical for Options 1 and 2.
The invention does not rely on the inventors' understanding of the programming or erasing mechanisms (e.g. whether the voltages of Table 1 really cause a hot hole injection or some other phenomenon leading to a transistor 110L becoming programmed). The invention is not limited to particular voltages, currents, or programming mechanisms.
Then another mask is formed to define the threshold adjust implant regions. Suitable implants are performed into the array and/or peripheral memory regions. The mask is then removed.
Silicon oxide layer 140 (“tunnel oxide”) is thermally grown to an appropriate thickness (e.g. 9˜10 nm) on substrate 130. Doped polysilicon 120 is deposited on oxide 140. Photoresist mask 410 is formed on layer 120 and patterned to open a number of strips running in the column direction and including the bitline strips 160 and connection region strips 210i (
A photoresist layer 610 (
An N type dopant is implanted to dope the bitlines. In some embodiments, ion implantation of arsenic is used at an energy of 30˜40 KeV. An exemplary dopant concentration achieved is 1015 atoms/cm3. The dopant material and the concentrations and energy levels are exemplary and not limiting.
Photoresist 610 is removed. Dielectric 144 (
Another fabrication process is as follows. The fabrication proceeds as in
Then a connection implant (type N) is performed to dope the connection strips 210i (laid out as in
A photoresist layer 910 (
An N+ dopant is implanted to dope the bitlines 160. The implant parameters can be as described above for
Photoresist 910 and oxide 610 are removed. The memory fabrication can be completed in the same way as for
In another variation, the nitride strips 710 (
U.S. Pat. No. 5,705,415 issued Jan. 6, 1998 to Orlowski et al. describes some techniques to fabricate sidewall spacer floating gates in trenches. An exemplary fabrication process for the memory of
The remaining fabrication steps can be as in the embodiments of
The invention is not limited to the materials described. For example, doped polysilicon can be replaced with other conductive materials, and silicon dioxide can be replaced with other dielectrics. The P and N conductivity types can be reversed. P type substrate 130 can be replaced with an isolated P type well in P or N type substrate. The dimensions are exemplary and not limiting. Other embodiments and variations are within the scope of the invention, as defined by the appended claims.
Number | Name | Date | Kind |
---|---|---|---|
5422504 | Chang et al. | Jun 1995 | A |
5495441 | Hong | Feb 1996 | A |
5705415 | Orlowski et al. | Jan 1998 | A |
5929479 | Oyama | Jul 1999 | A |
5929492 | Okamura | Jul 1999 | A |
6433382 | Orlowski et al. | Aug 2002 | B1 |
6441430 | Tanigami | Aug 2002 | B1 |
6653682 | Houdt et al. | Nov 2003 | B1 |
6798015 | Kasuya | Sep 2004 | B2 |
6897517 | Van Houdt et al. | May 2005 | B2 |
6897533 | Yang et al. | May 2005 | B1 |
20040119109 | Kang | Jun 2004 | A1 |
20040129972 | Kasuya | Jul 2004 | A1 |
20050051833 | Wang et al. | Mar 2005 | A1 |
20060033147 | Tang | Feb 2006 | A1 |
20060175654 | Pan et al. | Aug 2006 | A1 |
Number | Date | Country |
---|---|---|
1 262 995 | Dec 2002 | EP |
1 376 676 | Jan 2004 | EP |
1 381 055 | Jan 2004 | EP |
Number | Date | Country | |
---|---|---|---|
20070120171 A1 | May 2007 | US |