This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2016-155106, filed Aug. 5, 2016, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a nonvolatile memory.
Currently, cash memories and main memories used in various systems are mainly volatile memories such as a static random access memory (SRAM) and a dynamic random access memory (DRAM). However, they have a problem that power consumption is large. Thus, an attempt of replacing the volatile memories used in various systems and, furthermore, storage memories with high-speed and low-power nonvolatile RAM has been reviewed.
In general, according to one embodiment, a nonvolatile memory comprising: a first conductive line extending in a first direction, and including a first portion, a second portion, a third portion provided between the first and second portions, and a fourth portion provided between the second and third portions; a first storage element including a first terminal and a second terminal, the first terminal being connected to the third portion; a first transistor including a third terminal, a fourth terminal, and a first electrode controlling a first current path between the third and fourth terminals, the third terminal being connected to the second terminal; a second storage element including a fifth terminal and a sixth terminal, the fifth terminal being connected to the fourth portion; a second transistor including a seventh terminal, an eighth terminal, and a second electrode controlling a second current path between the seventh and eighth terminals, the seventh terminal being connected to the sixth terminal; a second conductive line extending in the first direction and connected to the first and second electrodes; a third conductive line extending in a second direction crossing to the first direction and connected to the fourth terminal; and a fourth conductive line extending in the second direction and connected to the eighth terminal.
Embodiments will be described hereinafter with reference to the accompanying drawings.
(Memory System)
The memory system to which the embodiments are applied comprises a CPU (host) 11, a memory controller 12 and a nonvolatile RAM 13.
This memory system is employed in, for example, personal computers, electronic devices including cellular telephone terminals, image pickup devices including digital still cameras and video cameras, tablet computers, smartphones, game consoles, car navigation systems, printer devices, scanner devices, server systems and the like.
In the example of
In contrast, in the example of
The CPU 11 comprises, for example, CPU cores. The CPU cores are the elements which can execute different data processing parallel to each other. The memory controller 12 mainly controls a read operation and a write operation for the nonvolatile RAM 13.
The nonvolatile RAM 13 is a memory which can switch a multi-bit access (first mode) and a single-bit access (second mode).
The multi-bit access indicates accessing memory cells in a memory cell array in parallel and the single-bit access indicates accessing one memory cell in the memory cell array.
For example, a spin orbit torque (SOT)-magnetic random access memory (MRAM) is one of memories that can switch the multi-bit access and the single-bit access. The SOT-MRAM will be explained later.
In the memory system shown in
The sequential access is a mode of sequentially accessing (multi-bit) memory cells. For example, burst transfer employed in DRAM, a storage class memory (SCM) and the like is a type of the sequential access.
In the burst transfer, the memory controller 12 can omit, for example, transfer of a column address to the nonvolatile RAM (embodiments) 13 or transfer of a column address to the DRAM (comparative example) 13′ by issuing the first command (burst transfer command). A band width (data amount which can be transferred in a certain period) between the CPU and the memory (nonvolatile RAM or DRAM) can be therefore improved.
The random access is a mode of accessing one (single-bit) memory cell. In the random access, the memory controller 12 issues the second command (random access command) and transfers a row address and a column address to the nonvolatile RAM (embodiments) 13 or the DRAM (comparative example) 13′.
In the random access, latency (i.e., a period from the time when the CPU requests a certain amount of data to the time when the CPU receives the data) is reduced as compared with the sequential access since the data required by the CPU alone is accessed.
Thus, the memory controller 12 issues the first command to instruct the sequential access when the band width is considered with a higher priority or the second command to instruct the random access when the latency is considered with a higher priority.
In the embodiments, the nonvolatile RAM 13 can switch the first mode to execute the multi-bit access and the second mode to execute the single-bit access, in response to the first command and the second command.
For example, when the memory controller 12 issues the first command, the first command is transferred to an internal controller 13-2 via an interface 13-1. When the internal controller 13-2 confirms the first command, the internal controller 13-2 executes the multi-bit access to a memory cell array 13-3.
In addition, when the memory controller 12 issues the second command, the second command is transferred to the internal controller 13-2 via the interface 13-1. When the internal controller 13-2 confirms the second command, the internal controller 13-2 executes the single-bit access to a memory cell array 13-3.
Thus, the multi-bit access is executed inside the nonvolatile RAM 13 when the sequential access is instructed, and the single-bit access is executed inside the nonvolatile RAM 13 when the random access is instructed. An access efficiency inside the nonvolatile RAM 13 can be thereby increased.
In other words, increase in the band width (increase in the data transfer efficiency) can be first obtained as an effect of the sequential access by making the multi-bit access correspond to the sequential access. In addition to this, the time required for the read operation or the write operation is reduced and the access efficiency inside the nonvolatile RAM 13 is increased by executing the multi-bit access inside the nonvolatile RAM 13, in the embodiments.
In contrast, in the comparative example, the DRAM 13′ comprises an interface 13′-1 corresponding to the first command and the second command but an internal controller 13′-2 can only execute the single-bit access.
Therefore, even when the memory controller 12 issues the first command, the internal controller 13′-2 executes the single-bit access to the memory cell array 13′-3. In other words, when the sequential access (access to memory cells) is instructed, the internal controller 13′-2 must repeat access operations (operations of generating the column address and accessing the memory in response to the burst length).
If the sequential access is thus instructed in the comparative example, the time required for the read operation or the write operation is long and the access efficiency inside the DRAM 13′ is degraded since the access operations are executed inside the DRAM 13′.
When the first command to instruct the sequential access is issued, the nonvolatile RAM executes the multi-bit access. The multi-bit access is N-bit access to access N bits (N memory cells) parallel. N is a natural number of 2 or larger. When N is eight, the N-bit access is a byte access.
The I/O width at the N-bit access is, for example, n×N. n is the number of blocks (memory cores) in which the read operation or the write operation can be executed parallel. n is, for example, 64, 128, 256, and the like. The I/O width indicates the data amount which can be transferred between the interface 13-1 and the memory cell array 13-3 within a certain period, inside the nonvolatile RAM.
As shown in
In this case, n×N bits are transferred from the memory cell array 13-3 to the interface 13-1 via the internal bus (I/O width=n×N bits) in the read operation. The access efficiency in the nonvolatile RAM 13 is therefore improved in the read operation at the N-bit access.
However, the read operation in each of blocks BK_k (k is one of 1 to n) is executed in, for example, N cycles (N-time read operations). This is because one block BK_k includes one sense amplifier for convenience of layout. Since only one sense amplifier is included in each block BK_k, N cycles are required to read N bits from each block BK_k. This will be explained later.
However, each block BK_k includes, for example, a register and N bits read in N cycles are temporarily stored in the register. For this reason, n×N bits are transferred from the memory cell array 13-3 to the interface 13-1 via the internal bus (I/O width=n×N bits) in the read operation at the N-bit access as explained above.
Latency of the read operation at the N-bit access is tread×N. tread represents the latency in one cycle of the read operation (latency in reading one bit).
In addition, energy generated in the read operation at the N-bit access includes EWL, Ecol, and Esensing×N. However, EWL represents energy for activating the row (word line), Ecol represents energy for activating the column (column select line), and Esensing represents energy required to read the data by the sense amplifier.
In addition, as shown in
In this case, n×N bits are transferred from the interface 13-1 to the memory cell array 13-3 via the internal bus (I/O width=n×N bits) in the write operation. In addition, in each block BK_k (k is one of 1 to n) of the memory cell array 13-3, N bits transferred from the interface 13-1 are temporarily stored in the register. Therefore, in the write operation at the N-bit access, too, the access efficiency in the nonvolatile RAM 13 is improved, similarly to the read operation.
However, the write operation in each of the blocks BK_k is executed in, for example, two cycles (two write operations). This corresponds to a case where the nonvolatile RAM 13 is, for example, an SOT-MRAM.
In SOT-MRAM, for example, the same data (for example, 0) is written to N bits (N memory cells) in each block BK_k, in the first write operation. After this, N bits (N memory cells) in each block BK_k are held or changed as data (0 or 1) corresponding to the write data (N bits transferred from the interface 13-1), in the second write operation. This will be explained later.
The write operation in each block BK_k is executed in two cycles in, for example, SOT-MRAM but, if a nonvolatile memory capable of executing the operation in one cycle or the other cycles exists, the embodiments can also be implemented by using it.
An example of latency and energy of the write operation at the N-bit access will be explained. In this example, the nonvolatile RAM 13 is SOT-MRAM shown in
The latency of the write operation at the N-bit access is twrite×2. However, twrite is the latency in one cycle of the write operation.
In addition, the energy generated in the write operation at the N-bit access includes EWL, Ecol, EBL×N, and ESOT×2. However, EWL represents energy for activating the row (word line), Ecol represents energy for activating the column (column select line), EBL represents energy required for the voltage assist in SOT-MRAM, and ESOT represents energy required to generate a write current in SOT-MRAM.
The voltage assist and generation of the write current in SOT-MRAM will be explained later.
The important matter is that the I/O width (n×N bits) in the read operation and the I/O width (n×N bits) in the write operation are the same as each other at the N-bit access. Since both the I/O widths are the same as each other, an algorithm in the read operation and an algorithm in the write operation can be partially made common, and control of the read operation and the write operation using the controller in the nonvolatile RAM can be simplified.
In contrast, when the second command to instruct the random access is issued, the nonvolatile RAM executes the single-bit access. The I/O width at the single-bit access is, for example, n.
As shown in
In this case, n bits are transferred from the memory cell array 13-3 to the interface 13-1 via the internal bus (I/O width=n bits) in the read operation. The access efficiency in the nonvolatile RAM 13 is therefore improved in the read operation at the single-bit access.
The latency of the read operation at the single-bit access is tread. In addition, the energy generated in the read operation at the single-bit access includes EWL, Ecol, and Esensing.
As shown in
In this case, n bits are transferred from the interface 13-1 to the memory cell array 13-3 via the internal bus (I/O width=n bits) in the write operation. In addition, in each block BK_k (k is one of 1 to n) of the memory cell array 13-3, 1 bit transferred from the interface 13-1 is temporarily stored in the register. Therefore, in the write operation at the single-bit access, too, the access efficiency in the nonvolatile RAM 13 is improved, similarly to the read operation.
However, the write operation in each block BK_k is executed in, for example, two cycles (two write operations), similarly to the case of the N-bit access. This corresponds to a case where the nonvolatile RAM 13 is, for example, an SOT-MRAM.
In SOT-MRAM, for example, predetermined data (for example, 0) is written to 1 bit (one memory cell) which is an interest of write, in each block BK_k, in the first write operation. After this, 1 bit (one memory cell) which is the interest of write in each block BK_k, is held or changed as data (0 or 1) corresponding to the write data (1 bit transferred from the interface 13-1), in the second write operation.
N−1 bits other than 1 bit which is an interest of write are masked so as not to be the interest of write in both the first and second write operations. At the single-bit access, for example, 1 bit which is the interest of write and N−1 bits which is to be masked are determined based on the data stored in the register. This will be explained later.
An example of latency and energy of the write operation at the single-bit access in the embodiments will be explained. In this example, the nonvolatile RAM 13 is SOT-MRAM and the write operation is completed in two cycles.
The latency and energy of the write operation at the single-bit access are the same as the latency and energy of the write operation at the N-bit access. The latency of the write operation at the single-bit access is twrite×2. In addition, the energy generated in the write operation at the single-bit access includes EWL, Ecol, EBL×N, and ESOT×2.
The important matter is that the I/O width (n bits) in the read operation and the I/O width (n bits) in the write operation are the same as each other at the single-bit access, too. Since both the I/O widths are the same as each other, an algorithm in the read operation and an algorithm in the write operation can be partially made common, and control of the read operation and the write operation using the controller in the nonvolatile RAM can be simplified.
(SOT-MRAM)
The SOT-MRAM will be explained as a nonvolatile RAM to which the embodiments can be applied.
The SOT-MRAM 13SOT comprises an interface 13-1, an internal controller 13-2, a memory cell array 13-3 and a word line decoder/driver 17. The memory cell array 13-3 comprises n blocks (memory cores) BK_1 to BK_n. n is a natural number of 2 or larger.
A command CMD is transferred to the internal controller 13-2 via the interface 13-1. The command CMD includes, for example, a first command to instruct the sequential access and a second command to instruct the random access.
When the internal controller 13-2 receives the command CMD, the internal controller 13-2 outputs, for example, control signals WEl, to WEn, REl to REn, WE1/2, Wsel_1 to Wsel_n, Rsel_1 to Rsel_n, and SE1 to SEn, to execute the command CMD. The meaning and roles of the control signals will be explained later.
An address signal Addr is transferred to the internal controller 13-2 via the interface 13-1. The address signal Addr is divided into a row address Arow and column addresses Acol_1 to Acol_n in the interface 13-1. The row address Arow is transferred to the word line decoder/driver 17. The column addresses Acol_1 to Acol_n are transferred to n blocks BK_1 to BK_n.
DA1 to DAn are read data or write data transmitted or received in the read operation or the write operation. The I/O width (bit width) between the interface 13-1 and each of the blocks BK_k (k is one of 1 to n) is N bits at the N-bit access or 1 bit at the single-bit access as explained above.
Each of the blocks BK_k includes a sub-array Asub_k, a read/write circuit 15, and a column selector 16.
The column selector 16 selects one of j columns (j is a natural number of 2 or larger) CoL1 to CoLj and connects the selected column CoLp (p is one of 1 of j) to the read/write circuit 15. If the selected column CoLp is CoL1, for example, conductive lines LBL1 to LBL8, SBL1 and WBL1 are electrically connected to the read/write circuit 15 via the column selector 16, as conductive lines LBL1 to LBL8, SBL and WBL.
The sub-array Asub_k comprises, for example, memory cells M11 (MC1 to MC8) to M1j (MC1 to MC8), and Mi1 (MC1 to MC8) to Mij (MC1 to MC8).
An example of the sub-array Asub_k will be explained with an equivalent circuit of a sub-array Asub_1 shown in
M11 (MC1 to MC8) to M1j (MC1 to MC8), Mi1 (MC1 to MC8) to Mij (MC1 to MC8), WL1 to WLi, SWL1 to SWLi, SBL1 to SBLj, WBL1 to WBLj, LBL1 to LBL8, QW, and QS shown in
Conductive lines LSOT extend in the first direction. The cell unit Mij corresponds to the conductive line LSOT and comprises the memory cells MC1 to MC8. The number of memory cells MC1 to MC8 corresponds to N of the N-bit access. The number of memory cells MC1 to MC8 is eight in the present example but is not limited to this. For example, the number of memory cells MC1 to MC8 may be two or larger.
The memory cells MC1 to MC8 comprise storage elements MTJ1 to MTJ8 and transistors T1 to T8, respectively.
Each of the storage elements MTJ1 to MTJ8 is a magnetoresistive element. For example, each of the storage elements MTJ1 to MTJ8 comprises a first magnetic layer (storage layer) having a variable magnetization direction, a second magnetic layer (reference layer) having an invariable magnetization direction, and a nonmagnetic layer (tunnel barrier layer) between the first and second magnetic layers, and the first magnetic layer is in contact with the conductive line LSOT.
In this case, the conductive line LSOT desirably has the material and the thickness which enable the magnetization direction of the first magnetic layers of the storage elements MTJ1 to MTJ8 to be controlled by spin orbit coupling or the Rashba effect. For example, the conductive line LSOT contains tantalum (Ta), tungsten (W), platinum (Pt) and the like and has a thickness in a range of 5 to 20 mm (for example, approximately 10 nm). The conductive line LSOT may be formed in a multilayer structure of two or more layers including a layer of metals such as hafnium (Hf), magnesium (Mg), titanium (Ti) and the like in addition to a layer of the metals such as tantalum (Ta), tungsten (W), platinum (Pt) and the like. Furthermore, the conductive line LSOT may be formed in a multilayer structure of two or more layers including layers formed of single metallic elements of the above but different in crystal structure or a layer in which a single metallic element of the above is oxidized or nitrided.
Each of transistors T1 to T8 is, for example, an N-channel field effect transistor (FET). The transistors T1 to T8 are desirably so called vertical transistors which are disposed above the semiconductor substrate and in which channels (current paths) intersect the surface of the semiconductor substrate in the vertical direction.
The storage element MTJd (d is one of 1 to 8) comprises a first terminal (storage layer) and a second terminal (reference layer), and the first terminal is connected to the conductive line LSOT. The transistor Td comprises a third terminal (source/drain), a fourth terminal (source/drain), a channel (current path) between the third and fourth terminals, and a control electrode (gate) which controls occurrence of a channel, and the third terminal is connected to a second terminal.
The conductive lines WL1 to WLi extend in the first direction and are connected to the control electrodes of the transistors T1 to T8. The conductive lines LBL1 to LBL8 extend in the second direction intersecting the first direction and are connected to the fourth terminals of the transistors T1 to T8, respectively.
Each of the conductive lines LSOT has first and second end portions.
Each of the transistors QS comprises a channel (current path) connected between the first end portion of the conductive line LSOT and the conductive lines SBL1 to SBLj, and a control terminal (gate) which controls generation of the channel. Each of the transistors QW comprises a channel (current path) connected between the second end portion of the conductive line LSOT and the conductive lines SBL1 to SBLj, and a control terminal (gate) which controls generation of the channel.
The conductive lines SWL1 to SWLi extend in the first direction and are connected to the control electrodes of the transistors QS and QW. The conductive lines SBL1 to SBLj and WBL1 to WBLj extend in the second direction.
In the present embodiments, the transistor QS is connected to the first end portion of the conductive line LSOT and the transistor QW is connected to the second end portion of the conductive line LSOT, but one of them may be omitted.
According to the present embodiments, the architecture or the layout for putting SOT-MRAM to practical use is implemented. The nonvolatile MRAM which can be used in various systems can be thereby implemented.
In these figures, Mij (MC1 to MC8, MTJ1 to MTJ8, T1 to T8), WLi, SWLi, SBLj, WBLj, LBL1 to LBL8, QW, and QS correspond to M1j (MC1 to MC8, MTJ1 to MTJ8, T1 to T8), WLi, SWLi, SBLj, WBLj, LBL1 to LBL8, QW, and QS shown in
In the example shown in
The storage elements MTJ1 to MTJ8 are disposed on the conductive line LSOT and the transistors T1 to T8 are disposed on the storage elements MTJ1 to MTJ8, respectively. The transistors T1 to T8 are so called vertical transistors. The conductive lines LBL1 to LBL8, SBLj and WBLj are disposed on the transistors T1 to T8.
In the example shown in
In addition, the conductive lines LBL1 to LBL8 are disposed on the transistors T1 to T8, and the conductive lines SBLj and WBLj are disposed on the transistors QS and QW.
In the example shown in
The conductive line LSOT is disposed on the transistors T1 to T8, QS and QW. The transistors QS, QW, and T1 to T8 are so called vertical transistors.
In the examples of
In addition, each of the first magnetic layer 22 and the second magnetic layer 23 has an easy-axis of magnetization in an in-plane direction along the surface of the semiconductor substrate 21 and in the second direction intersecting the first direction in which the conductive line LSOT extends.
For example,
The easy-axis of magnetization of each of the first magnetic layer 22 and the second magnetic layer 23 is the second direction in the example shown in
The device structure shown in
A characteristic of the memory cell MC1 shown in
For example, the read current Iread flows from the conductive line LBL1 to the conductive line LSOT or from the conductive line LSOT to the conductive line LBL1 in the read operation. In contrast, the write current Iwrite flows from the right side to the left side or from the left side to the right side inside the conductive line LSOT in the write operation.
In the spin-transfer-torque (STT)-MRAM, the current path of the read current Iread used in the read operation is the same as the current path of the write current Iwrite used in the write operation. In this case, margin of the read current Iread and the write current Iwrite must be sufficiently secured in consideration of thermal stability Δ and the like to prevent occurrence of the write phenomenon in the read operation.
However, both the read current Iread and the write current Iwrite become small due to microminiaturization of a memory cell or the like, and the margin of both the currents can hardly be sufficiently secured.
According to the SOT-MRAM of the present example, since the current path of the read current Iread is different from the current path of the write current Iwrite, the margin of both the currents can be sufficiently secured in consideration of thermal stability Δ and the like even if the read current Iread and the write current Iwrite become small due to microminiaturization of a memory cell or the like.
The word line decoder/driver 17 has a function of activating or deactivating the conductive lines WL1 to WLi and SWL1 to SWLi in the read operation or the write operation.
Activation of the conductive lines WL1 to WLi indicates applying an ON potential to turn on (i.e., to urge the current paths to be generated in) the transistors T1 to T8 to the conductive lines WL1 to WLi. Activation of the conductive lines SWL1 to SWLi indicates applying an ON potential to turn on (i.e., to urge the current paths to be generated in) the transistors QS and QW to the conductive lines SWL1 to SWLi.
Deactivation of the conductive lines WL1 to WLi indicates applying an OFF potential to turn off (i.e., to urge no current paths to be generated in) the transistors T1 to T8 to the conductive lines WL1 to WLi. Deactivation of the conductive lines SWL1 to SWLi indicates applying an OFF potential to turn off (i.e., to urge no current paths to be generated in) the transistors QS and QW to the conductive lines SWL1 to SWLi.
An OR circuit 31 and AND circuits 321 to 32i are decoder circuits.
In the read operation, for example, a read enable signal RE from the internal controller 13-2 shown in
The row address signal Arow has, for example, R bits (R is a natural number of 2 or more) and has a relationship i (number of rows)=2R.
In the read operation or the write operation, an output signal of one of the AND circuits 321 to 32i becomes active (1) when the row address signal Arow is input to the word line decoder/driver 17. For example, if the row address signal Arow is 00 . . . 00 (all 0), the output signal of the AND circuit 321 becomes active. If the row address signal Arow is 11 . . . 11 (all 1), the output signal of the AND circuit 32i becomes active.
Drive circuits 331 to 33i and drive circuits 341 to 34i correspond to the AND circuits 321 to 32i, respectively.
If the output signal of the AND circuit 321 is active (1), the drive circuit 331 outputs the ON potential to the conductive line WL1 and the drive circuit 341 outputs the ON potential to the conductive line SWL1. If the output signal of the AND circuit 321 is nonactive (0), the drive circuit 331 outputs the OFF potential to the conductive line WL1 and the drive circuit 341 outputs the OFF potential to the conductive line SWL1.
Similarly to this, if the output signal of the AND circuit 32i is active (1), the drive circuit 33i outputs the ON potential to the conductive line WLi and the drive circuit 34i outputs the ON potential to the conductive line SWLi. If the output signal of the AND circuit 32i is nonactive (0), the drive circuit 33i outputs the OFF potential to the conductive line WLi and the drive circuit 34i outputs the OFF potential to the conductive line SWLi.
In the read operation or the write operation, the read/write circuit 15 selects one of the multi-bit access and the single-bit access, based on an instruction from the internal controller 13-2 shown in
The read/write circuit 15 comprises a read circuit and a write circuit.
The write circuit comprises ROMs 35 and 37, selectors (multiplexers) 36 and 39, write drivers/sinkers D/S_A and D/S_B, a transfer gate TG, a data register 38, a mask register 40, AND circuits 411 to 418, and voltage assist drivers 421 to 428.
The write drivers/sinkers D/S_A and D/S_B have a function of urging one of a first write current and a second write current in mutually opposite directions to be generated in, for example, the conductive line LSOT shown in
The first write current is a current for, for example, writing 0 to the storage elements MTJ1 to MTJ8 shown in
The second write current is a current for, for example, writing 1 to the storage elements MTJ1 to MTJ8 shown in
The voltage assist drivers 421 to 428 have a function of permitting/inhibiting the 0/1-write operation using the first and second write currents.
For example, when the voltage assist drivers 421 to 428 permit the 0/1-write operation, the voltage assist drivers 421 to 428 selectively apply an assist potential Vdd_W2 for facilitating the 0/1-write operation to, for example, the conductive lines LBL1 to LBL8 shown in
When the voltage assist drivers 421 to 428 permit the 0/1-write operation as shown in
When the voltage assist drivers 421 to 428 inhibit the 0/1-write operation, the voltage assist drivers 421 to 428 selectively apply an inhibit potential Vinhibit_W for urging the 0/1-write operation to be hardly executed to, for example, the conductive lines LBL1 to LBL8 shown in
When the voltage assist drivers 421 to 428 inhibit the 0/1-write operation, the voltage assist drivers 421 to 428 may set the conductive lines LBL1 to LBL8 to be in a floating state instead of applying the inhibit potential Vinhibit_W to the conductive lines LBL1 to LBL8.
The read circuit comprises shift registers 43 and 46, read drivers 441 to 448 and a sense circuit 45.
The read drivers 441 to 448 have a function of selectively applying, for example, a select potential Vdd_r for urging the read current to be generated to the conductive lines LBL1 to LBL8 shown in
The read drivers 441 to 448 may apply a nonselect potential Vinhibit_r which does not urge the read current to be generated, to remaining seven conductive lines other than the conductive line LBLd, of the conductive lines LBL1 to LBL8 or may set seven conductive lines to be in a floating state instead.
One sense circuit 45 is provided in, for example, one read/write circuit 15. In other words, only one sense circuit 45 is provided in one block (memory core) BK_k.
The sense circuit 45 comprises, for example, a sense amplifier SAn, a clamp transistor (for example, N-channel FET) Qclamp, an equalizing transistor (for example, N-channel FET) Qequ, and a reset transistor (for example, N-channel FET) Qrst as shown in
When the control signal REn from the internal controller 13-2 shown in
The sense amplifier SAn is a current sense type of comparing a cell current (read current) Imc flowing from the memory cell which is to be read to the conductive line SBL with a reference current Irc flowing to the reference cell, in the present example, but is not limited to this. The sense amplifier SAn may adopt, for example, a sense amplifier circuit of a voltage sense type or a self-reference type.
In addition, when the control l signal φeau is active (high level), the equalizing transistor Qequ is turned on and, for example, potentials of two input/output nodes Nmc and Nrc of the sense amplifier SAn are equalized. In addition, when the control signal φrst is active (high level), the reset transistor Qrst is turned on.
Next, an example of the read operation and an example of the write operation using the word line decoder/driver 17 shown in
*Write Operation
[Multi-Bit Access]
When the internal controller 13-2 shown in
The first write operation is an operation of writing the same data (for example, 0) at multi-bits (for example, 8 bits) which are the interests of write.
First, the write enable signal WE becomes 1 and the output signal of the OR circuit 31 becomes 1 in the word line decoder/driver 17 shown in
Next, the internal controller 13-2 shown in
In this case, the selector 36 selects and outputs 0 from the ROM 35 as the ROM data, in the read/write circuit 15 shown in
In addition, in the write operation, the transfer gate TG is on since the control signal WEn becomes active (high level).
Therefore, the write pulse signal is applied to the conductive line WBL via the transfer gate TG and the ground potential Vss is applied to the conductive line SBL via the transfer gate TG. At this time, if the column selected by the column selector 16 shown in
In addition, the selector 39 selects and outputs all 1 (11111111) from the ROM 37 as the ROM data, in the read/write circuit 15 shown in
All the AND circuits 411 to 418 therefore output 1 as the output signals. At this time, all the high-voltage assist drivers 421 to 428 output, for example, the assist potential Vdd_W2 to the conductive lines LBL1 to LBL8.
In other words, for example, the write current (first write current) Iwrite flows from the conductive line WBLj to the conductive line SBLj in a state in which the assist potential Vdd_W2 is applied to all the conductive lines LBL1 to LBL8, as shown in
As a result, the same data is written at all the multi-bits (for example, 8 bits) that are the interests of write, in the first write operation. However, it is assumed that 0 is written, i.e., all the storage elements MTJ1 to MTJ8 become in a parallel state in the first write operation.
In addition, the assist potentials applied to the respective conductive lines LBL1 to LBL8 may be mutually different potentials Vdd_W2 to Vdd_W9 by preparing a plurality of (for example, eight) power lines as shown in
The second write operation is an operation of urging the same data (for example, 0) written at multi-bits (for example, 8 bits) which are the interests of write, to be held (for example, if the write data is 0) or to be changed from 0 to 1 (for example, if the write data is 1) in accordance with the write data.
First, the conductive lines WLi and SWLi are held in the activated state in the word line decoder/driver 17 shown in
Next, the internal controller 13-2 shown in
In this case, the selector 36 selects and outputs 1 from the ROM 35 as the ROM data, in the read/write circuit 15 shown in
The drive potential of the write pulse signal output from the write driver/sinker D/S_A circuit in the first write operation and the drive potential of the write pulse signal output from the write driver/sinker D/S_B in the second write operation may be different drive potentials. In addition, the ground potential of the write pulse signal output from the write driver/sinker D/S_B circuit in the first write operation and the ground potential of the write pulse signal output from the write driver/sinker D/S_B in the second write operation may be different ground potentials.
The write pulse signal is applied to the conductive line SBL via the transfer gate TG and the ground potential Vss is applied to the conductive line WBL via the transfer gate TG. At this time, if the column selected by the column selector 16 shown in
In addition, the selector 39 selects and outputs the write data (for example, 01011100) stored in the data register 38, in the read/write circuit 15 shown in
The AND circuits 411 to 418 therefore output the output signal (for example, 01011100) corresponding to the write data. At this time, for example, each of the voltage assist drivers 421 to 428 outputs the assist potential Vdd_W2 when the write data is 1 or outputs the inhibit potential Vinhibit_W when the write data is 0.
In other words, for example, if the write data is 01011100, the write current (second write current) Iwrite flows from the conductive line SBLj to the conductive line WBLj in a state in which the inhibit potential Vinhibit_W is applied to the conductive lines LBL1, LBL3, LBL7 and LBL8 and the assist potential Vdd_W2 is applied to the conductive lines LBL2, LBL4, LBL5 LBL6, as shown in
As a result, 0 is held, i.e., 0 is written as the data of the storage elements MTJ1, MTJ3, MTJ7 and MTJ8, of the multi-bits (for example, 8 bits) which are the interests of write, in the second write operation. In addition, 0 is changed to 1, i.e., 1 is written as the data of the storage elements MTJ2, MTJ4, MTJ5 and MTJ6, of the multi-bits (for example, 8 bits) which are the interests of write.
In addition, the assist potentials applied to the conductive lines LBL2, LBL4, LBL5 and LBL6 may be Vdd_W3, Vdd_W5, Vdd_W6 and Vdd_W7, respectively, as shown in
However, it is assumed that 1 is selectively written to the storage elements MTJ1 to MTJ8, i.e., the state of the storage elements MTJ1 to MTJ8 is selectively changed from the parallel state to the antiparallel state, in the second write operation.
[Single-Bit Access]
When the internal controller 13-2 shown in
The first write operation is an operation of writing predetermined data (for example, 0) at the single bit which is the interest of write.
First, the output signal of the OR circuit 31 becomes 1 in the word line decoder/driver 17 shown in
Next, the internal controller 13-2 shown in
In this case, the selector 36 selects and outputs 0 from the ROM 35 as the ROM data, in the read/write circuit 15 shown in
The write pulse signal is applied to the conductive line WBL via the transfer gate TG and the ground potential Vss is applied to the conductive line SBL via the transfer gate TG. At this time, if the column selected by the column selector 16 shown in
In addition, the selector 39 selects and outputs all 1 (11111111) from the ROM 37 as the ROM data, in the read/write circuit 15 shown in
For example, when the storage element MTJ4 is an interest of write, 1 bit corresponding to the conductive line LBL4 connected to the storage element MTJ4, of 8 bits stored in the mask register 40, is set at 1. In this case, 8 bits stored in the mask register 40 becomes, for example, 00010000.
Therefore, the AND circuit 414, of the AND circuits 411 to 418, outputs 1 as the output signal and the remaining AND circuits 411 to 413 and 415 to 418 output 0 as the output signals. At this time, the voltage assist driver 424, of the high-voltage assist drivers 421 to 428 outputs the assist potential Vdd_W2 to the conductive line LBL4, and the remaining voltage assist drivers 421 to 423 and 425 to 428 output the inhibit potential Vinhibit_W to the conductive lines LBL1 to LBL3 and LBL5 to LBL8.
In other words, for example, the write current (first write current) Iwrite flows from the conductive line WBLj to the conductive line SBL1 in a state in which the assist potential Vdd_W2 is applied to the conductive line LBL4 and the inhibit potential Vinhibit_W is applied to the conductive lines LBL1 to LBL3 and LBL5 to LBL8, as shown in
As a result, the single bit which is the interest of write, for example, predetermined data (for example, 0) is written to the storage element MTJ4, in the first write operation.
In addition, the already written data is held in remaining seven bits that are not the interests of write, for example, the storage elements MTJ1 to MTJ3 and MTJ5 to MTJ8, by the above mask processing. In other words, the data in the storage elements MTJ1 to MTJ3 and MTJ5 to MTJ8 is not changed to 0, but the data in the storage elements MTJ1 to MTJ3 and MTJ5 to MTJ8 is protected, in the first write operation.
As shown in
The second write operation is an operation of urging the predetermined data (for example, 0) written at the single bit which is the interest of write, to be held (for example, if the write data is 0) or to be changed from 0 to 1 (for example, if the write data is 1) in accordance with the write data.
First, the conductive lines WLi and SWLi are held in the activated state in the word line decoder/driver 17 shown in
Next, the internal controller 13-2 shown in
In this case, the selector 36 selects and outputs 1 from the ROM 35 as the ROM data, in the read/write circuit 15 shown in
The drive potential of the write pulse signal output from the write driver/sinker D/S_A circuit in the first write operation and the drive potential of the write pulse signal output from the write driver/sinker D/S_B in the second write operation may be different drive potentials. In addition, the ground potential of the write pulse signal output from the write driver/sinker D/S_B circuit in the first write operation and the ground potential of the write pulse signal output from the write driver/sinker D/S_B in the second write operation may be different ground potentials.
The write pulse signal is applied to the conductive line SBL via the transfer gate TG and the ground potential Vss is applied to the conductive line WBL via the transfer gate TG. At this time, if the column selected by the column selector 16 shown in
In addition, the selector 39 selects and outputs the write data (for example, xxx1xxxx) stored in the data register 38, in the read/write circuit 15 shown in
For example, when the storage element MTJ4 is an interest of write in the first write operation, 1 bit corresponding to the conductive line LBL4 connected to the storage element MTJ4, of 8 bits stored in the mask register 40, is set at 1 in the second write operation, too. In other words, 8 bits stored in the mask register 40 becomes, for example, 00010000.
The AND circuit 414, of the AND circuits 411 to 418, therefore outputs the output signal (for example, 1) corresponding to the write data. At this time, for example, the voltage assist driver 424 outputs the assist potential Vdd_W2 when the write data is 1 or outputs the inhibit potential Vinhibit_W when the write data is 0.
In addition, the AND circuits 411 to 413 and 415 to 418, of the AND circuits 411 to 418, output 0. At this time, the voltage assist drivers 421 to 423 and 425 to 428 output, for example, the inhibit potential Vinhibit_W.
In other words, for example, if the write data is xxx1xxxx and the mask data is 00010000, the write current (second write current) Iwrite flows from the conductive line SBLj to the conductive line WBLj in a state in which the inhibit potential Vinhibit_W is applied to the conductive lines LBL1 to LBL3 and LBL5 to LBL8 and the assist potential Vdd_W2 is applied to the conductive lines LBL4, as shown in
As a result, the predetermined data (for example, 0) is changed to 1, i.e., 1 is written as the single bit which is the interest of write, for example, the data of the storage element MTJ4, in the second write operation. In contrast, when the write data is 0, the predetermined data (for example, 0) is held, i.e., 0 is written as the data of the storage elements MTJ4.
In addition, the already written data is held in remaining seven bits that are not the interests of write, for example, the storage elements MTJ1 to MTJ3 and MTJ5 to MTJ8, by the above mask processing. In other words, the data in the storage elements MTJ1 to MTJ3 and MTJ5 to MTJ8 is not changed to 1, but the data in the storage elements MTJ1 to MTJ3 and MTJ5 to MTJ8 is protected, in the second write operation, too.
As shown in
A single voltage assist driver may be provided instead of the voltage assist drivers and a destination of its output may be changed to one of the conductive lines LBL1 to LBL8 sequentially. In this case, the multi-bit access can be executed in the write type close to a single-bit access type which will be explained later.
*Read Operation
[Multi-Bit Access]
When the internal controller 13-2 shown in
First, the read enable signal RE becomes 1 and the output signal of the OR circuit 31 becomes 1 in the word line decoder/driver 17 shown in
Next, the internal controller 13-2 shown in
For example, the conductive lines LBL1 to LBL8 are selected one by one at the select potential Vdd_r and seven conductive lines other than the conductive line LBLd (d is one of 1 to 8) set at the select potential Vdd_r are set at the nonselect potential Vinhibit_r. In addition, φrst in
In this case, for example, if the conductive line LBL1 is set at the select potential Vdd_r, the read current Iread flows from the conductive line LBL1 to the conductive line LSOT via the storage element MTJ1, as shown in
Similarly to this, the data of the storage elements MTJ2 to MTJ8 is sequentially stored in the shift register 46 via the sense circuit 45 shown in
As a result, the multi-bits (for example, 8 bits) that are the interests of sequential access are stored in the shift register 46 as the read data (for example, 01011100), by eight read operations. The multi-bits are wholly transferred to the interface 13-2 shown in
The select potentials sequentially applied to the conductive lines LBL1 to LBL8 can be different potentials by preparing a plurality of (for example, eight) power lines. In this case, the influence that the parasitic resistance differs in accordance with the location of the selected storage element on the conductive line LSOT can be canceled.
If the efficiency of the voltage effect of the voltage assist is adequately high, the floating potential can also be used as the nonselect potential. In this case, a plurality of read drivers do not need to be mounted, and the select potential Vdd_r can be output to the predetermined conductive line and the read operation can be executed by changing one of the conductive lines LBL1 to LBL8 sequentially as the destination of the output of the single read driver.
[Single-Bit Access]
When the internal controller 13-2 shown in
First, the read enable signal RE becomes 1 and the output signal of the OR circuit 31 becomes 1 in the word line decoder/driver 17 shown in
Next, the internal controller 13-2 shown in
In this case, the read driver 444, of the read drivers 441 to 448, outputs the select potential Vdd_r and remaining seven read drivers 441 to 443 and 445 to 448 output the nonselect potential Vinhibit r. In addition, φrst in
Therefore, for example, the read current Iread flows from the conductive line LBL4 to the conductive line LSOT via the storage element MTJ4, as shown in
The valid data (read data) stored in the shift register 46 is transferred to the interface 13-1 shown in
The select potentials sequentially applied to the conductive lines LBL1 to LBL8 may be different potentials by preparing a plurality of (for example, eight) power lines. In this case, the influence that the parasitic resistance differs in accordance with the location of the selected storage element on the conductive line LSOT can be canceled.
If the efficiency of the voltage effect of the voltage assist is adequately high, the floating potential can also be used as the nonselect potential. In this case, a plurality of read drivers do not need to be mounted, and the select potential Vdd_r can be output to the predetermined conductive line and the read operation can be executed by changing one of the conductive lines LBL1 to LBL8 sequentially as the destination of the output of the single read driver.
(Layout)
The same elements as those shown in, for example,
The SOT-MRAM shown in
In addition, the SOT-MRAM shown in
In this case, the write drivers/sinkers D/S_A and D/S_B are disposed in the read/write circuit 15 in each block (memory core) BK_k (k is one of 1 to n). The write drivers/sinkers D/S_A and D/S_B are shared by the columns CoL1 to CoLj.
In addition, the power lines PSL for supplying, for example, the drive potential Vdd_W1 and the ground potential Vss to the write drivers/sinkers D/S_A and D/S_B are disposed above the read/write circuit 15 and extend in the first direction.
The SOT-MRAM shown in
However, the write drivers/sinkers D/S_A and D/S_B are provided for each column CoLp (p is one of 1 to j) in the block BK_k (k is one of 1 to n). In this case, the write drivers/sinkers D/S_A and D/S_B are laid out between sub-arrays Asub_1 to Asub_n and the column selector 16.
In addition, the power lines PSL for supplying, for example, the drive potential Vdd_W1and the ground potential Vss to the write drivers/sinkers D/S_A and D/S_B are disposed above the write drivers/sinkers D/S_A and D/S_B and extend in the first direction.
The SOT-MRAM shown in
However, the example shown in
In addition, the power lines PSL for supplying, for example, the drive potential Vdd_W1 and the ground potential Vss to the write drivers/sinkers D/S_A are disposed above the write drivers/sinkers D/S_A and extend in the first direction. The power lines PSL for supplying, for example, the drive potential Vdd_W1 and the ground potential Vss to the write drivers/sinkers D/S_B are disposed above the write drivers/sinkers D/S_B and extend in the first direction.
The SOT-MRAM shown in
However, the example shown in
In addition, the D/S_A sinkers and the D/S_B sinkers are laid out at one of ends (i.e., the end portion on the side where the column selectors 16 do not exist) of the sub-arrays Asub_1 to Asub_n, and the D/S_A drivers and the D/S_B drivers are laid out at the other end (i.e., the end portion on the side where the column selectors 16 exist) of the sub-arrays Asub_1 to Asub_n.
The power lines PSL for supplying, for example, the ground potential Vss to the D/S_A sinkers and the D/S_B sinkers are disposed above the D/S_A sinkers and the D/S_B sinkers and extend in the first direction. The power lines PSL for supplying, for example, the drive potential Vdd_W1 to the D/S_A drivers and the D/S_B drivers are disposed above the D/S_A drivers and the D/S_B drivers and extend in the first direction.
The SOT-MRAM shown in
However, the SOT-MRAM shown in
In this case, the D/S_A sinkers and the D/S_B sinkers are laid out at one of ends (i.e., the end portion in the first direction) of the sub-arrays Asub_1 to Asub_n, and the D/S_A drivers and the D/S_B drivers are laid out at the other end (i.e., the end portion in the first direction) of the sub-arrays Asub_1 to Asub_n.
As shown in this figure, for example, the D/S_A sinkers and the D/S_B sinkers are laid out at one of ends (i.e., the left end portion) of the sub-arrays Asub_1 to Asub_n, and the D/S_A drivers and the D/S_B drivers are laid out at the other end (i.e., the right end portion) of the sub-arrays Asub_1 to Asub_n, in the odd-numbered block BK_k (k is 1, 3, 5, . . . )
The D/S_A sinkers and the D/S_B sinkers are laid out at one of ends (i.e., the right end portion) of the sub-arrays Asub_1 to Asub_n, and the D/S_A drivers and the D/S_B drivers are laid out at the other end (i.e., the left end portion) of the sub-arrays Asub_1 to Asub_n, in the even-numbered block BK_k (k is 2, 4, 6, . . . )
The power lines PSL for supplying, for example, the ground potential Vss to the D/S_A sinkers and the D/S_B sinkers are disposed above the D/S_A sinkers and the D/S_B sinkers and extend in the second direction. The power lines PSL for supplying, for example, the drive potential Vdd_W1 to the D/S_A drivers and the D/S_B drivers are disposed above the D/S_A drivers and the D/S_B drivers and extend in the second direction.
The D/S_A driver comprises, for example, a P-channel FET controlled by a control signal φIN, and the D/S_B driver comprises, for example, a P-channel FET controlled by a control signal bφIN. The D/S_A sinker comprises, for example, an N-channel FET controlled by a control signal φIN, and the D/S_B sinker comprises, for example, an N-channel FET controlled by a control signal bφIN.
The control signal φIN corresponds to the control signal φIN output from the selector 36 in
In the example shown in
The SOT-MRAM 13SOT comprises an interface 13-1, an internal controller 13-2, a memory cell array 13-3 and a word line decoder/driver 17. The memory cell array 13-3 comprises n blocks (memory cores) BK_1 to BK_n. n is a natural number of 2 or larger.
A command CMD is transferred to the internal controller 13-2 via the interface 13-1. The command CMD includes, for example, a first command to instruct the sequential access and a second command to instruct the random access.
For example, when the internal controller 13-2 receives the command CMD, the internal controller 13-2 outputs, for example, control signals WE, RE, WE1/2, Wsel, Rsel, RE1 to REn, and SE1 to SEn, to execute the command CMD. The meaning and roles of the control signals will be explained later.
An address signal Addr is transferred to the internal controller 13-2 via the interface 13-1. The address signal Addr is divided into a row address Arow and column addresses Acol_1 to Acol_n in the interface 13-1. The row address Arow is transferred to the word line decoder/driver 17. The column addresses Acol_1 to Acol_n are transferred to n blocks BK_1 to BK_n.
DA is read data or write data transmitted or received in the read operation or the write operation. The I/O width (bit width) between the interface 13-1 and each of the blocks BK_k (k is one of 1 to n) is N bits at the N-bit access or 1 bit at the single-bit access as explained above.
Each of the blocks BK_k includes a sub-array Asub_k, a read/write circuit 15, and a column selector 16.
The column selector 16 selects one of j columns (j is a natural number of 2 or larger) CoL1 to CoLj and connects the selected column CoLp (p is one of 1 of j) to the read/write circuit 15. For example, if the selected column CoLp is CoL1, conductive lines LBL1, SBL1 and WBL1 are electrically connected to the read/write circuit 15 via the column selector 16, as conductive lines LBL, SBL and WBL.
The sub-array Asub_k comprises, for example, memory cells M11 (MC1 to MC8) to M1j (MC1 to MC8), and Mi1 (MC1 to MC8) to Mij (MC1 to MC8).
An example of the sub-array Asub_k will be explained with an equivalent circuit of a sub-array Asub_1 shown in
M11 (MC1 to MC8) to M1j (MC1 to MC8), Mi1 (MC1 to MC8) to Mij (MC1 to MC8), WL11 to WL18, WLi1 to WLi8, SWL1 to SWLi, SBL1 to SBLj, WBLj to WBLj, LBL1 to LBL8, QW, and QS shown in
Conductive lines LSOT extend in the first direction. The cell unit Mij corresponds to the conductive line LSOT and comprises the memory cells MC1 to MC8. The number of memory cells MC1 to MC8 corresponds to N of the N-bit access. The number of memory cells MC1 to MC8 is eight in the present example but is not limited to this. For example, the number of memory cells MC1 to MC8 may be two or larger.
The memory cells MC1 to MC8 comprise storage elements MTJ1 to MTJ8 and transistors T1 to T8, respectively.
Each of the storage elements MTJ1 to MTJ8 is a magnetoresistive element. For example, each of the storage elements MTJ1 to MTJ8 comprises a first magnetic layer (storage layer) having a variable magnetization direction, a second magnetic layer (reference layer) having an invariable magnetization direction, and a nonmagnetic layer (tunnel barrier layer) between the first and second magnetic layers, and the first magnetic layer is in contact with the conductive line LSOT.
In this case, the conductive line LSOT desirably has the material and the thickness which enable the magnetization direction of the first magnetic layers of the storage elements MTJ1 to MTJ8 to be controlled by spin orbit coupling or the Rashba effect. For example, the conductive line LSOT contains tantalum (Ta), tungsten (W), platinum (Pt) and the like and has a thickness in a range of 5 to 20 mm (for example, approximately 10 nm). The conductive line LSOT may be formed in a multilayer structure of two or more layers including a layer of metals such as hafnium (Hf), magnesium (Mg), titanium (Ti) and the like in addition to a layer of the metals such as tantalum (Ta), tungsten (W), platinum (Pt) and the like. Furthermore, the conductive line LSOT may be formed in a multilayer structure of two or more layers including layers formed of single metallic elements of the above but different in crystal structure or a layer in which a single metallic element of the above is oxidized or nitrided.
Each of transistors T1 to T8 is, for example, an N-channel FET. The transistors T1 to T8 are desirably so called vertical transistors which are disposed above the semiconductor substrate and in which channels (current paths) intersect the surface of the semiconductor substrate in the vertical direction.
The storage element MTJd (d is one of 1 to 8) comprises a first terminal (storage layer) and a second terminal (reference layer), and the first terminal is connected to the conductive line LSOT. The transistor Td comprises a third terminal (source/drain), a fourth terminal (source/drain), a channel (current path) between the third and fourth terminals, and a control electrode (gate) which controls occurrence of a channel, and the third terminal is connected to a second terminal.
The conductive lines WL11 to WL18 and WLi1 to WLi8 extend in the second direction intersecting the first direction and are connected to the control electrodes of the transistors T1 to T8. The conductive lines LBL1 to LBLj extend in the first direction and are connected to the fourth terminals of the transistors T1 to T8, respectively.
Each of the conductive lines LSOT has first and second end portions.
Each of the transistors QS comprises a channel (current path) connected between the first end portion of the conductive line LSOT and the conductive lines SBL1 to SBLj, and a control terminal (gate) which controls generation of the channel. Each of the transistors QW comprises a channel (current path) connected between the second end portion of the conductive line LSOT and the conductive lines SBL1 to SBLj, and a control terminal (gate) which controls generation of the channel.
The conductive lines SWL1 to SWLi extend in the second direction and are connected to the control electrodes of the transistors QS and QW. The conductive lines SBL1 to SBLj and WBL1 to WBLj extend in the first direction.
In the present embodiments, the transistor QS is connected to the first end portion of the conductive line LSOT and the transistor QW is connected to the second end portion of the conductive line LSOT, but one of them may be omitted.
In addition, the transistors T1 to T8 can be replaced with diodes D1 to D8 as shown in
According to the present embodiments, the architecture or the layout for putting SOT-MRAM to practical use is implemented. The nonvolatile MRAM which can be used in various systems can be thereby implemented.
In these figures, Mij (MC1 to MC8, MTJ1 to MTJ8, T1 to T8), WLi1 to WLi8, SWLi, SBLj, LBLj, QW, and QS correspond to Mij (MC1 to MC8, MTJ1 to MTJ8, T1 to T8), WLi1 to WLi8, SWLi, SBLj, WBLj, LBLj, QW, and QS shown in
In the example shown in
The storage elements MTJ1 to MTJ8 are disposed on the conductive line LSOT and the transistors T1 to T8 are disposed on the storage elements MTJ1 to MTJ8, respectively. The transistors T1 to T8 are so called vertical transistors. In addition, the conductive lines LBLj, SBLj and WBLj are disposed on the transistors T1 to T8.
In the example shown in
In addition, the conductive line LBLj is disposed on the transistors T1 to T8, and the conductive lines SBLj and WBLj are disposed on the transistors QS and QW.
In the example shown in
The conductive line LSOT is disposed on the transistors T1 to T8, QS and QW. The transistors QS, QW, and T1 to T8 are so called vertical transistors.
In the examples of
In addition, each of the first magnetic layer 22 and the second magnetic layer 23 has an easy-axis of magnetization in an in-plane direction along the surface of the semiconductor substrate 21 and in the second direction intersecting the first direction in which the conductive line LSOT extends.
The structure explained with reference to
The characteristic of the memory cell shown in
The word line decoder/driver 17 has a function of activating or deactivating the conductive lines WL11 to WL18, WLi1 to WLi8 and SWL1 to SWLi in the read operation or the write operation.
An OR circuit 31 and AND circuits 321 to 32i, 3211 to 3218, 32i1 to 32i8, 32′11 to 32′18, and 32′i1 to 32′i8 are decoder circuits.
In the read operation, for example, a read enable signal RE from the internal controller 13-2 shown in
The row address signal Arow has, for example, R bits (R is a natural number of 2 or more) and has a relationship i (number of rows)=2R.
In the read operation or the write operation, all bits (R bits) of one of the row address signals Arow1 to Arowi become 1 when the row address signal Arow is input to the word line decoder/driver 17.
For example, if the row address signal Arow is 00 . . . 00 (all 0), the output signal of the AND circuit 321 becomes 1 since all the bits of the row address signal Arow1 become 1. In this case, the drive circuit 341 sets the conductive line SWL1 to be active. In addition, if the row address signal Arow is 11 . . . 11 (all 1), the output signal of the AND circuit 32i becomes 1 since all the bits of the row address signal Arowi become 1. In this case, the drive circuit 34i sets the conductive line SWLi to be active.
A ROM 37, a data register 38, a selector (multiplexer) 39 and a mask register 40 are elements used in the write operation. The ROM 37, the data register 38, the selector (multiplexer) 39 and the mask register 40 control setting the conductive lines WL11 to WL18 and WLi1 to WLi8 to be active/nonactive, in the row selected by the row address signal Arow. This will be explained later.
A shift register 43 is an element used in the read operation. The shift register 43 controls setting the conductive lines WL11 to WL18 and WLi1 to WLi8 to be active/nonactive, in the row selected by the row address signal Arow. This will also be explained later.
Drive circuits 3311 to 3318, 33i1 to 33i8, 33′11 to 33′18, and 33′i1 to 33′i8 correspond to AND circuits 3211 to 3218, 32i1 to 32i8, 32′11 to 32′18, and 32′i1 to 32′i8, respectively.
When an output signal of the AND circuit 321 is active (1), output signals of the AND circuits 3211 to 3218 and 32′11 to 32′18 can be active. In addition, when an output signal of the AND circuit 32i is active (1), output signals of the AND circuits 32i1 to 32i8 and 32′i1 to 32′i8 can be active.
In the read operation or the write operation, the read/write circuit 15 selects one of the multi-bit access and the single-bit access and executes the read operation or the write operation, based on an instruction from the internal controller 13-2 shown in
The read/write circuit 15 comprises a read circuit and a write circuit.
The write circuit comprises a ROM 35, a selector (multiplexer) 36, write drivers/sinkers D/SA and D/S_B, a transfer gate TG, and a voltage assist driver 42.
The write drivers/sinkers D/S_A and D/S_B have a function of urging one of a first write current and a second write current in mutually opposite directions to be generated in, for example, the conductive line LSOT shown in
The first write current is a current for, for example, writing 0 to the storage elements MTJ1 to MTJ8 shown in
The second write current is a current for, for example, writing 1 to the storage elements MTJ1 to MTJ8 shown in
The voltage assist driver 42 has a function of applying a voltage for facilitating the write operation to the storage elements MTJ1 to MTJ8 in the 0/1-write operation using the first and second write currents.
For example, when the voltage assist driver 42 applies an assist potential Vdd_W2 to, for example, LBLj shown in
The read circuit comprises a sense circuit 45 and a shift register 46.
The read driver 44 has a function of applying a select potential Vdd_r for urging the read current to be generated to, for example, the conductive line LBLj shown in
For example, when the read driver 44 applies the select potential Vdd_r to, for example, LBLj shown in
One sense circuit 45 is disposed in, for example, one read/write circuit 15. In other words, only one sense circuit 45 is disposed in one block (memory core) BK_k.
The sense circuit 45 comprises, for example, a sense amplifier SAn, a clamp transistor (for example, N-channel FET) Qclamp, an equalizing transistor (for example, N-channel FET) Qequ, and a reset transistor (for example, N-channel FET) Qrst as shown in
The sense circuit 45 is not explained here since the circuit has been explained in the first example of the SOT MRAM.
Next, an example of the read operation and an example of the write operation using the word line decoder/driver 17 shown in
*Write Operation
[Multi-Bit Access]
When the internal controller 13-2 shown in
The first write operation is an operation of writing the same data (for example, 0) at multi-bits (for example, 8 bits) which are the interests of write.
First, the write enable signal WE becomes 1 and the output signal of the OR circuit 31 becomes 1 in the word line decoder/driver 17 shown in
In addition, the internal controller 13-2 shown in
In other words, the selector 39 selects the ROM 37 and outputs all 1 (11111111) as the ROM data. In addition, the internal controller 13-2 shown in
Therefore, when an output signal of the AND circuit 32i is 1, all the AND circuits 32i1 to 32i8 output 1 as the output signals. In this case, the drivers 33i1 to 33i8 activate the conductive lines WLi1 to WLi8.
In contrast, the selector 36 selects and outputs 0 from the ROM 35 as the ROM data, in the read/write circuit 15 shown in
In addition, in the write operation, the transfer gate TG is on since the control signal WEn becomes active (high level).
Therefore, the write pulse signal is applied to the conductive line WBL via the transfer gate TG and the ground potential V55 is applied to the conductive line SBL via the transfer gate TG. At this time, if the column selected by the column selector 16 shown in
In addition, in the read/write circuit 15 shown in
In the first write operation, all the transistors T1 to T8 are on since all the conductive lines WLi1 to WLi8 are activated as shown in, for example,
As a result, the same data is written at all the multi-bits (for example, 8 bits) that are the interests of write, in the first write operation. However, it is assumed that 0 is written, i.e., all the storage elements MTJ1 to MTJ8 become in a parallel state in the first write operation.
The second write operation is an operation of urging the same data (for example, 0) written at multi-bits (for example, 8 bits) which are the interests of write, to be held (for example, if the write data is 0) or to be changed from 0 to 1 (for example, if the write data is 1) in accordance with the write data.
First, the internal controller 13-2 shown in
In this case, the selector 39 selects the data register 38 and outputs the write data (for example, 01011100) stored in the data register 38, in the word line decoder/driver 17 shown in
The AND circuits 32i1 to 32i8 therefore output the output signal (for example, 01011100) corresponding to the write data. At this time, for example, the drivers 33i1 to 3318 activate the corresponding conductive lines WLi1 to WLi8 when the write data is 1 or deactivate the corresponding conductive lines WLi1 to WLi8 when the write data is 0.
In addition, the selector 36 selects and outputs 1 from the ROM 35 as the ROM data, in the read/write circuit 15 shown in
The write pulse signal is applied to the conductive line SBL via the transfer gate TG and the ground potential Vss is applied to the conductive line WBL via the transfer gate TG. In addition, the driver 42 applies the assist potential Vdd_W2 to the conductive line LBL since the control signal φWE becomes active (1).
At this time, if the column selected by the column selector 16 shown in
In other words, for example, if the write data is 01011100, the transistors T1, T3, T7, and T8 become OFF and the transistors T2, T4, T5, and T6 become ON, as shown in
As a result, 0 is held, i.e., 0 is written as the data of the storage elements MTJ1, MTJ3, MTJ7 and MTJ8, of the multi-bits (for example, 8 bits) which are the interests of write, in the second write operation. In addition, 0 is changed to 1, i.e., 1 is written as the data of the storage elements MTJ2, MTJ4, MTJ5 and MTJ6, of the multi-bits (for example, 8 bits) which are the interests of write.
However, it is assumed that 1 is selectively written to the storage elements MTJ1 to MTJ8, i.e., the state of the storage elements MTJ1 to MTJ8 is selectively changed from the parallel state to the antiparallel state, in the second write operation.
[Single-Bit Access]
When the internal controller 13-2 shown in
The first write operation is an operation of writing predetermined data (for example, 0) at the single bit which is the interest of write.
First, the output signal of the OR circuit 31 becomes 1 in the word line decoder/driver 17 shown in
Next, the internal controller 13-2 shown in
In this case, the selector 39 selects the ROM 37 and outputs all 1 (11111111) as the ROM data, in the word line decoder/driver 17 shown in
For example, when the storage element MTJ4 is an interest of write, 1 bit corresponding to the storage element MTJ4, of 8 bits stored in the mask register 40, is set at 1. In this case, 8 bits stored in the mask register 40 becomes, for example, 00010000.
Therefore, the AND circuit 32i4, of the AND circuits 32i1 to 32i8, outputs 1 as the output signal and the remaining AND circuits 32i1 to 32i3 and 32i5 to 32i8 output 0 as the output signals. At this time, the driver 33i4, of the drivers 33i1 to 33i8, activate the conductive line WLi4 and the remaining drivers 3311 to 33i3 and 33i5 to 33i8 deactivate the conductive lines WLi1 to WLi3 and WLi5 to WLi8.
In addition, the selector 36 selects and outputs 0 from the ROM 35 as the ROM data, in the read/write circuit 15 shown in
The write pulse signal is applied to the conductive line WBL via the transfer gate TG and the ground potential Vss is applied to the conductive line SBL via the transfer gate TG. In addition, the driver 42 applies the assist potential Vdd_W2 to the conductive line LBL since the control signal φWE becomes active (1).
At this time, if the column selected by the column selector 16 shown in
In other words, for example, the write current (first write current) Iwrite flows from the conductive line WBLj to the conductive line SBLj in a state in which the assist potential Vdd_W2 is applied to the storage element MTJ4 and the assist potential Vdd_W2 is not applied to the storage elements MTJ1 to MTJ3 and MTJ5 to MTJ8, as shown in
As a result, the single bit which is the interest of write, for example, predetermined data (for example, 0) is written to the storage element MTJ4, in the first write operation.
In addition, the already written data is held in remaining seven bits that are not the interests of write, for example, the storage elements MTJ1 to MTJ3 and MTJ5 to MTJ8, by the above mask processing. In other words, the data in the storage elements MTJ1 to MTJ3 and MTJ5 to MTJ8 is not changed to 0, but the data in the storage elements MTJ1 to MTJ3 and MTJ5 to MTJ8 is protected, in the first write operation.
The second write operation is an operation of urging the predetermined data (for example, 0) written at the single bit which is the interest of write, to be held (for example, if the write data is 0) or to be changed from 0 to 1 (for example, if the write data is 1) in accordance with the write data.
First, the conductive lines WLi4 and SWLi are held in the activated state in the word line decoder/driver 17 shown in
Next, the internal controller 13-2 shown in
In this case, the selector 36 selects and outputs 1 from the ROM 35 as the ROM data, in the read/write circuit 15 shown in
The write pulse signal is applied to the conductive line SBL via the transfer gate TG and the ground potential Vss is applied to the conductive line WBL via the transfer gate TG. In addition, the driver 42 applies the assist potential Vdd_W2 to the conductive line LBL since the control signal φWE becomes active (1).
At this time, if the column selected by the column selector 16 shown in
In addition, the selector 39 outputs the write data (for example, xxx1xxxx) stored in the data register 38, in the word line decoder/driver 17 shown in
For example, when the storage element MTJ4 is an interest of write in the first write operation, 1 bit corresponding to the storage element MTJ4, of 8 bits stored in the mask register 40, is set at 1 in the second write operation, too. In other words, 8 bits stored in the mask register 40 becomes, for example, 00010000.
The AND circuit 32i4, of the AND circuits 32i1 to 32i8, therefore outputs the output signal (for example, 1) corresponding to the write data. At this time, for example, the driver 33i4 activates the conductive line WLi4 when the write data is 1 or deactivates the conductive line WLi4 when the write data is 0.
In addition, the AND circuits 32i1 to 32i3 and 32i5 to 32i8, of the AND circuits 32i1 to 32i8, output, for example, 0. At this time, the drivers 33i1 to 3313 and 3315 to 33i8 deactivate, for example, the conductive lines WLi1 to WLi3 and WLi5 to WLi8.
In other words, for example, when the write data is xxx1xxxx and the mask data is 00010000, the write current (second write current) Iwrite flows from the conductive line SBLj to the conductive line WBLj in a state in which the assist potential Vdd_W2 is applied to the storage element MTJ4 and the assist potential Vdd_W2 is not applied to the storage elements MTJ1 to MTJ3 and MTJ5 to MTJ8, as shown in
As a result, the predetermined data (for example, 0) is changed to 1, i.e., 1 is written as the single bit which is the interest of write, for example, the data of the storage element MTJ4, in the second write operation. In contrast, when the write data is 0, the predetermined data (for example, 0) is held, i.e., 0 is written as the data of the storage elements MTJ4.
In addition, the already written data is held in remaining seven bits that are not the interests of write, for example, the storage elements MTJ1 to MTJ3 and MTJ5 to MTJ8, by the above mask processing. In other words, the data in the storage elements MTJ1 to MTJ3 and MTJ5 to MTJ8 is not changed to 1, but the data in the storage elements MTJ1 to MTJ3 and MTJ5 to MTJ8 is protected, in the second write operation, too.
*Read Operation
[Multi-Bit Access]
When the internal controller 13-2 shown in
First, the read enable signal RE becomes 1 and the output signal of the OR circuit 31 becomes 1 in the word line decoder/driver 17 shown in
Next, the internal controller 13-2 shown in
For example, the conductive lines WLi1 to WLi8 are activated one by one and seven conductive lines other than the activated conductive line WLid (d is one of 1 to 8) are deactivated. In addition, φrst in
In addition, in the read/write circuit 15 shown in
In this case, for example, if the transistor T1 in the memory cell MC1 is turned on, the read current Iread flows from the conductive line LBLj to the conductive line LSOT via the storage element MTJ1, as shown in
Similarly to this, the data of the storage elements MTJ2 to MTJ8 is sequentially stored in the shift register 46 via the sense circuit 45 shown in
As a result, the multi-bits (for example, 8 bits) that are the interests of sequential access are stored in the shift register 46 as the read data (for example, 01011100), by eight read operations. The multi-bits are wholly transferred to the interface 13-2 shown in
[Single-Bit Access]
When the internal controller 13-2 shown in
First, the read enable signal RE becomes 1 and the output signal of the OR circuit 31 becomes 1 in the word line decoder/driver 17 shown in
Next, the internal controller 13-2 shown in
In this case, the driver 33′i4, of the drivers 33′i1 to 33′1-8, activate the conductive line WLi4 and the remaining seven drivers 33′i1 to 33′i3 and 33′i5 to 33′i8 deactivate the conductive lines WLi1 to WLi8 and WLi5 to WLi8. In addition, φrst in
Therefore, for example, the read current Iread flows from the conductive line LBLj to the conductive line LSOT via the transistor T4 and the storage element MTJ4, as shown in
The valid data (read data) stored in the shift register 46 is transferred to the interface 13-1 shown in
This modified example is characterized by employing so called a divided word line structure in the second example, i.e., the SOT-MRAM shown in
The SOT-MRAM 13SOT comprises an interface 13-1, an internal controller 13-2, a memory cell array 13-3, a word line decoder/driver 17 and sub-decoders/drivers SD11 to SD1n and SDi1 to SDin. The memory cell array 13-3 comprises n blocks (memory cores) BK_1 to BK_n. n is a natural number of 2 or larger.
A command CMD is transferred to the internal controller 13-2 via the interface 13-1. The command CMD includes, for example, a first command to instruct the sequential access and a second command to instruct the random access.
When the internal controller 13-2 receives the command CMD, the internal controller 13-2 outputs, for example, control signals WE, RE, WE1/2, Wsel_1 to Wsel_n, Rsel_1 to Rsel_n, RE1 to REn, and SE1 to SEn, to execute the command CMD.
An address signal Addr is transferred to the internal controller 13-2 via the interface 13-1. The address signal Addr is divided into a row address Arow and column addresses Acol_1 to Acol_n in the interface 13-1. The row address Arow is transferred to the word line decoder/driver 17. The column addresses Acol_1 to Acol_n are transferred to n blocks BK_1 to BK_n.
DA1 to DAn are read data or write data transmitted or received in the read operation or the write operation. The I/O width (bit width) between the interface 13-1 and each of the blocks BK_k (k is one of 1 to n) is N bits at the N-bit access or 1 bit at the single-bit access as explained above.
Each of the blocks BK_k includes a sub-array Asub_k, a read/write circuit 15, and a column selector 16.
The column selector 16 selects one of j columns (j is a natural number of 2 or larger) CoL1 to CoLj and connects the selected column CoLp (p is one of 1 of j) to the read/write circuit 15. For example, if the selected column CoLp is CoL1, conductive lines LBL1, SBL1 and WBLj are electrically connected to the read/write circuit 15 via the column selector 16, as conductive lines LBL, SBL and WBL.
The sub-array Asub_k comprises, for example, memory cells M11 (MC1 to MC8) to M1j (MC1 to MC8), and Mi1 (MC1 to MC8) to Mij (MC1 to MC8). The sub-array Asub_k is not explained here since the sub-array is the same as the sub-array Asub_1 in the second example, for example,
The word line decoder/driver 17 has a function of activating or deactivating conductive lines SWL1 to SWLi and global conductive lines GWL1 to GWLi in the read operation or the write operation.
An OR circuit 31 and AND circuits 321 to 32i are decoder circuits.
In the read operation, for example, a read enable signal RE from the internal controller 13-2 shown in
The row address signal Arow has, for example, R bits (R is a natural number of 2 or more) and has a relationship i (number of rows)=2R.
In the read operation or the write operation, all bits (R bits) of one of the row address signals Arow1 to Arowi become 1 when the row address signal Arow is input to the word line decoder/driver 17.
For example, if the row address signal Arow is 00 . . . 00 (all 0), the output signal of the AND circuit 321 becomes 1 since all the bits of the row address signal Arow1 become 1. In this case, the drive circuit 331 sets the global conductive line GWL1 to be active and the drive circuit 341 sets the conductive line SWL1 to be active.
In addition, if the row address signal Arow is 11 . . . 11 (all 1), the output signal of the AND circuit 32i becomes 1 since all the bits of the row address signal Arowi become 1. In this case, the drive circuit 33i sets the global conductive line GWLi to be active and the drive circuit 34i sets the conductive line SWLi to be active.
The sub-decoder/driver SD11 has a function of activating or deactivating the conductive lines WL11 to WL18 and WLi1 to WLi8 in the read operation or the write operation.
A ROM 37, a data register 38, a selector (multiplexer) 39 and a mask register 40 are elements used in the write operation. The ROM 37, the data register 38, the selector (multiplexer) 39 and the mask register 40 control setting the conductive lines WL11 to WL18 and WLi1 to WLi8 to be active/nonactive, in the row selected by the row address signal Arow.
A shift register 43 is an element used in the read operation. The shift register 43 controls setting the conductive lines WL11 to WL18 and WLi1 to WLi8 to be active/nonactive, in the row selected by the row address signal Arow.
Drive circuits 3311 to 3318, 3311 to 33i8, 33′11 to 33′18, and 33′i1 to 33′i8 correspond to AND circuits 3211 to 3218, 32i1 to 32i8, 32′11 to 32′18, and 32′i1 to 32′i8, respectively.
When an output signal of the AND circuit 321 shown in
The read/write circuit 15 shown in
In addition, an example of the read operation and an example of the write operation using the word line decoder/driver 17 shown in
In the second example (shared bit line architecture), the write data cannot be written parallel to the sub-arrays Asub_1 to Asub_n. In contrast, in the third example (shared bit line architecture and divided word line structure), the write data can be written parallel for the sub-arrays Asub_1 to Asub_n.
In the first example (shared word line architecture) shown in
In the sub-arrays Asub_1 to Asub_n, however, the memory cells MC1 to MC8 which are the interests of write are limited in the same row selected by the word line decoder/driver 17.
In contrast, in the second example (shared word line architecture) shown in
It is the third example which solves the problem of the second example.
In the third example (shared bit line architecture and divided word line structure) shown in
Therefore, the write data is written to the memory cells MC1 to MC8 by, for example, controlling the electric potentials of the conductive lines WLi1 to WLi8 for each of the sub-arrays Asub_1 to Asub_n by using the sub-arrays Asub_1 to Asub_n.
In other words, the write data can be written parallel to the sub-arrays Asub_1 to Asub_n in the third example shown in
In the sub-arrays Asub_1 to Asub_n, however, the memory cells MC1 to MC8 which are the interests of write are limited in the same row selected by the word line decoder/driver 17.
(Layout)
The same elements as those shown in, for example,
The SOT-MRAM shown in
In addition, the SOT-MRAM shown in
In this case, the write drivers/sinkers D/S_A and D/S_B are disposed in the read/write circuit 15 in each block (memory core) BK_k (k is one of 1 to n). The write drivers/sinkers D/S_A and D/S_B are shared by the columns CoL1 to CoLj.
In addition, the power lines PSL for supplying, for example, the drive potential Vdd_W1 and the ground potential Vss to the write drivers/sinkers D/S_A and D/S_B are disposed above the read/write circuit 15 and extend in the second direction intersecting the first direction.
The SOT-MRAM shown in
However, the write drivers/sinkers D/S_A and D/S_B are provided for each column CoLp (p is one of 1 to j) in the block BK_k (k is one of 1 to n). In this case, the write drivers/sinkers D/S_A and D/S_B are laid out between sub-arrays Asub_1 to Asub_n and the column selector 16.
In addition, the power lines PSL for supplying, for example, the drive potential Vdd_W1 and the ground potential Vss to the write drivers/sinkers D/S_A and D/S_B are disposed above the write drivers/sinkers D/S_A and D/S_B and extend in the second direction.
The SOT-MRAM shown in
However, the example shown in
In addition, the power lines PSL for supplying, for example, the drive potential Vdd_W1 and the ground potential Vss to the write drivers/sinkers D/S_A are disposed above the write drivers/sinkers D/S_A and extend in the second direction. The power lines PSL for supplying, for example, the drive potential Vdd_W1 and the ground potential Vss to the write drivers/sinkers D/S_B are disposed above the write drivers/sinkers D/S_B and extend in the second direction.
The SOT-MRAM shown in
However, the example shown in
In addition, the D/S_A sinkers and the D/S_B sinkers are laid out at one of ends (i.e., the end portion on the side where the column selectors 16 do not exist) of the sub-arrays Asub_1 to Asub_n, and the D/S_A drivers and the D/S_B drivers are laid out at the other end (i.e., the end portion on the side where the column selectors 16 exist) of the sub-arrays Asub_1 to Asub_n.
The power line PSL for supplying, for example, the ground potential Vss to the D/S_A sinkers and the D/S_B sinkers is disposed above the D/S_A sinkers and the D/S_B sinkers and extend in the second direction. The power line PSL for supplying, for example, the drive potential Vdd_W1 to the D/S_A drivers and the D/S_B drivers is disposed above the D/S_A drivers and the D/S_B drivers and extend in the second direction.
The SOT-MRAM shown in
However, the SOT-MRAM shown in
In this case, the D/S_A sinkers and the D/S_B sinkers are laid out at one of ends (i.e., the end portion in the second direction) of the sub-arrays Asub_1 to Asub_n, and the D/S_A drivers and the D/S_B drivers are laid out at the other end (i.e., the end portion in the second direction) of the sub-arrays Asub_1 to Asub_n.
As shown in this figure, for example, the D/S_A sinkers and the D/S_B sinkers are laid out at one of ends (i.e., the left end portion) of the sub-arrays Asub_1 to Asub_n, and the D/S_A drivers and the D/S_B drivers are laid out at the other end (i.e., the right end portion) of the sub-arrays Asub_1 to Asub_n, in the odd-numbered block BK_k (k is 1, 3, 5, . . . )
The D/S_A sinkers and the D/S_B sinkers are laid out at one of ends (i.e., the right end portion) of the sub-arrays Asub_1 to Asub_n, and the D/S_A drivers and the D/S_B drivers are laid out at the other end (i.e., the left end portion) of the sub-arrays Asub_1 to Asub_n, in the even-numbered block BK_k (k is 2, 4, 6, . . . )
The power lines PSL for supplying, for example, the ground potential Vss to the D/S_A sinkers and the D/S_B sinkers are disposed above the D/S_A sinkers and the D/S_B sinkers and extend in the second direction. The power lines PSL for supplying, for example, the drive potential Vdd_W1 to the D/S_A drivers and the D/S_B drivers are disposed above the D/S_A drivers and the D/S_B drivers and extend in the first direction.
The D/S_A drivers, the D/S_B drivers, the D/S_A sinkers, and the D/S_B sinkers shown in
In the example shown in
According to the above embodiments, the nonvolatile MRAM which can be used in various systems can be thereby implemented.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
---|---|---|---|
2016-155106 | Aug 2016 | JP | national |