Nor flash memory cell with high storage density

Abstract

Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A sourceline is formed in a trench adjacent to the vertical floating gate transistor and coupled to the first source/drain region. A transmission line coupled to the second source/drain region. And, a wordline is coupled to the control gate perpendicular to the sourceline.

Description

FIELD OF THE INVENTION

[0002] The present invention relates generally to semiconductor integrated circuits and, more particularly, to NOR flash memory cells with high storage density.

BACKGROUND OF THE INVENTION

[0003] Many electronic products need various amounts of memory to store information, e.g. data. One common type of high speed, low cost memory includes dynamic random access memory (DRAM) comprised of individual DRAM cells arranged in arrays. DRAM cells include an access transistor, e.g a metal oxide semiconducting field effect transistor (MOSFET), coupled to a capacitor cell.

[0004] Another type of high speed, low cost memory includes floating gate memory cells. A conventional horizontal floating gate transistor structure includes a source region and a drain region separated by a channel region in a horizontal substrate. A floating gate is separated by a thin tunnel gate oxide. The structure is programmed by storing a charge on the floating gate. A control gate is separated from the floating gate by an intergate dielectric. A charge stored on the floating gate effects the conductivity of the cell when a read voltage potential is applied to the control gate. The state of cell can thus be determined by sensing a change in the device conductivity between the programmed and un-programmed states.

[0005] With successive generations of DRAM chips, an emphasis continues to be placed on increasing array density and maximizing chip real estate while minimizing the cost of manufacture. It is further desirable to increase array density with little or no modification of the DRAM optimized process flow.

[0006] Flash memories based on electron trapping are well known and commonly used electronic components. (See generally; B. Dipert and L. Hebert, “Flash Memory goes Mainstream,” IEEE Spectrum, No. 10, pp. 48-52, (October 1993); R. Goodwins, “New Memory Technologies on the Way,” http://zdnet.com.com/2100-1103-846950.html). Recently NAND flash memory cells have become common in applications requiring high storage density while NOR flash memory cells are used in applications requiring high access and read speeds. (See generally, C.-G. Hwang, “Semiconductor Memories for the IT Era,” Abst. IEEE Int. Solid-State Circuits Conf., San Francisco, 2002, pp. 24-27). NAND flash memories have a higher density because 16 or more devices are placed in series, this increases density at the expense of speed. (See generally; R. Shirota et al., “A 2.3 mu2 memory cell structure for 16 Mb NAND EEPROMs,” Digest of IEEE Int. Electron Device Meeting, San Francisco, 1990, pp. 103-106)

[0007] Thus, there is an ongoing need for improved DRAM technology compatible flash memory cells. It is desirable that such flash memory cells be fabricated on a DRAM chip with little or no modification of the DRAM process flow. It is further desirable that such flash cells provide increased density and high access and read speeds.

SUMMARY OF THE INVENTION

[0008] The above mentioned problems for creating DRAM technology compatible flash memory cells as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. This disclosure describes a high speed NOR type flash memory cell and arrays with high density. Two transistors occupy an area of 4F squared when viewed from above, or each memory cell consisting of one transistor has an area of 2F squared. NAND flash memories are ideally as small as 4F squared in conventional planar device technology, with practical devices having a cell area of SF squared. The vertical NOR flash memory cells described here have a higher density than conventional planar NAND cells but they would operate at speeds higher than or comparable to conventional planar NOR flash memories. The NOR flash memories described here then have both high density and high speed.

[0009] In particular, an embodiment of the present invention includes a NOR flash cell. The NOR flash memory cell includes a floating gate transistor extending outwardly from a substrate. The floating gate transistor has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A sourceline is formed buried in a trench adjacent to the vertical floating gate transistor and coupled to the first source/drain region. A transmission line coupled to the second source/drain region. And, a wordline is coupled to the control gate perpendicular to the sourceline.

[0010] These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1A is a block diagram of a metal oxide semiconductor field effect transistor (MOSFET) in a substrate according to the teachings of the prior art.

[0012] FIG. 1B illustrates the MOSFET of FIG. 1A operated in the forward direction showing some degree of device degradation due to electrons being trapped in the gate oxide near the drain region over gradual use.

[0013] FIG. 1C is a graph showing the square root of the current signal (Ids) taken at the drain region of the conventional MOSFET versus the voltage potential (VGS) established between the gate and the source region.

[0014] FIG. 2A is a diagram of a programmed MOSFET which can be used as a NOR flash cell according to the teachings of the present invention.

[0015] FIG. 2B is a diagram suitable for explaining the method by which the MOSFET of the NOR flash cell of the present invention can be programmed to achieve the embodiments of the present invention.

[0016] FIG. 2C is a graph plotting the current signal (Ids) detected at the drain region versus a voltage potential, or drain voltage, (VDS) set up between the drain region and the source region (Ids vs. VDS).

[0017] FIG. 3 illustrates a portion of a memory array according to the teachings of the present invention.

[0018] FIG. 4 illustrates an electrical equivalent circuit for the portion of the memory array shown in FIG. 3. FIGS. 5A-5E are cross sectional views of various embodiments of the invention from the same vantage point illustrated in FIG. 3.

[0019] FIGS. 6A-6B illustrates the operation of the novel NOR flash cell formed according to the teachings of the present invention.

[0020] FIG. 7 illustrates the operation of a conventional DRAM cell.

[0021] FIG. 8 illustrates a memory device according to the teachings of the present invention.

[0022] FIG. 9 is a block diagram of an electrical system, or processor-based system, utilizing write once read only memory constructed in accordance with the present invention.

DETAILED DESCRIPTION

[0023] In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.

[0024] The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0025] FIG. 1A is useful in illustrating the conventional operation of a MOSFET such as can be used in a DRAM array. FIG. 1A illustrates the normal hot electron injection and degradation of devices operated in the forward direction. As is explained below, since the electrons are trapped near the drain they are not very effective in changing the device characteristics.

[0026] FIG. 1A is a block diagram of a metal oxide semiconductor field effect transistor (MOSFET) 101 in a substrate 100. The MOSFET 101 includes a source region 102, a drain region 104, a channel region 106 in the substrate 100 between the source region 102 and the drain region 104. A gate 108 is separated from the channel region 108 by a gate oxide 110. A sourceline 112 is coupled to the source region 102. A bitline 114 is coupled to the drain region 104. A wordline 116 is coupled to the gate 108.

[0027] In conventional operation, a drain to source voltage potential (Vds) is set up between the drain region 104 and the source region 102. A voltage potential is then applied to the gate 108 via a wordline 116. Once the voltage potential applied to the gate 108 surpasses the characteristic voltage threshold (Vt) of the MOSFET a channel 106 forms in the substrate 100 between the drain region 104 and the source region 102. Formation of the channel 106 permits conduction between the drain region 104 and the source region 102, and a current signal (Ids) can be detected at the drain region 104.

[0028] In operation of the conventional MOSFET of FIG. 1A, some degree of device degradation does gradually occur for MOSFETs operated in the forward direction by electrons 117 becoming trapped in the gate oxide 110 near the drain region 104. This effect is illustrated in FIG. 1B. However, since the electrons 117 are trapped near the drain region 104 they are not very effective in changing the MOSFET characteristics.

[0029] FIG. 1C illustrates this point. FIG. 1C is a graph showing the square root of the current signal (Ids) taken at the drain region versus the voltage potential (VGS) established between the gate 108 and the source region 102. The change in the slope of the plot of {square root}{square root over (Ids)} versus VGS represents the change in the charge carrier mobility in the channel 106.

[0030] In FIG. 1C, ΔVT represents the minimal change in the MOSFET's threshold voltage resulting from electrons gradually being trapped in the gate oxide 110 near the drain region 104, under normal operation, due to device degradation. This results in a fixed trapped charge in the gate oxide 110 near the drain region 104. Slope 1 represents the charge carrier mobility in the channel 106 for FIG. 1A having no electrons trapped in the gate oxide 110. Slope 2 represents the charge mobility in the channel 106 for the conventional MOSFET of FIG. 1B having electrons 117 trapped in the gate oxide 110 near the drain region 104. As shown by a comparison of slope 1 and slope 2 in FIG. 1C, the electrons 117 trapped in the gate oxide 110 near the drain region 104 of the conventional MOSFET do not significantly change the charge mobility in the channel 106.

[0031] There are two components to the effects of stress and hot electron injection. One component includes a threshold voltage shift due to the trapped electrons and a second component includes mobility degradation due to additional scattering of carrier electrons caused by this trapped charge and additional surface states. When a conventional MOSFET degrades, or is “stressed,” over operation in the forward direction, electrons do gradually get injected and become trapped in the gate oxide near the drain. In this portion of the conventional MOSFET there is virtually no channel underneath the gate oxide. Thus the trapped charge modulates the threshold voltage and charge mobility only slightly.

[0032] The inventors have previously described programmable memory devices and functions based on the reverse stressing of MOSFET's in a conventional CMOS process and technology in order to form programmable address decode and correction. (See generally, L. Forbes, W. P. Noble and E. H. Cloud, “MOSFET technology for programmable address decode and correction,” application Ser. No. 09/383,804). That disclosure, however, did not describe write once read only memory solutions, but rather address decode and correction issues. The inventors also describe write once read only memory cells employing charge trapping in gate insulators for conventional MOSFETs and write once read only memory employing floating gates. The same are described in co-pending, commonly assigned U.S. patent applications, entitled “Write Once Read Only Memory Employing Charge Trapping in Insulators,” attorney docket no. 1303.052US1, Ser. No. ______, and “Write Once Read Only Memory Employing Floating Gates,” attorney docket no. 1303.051US1, Ser. No. ______. The present application, however, describes NOR flash cells formed from conventional flash memory device structures.

[0033] According to the teachings of the present invention, normal flash memory cells can be programmed by operation in the reverse direction and utilizing avalanche hot electron injection to trap electrons on the floating gate of the floating gate transistor. When the programmed floating gate transistor is subsequently operated in the forward direction the electrons trapped on the floating gate cause the channel to have a different threshold voltage. The novel programmed floating gate transistors of the present invention conduct significantly less current than conventional flash cells which have not been programmed. These electrons will remain trapped on the floating gate unless negative control gate voltages are applied. The electrons will not be removed from the floating gate when positive or zero control gate voltages are applied. Erasure can be accomplished by applying negative control gate voltages and/or increasing the temperature with negative control gate bias applied to cause the trapped electrons on the floating gate to be re-emitted back into the silicon channel of the MOSFET.

[0034] FIG. 2A is a diagram of a programmed floating gate transistor which can be used as a NOR flash cell according to the teachings of the present invention. As shown in FIG. 2A the NOR flash cell 201 includes a floating gate transistor in a substrate 200 which has a first source/drain region 202, a second source/drain region 204, and a channel region 206 between the first and second source/drain regions, 202 and 204. In one embodiment, the first source/drain region 202 includes a source region 202 for the floating gate transistor and the second source/drain region 204 includes a drain region 204 for the floating gate transistor. FIG. 2A further illustrates a floating gate 208 separated from the channel region 206 by a floating gate insulator 210. An array plate 212 is coupled to the first source/drain region 202 and a transmission line 214 is coupled to the second source/drain region 204. In one embodiment, the transmission line 214 includes a bit line 214. Further as shown in FIG. 2A, a control gate 216 is separated from the floating gate 208 by a gate dielectric 218.

[0035] As stated above, NOR flash cell 201 is comprised of a programmed floating gate transistor. This programmed floating gate transistor has a charge 217 trapped on the floating gate 208. In one embodiment, the charge 217 trapped on the floating gate 208 includes a trapped electron charge 217.

[0036] FIG. 2B is a diagram suitable for explaining the method by which the floating gate of the NOR flash cell 201 of the present invention can be programmed to achieve the embodiments of the present invention. As shown in FIG. 2B the method includes programming the floating gate transistor. Programming the floating gate transistor includes applying a first voltage potential V1 to a drain region 204 of the floating gate transistor and a second voltage potential V2 to the source region 202.

[0037] In one embodiment, applying a first voltage potential V1 to the drain region 204 of the floating gate transistor includes grounding the drain region 204 of the floating gate transistor as shown in FIG. 2B. In this embodiment, applying a second voltage potential V2 to the source region 202 includes biasing the array plate 212 to a voltage higher than VDD, as shown in FIG. 2B. A gate potential VGS is applied to the control gate 216 of the floating gate transistor. In one embodiment, the gate potential VGS includes a voltage potential which is less than the second voltage potential V2, but which is sufficient to establish conduction in the channel 206 of the floating gate transistor between the drain region 204 and the source region 202. As shown in FIG. 2B, applying the first, second and gate potentials (V1, V2, and VGS respectively) to the floating gate transistor creates a hot electron injection into the floating gate 208 of the floating gate transistor adjacent to the source region 202. In other words, applying the first, second and gate potentials (V1, V2, and VGS respectively) provides enough energy to the charge carriers, e.g. electrons, being conducted across the channel 206 that, once the charge carriers are near the source region 202, a number of the charge carriers get excited into the floating gate 208 adjacent to the source region 202. Here the charge carriers become trapped.

[0038] In an alternative embodiment, applying a first voltage potential V1 to the drain region 204 of the floating gate transistor includes biasing the drain region 204 of the floating gate transistor to a voltage higher than VDD. In this embodiment, applying a second voltage potential V2 to the source region 202 includes grounding the array plate 212. A gate potential VGS is applied to the control gate 216 of the floating gate transistor. In one embodiment, the gate potential VGS includes a voltage potential which is less than the first voltage potential V1, but which is sufficient to establish conduction in the channel 206 of the floating gate transistor between the drain region 204 and the source region 202. Applying the first, second and gate potentials (V1, V2, and VGS respectively) to the floating gate transistor creates a hot electron injection into the floating gate 208 of the floating gate transistor adjacent to the drain region 204. In other words, applying the first, second and gate potentials (V1, V2, and VGS respectively) provides enough energy to the charge carriers, e.g. electrons, being conducted across the channel 206 that, once the charge carriers are near the drain region 204, a number of the charge carriers get excited into the floating gate 208 adjacent to the drain region 204. Here the charge carriers become trapped as shown in FIG. 2A.

[0039] In one embodiment of the present invention, the method is continued by subsequently operating the floating gate transistor in the forward direction in its programmed state during a read operation. Accordingly, the read operation includes grounding the source region 202 and precharging the drain region a fractional voltage of VDD. If the device is addressed by a wordline coupled to the gate, then its conductivity will be determined by the presence or absence of stored charge in the floating gate. That is, a gate potential can be applied to the control gate 216 by a wordline 220 in an effort to form a conduction channel between the source and the drain regions as done with addressing and reading conventional DRAM cells.

[0040] However, now in its programmed state, the conduction channel 206 of the floating gate transistor will have a higher voltage threshold and will not conduct.

[0041] FIG. 2C is a graph plotting a current signal (IDS) detected at the second source/drain region 204 versus a voltage potential, or drain voltage, (VDS) set up between the second source/drain region 204 and the first source/drain region 202 (IDS vs. VDS). In one embodiment, VDS represents the voltage potential set up between the drain region 204 and the source region 202. In FIG. 2C, the curve plotted as D1 represents the conduction behavior of a conventional floating gate transistor which is not programmed according to the teachings of the present invention. The curve D2 represents the conduction behavior of the programmed floating gate transistor, described above in connection with FIG. 2A, according to the teachings of the present invention. As shown in FIG. 2C, for a particular drain voltage, VDS, the current signal (IDS2) detected at the second source/drain region 204 for the programmed floating gate transistor (curve D2) is significantly lower than the current signal (IDS1) detected at the second source/drain region 204 for the conventional floating gate cell which is not programmed according to the teachings of the present invention. Again, this is attributed to the fact that the channel 206 in the programmed floating gate transistor of the present invention has a different voltage threshold.

[0042] Some of these effects have recently been described for use in a different device structure, called an NROM, for flash memories. This latter work in Israel and Germany is based on employing charge trapping in a silicon nitride layer in a non-conventional flash memory device structure. (See generally, B. Eitan et al., “Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM device,” IEEE Electron Device Lett., Vol. 22, No. 11, pp. 556-558, (November 2001); B. Etian et al., “NROM: A novel localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Lett., Vol. 21, No. 11, pp. 543-545, (November 2000)). Charge trapping in silicon nitride gate insulators was the basic mechanism used in MNOS memory devices (see generally, S. Sze, Physics of Semiconductor Devices, Wiley, N.Y., 1981, pp. 504-506), charge trapping in aluminum oxide gates was the mechanism used in MIOS memory devices (see generally, S. Sze, Physics of Semiconductor Devices, Wiley, N.Y., 1981, pp. 504-506), and the present inventors have previously disclosed charge trapping at isolated point defects in gate insulators (see generally, L. Forbes and J. Geusic, “Memory using insulator traps,” U.S. Pat. No. 6,140,181, issued Oct. 31, 2000). However, none of the above described references addressed forming NOR flash memory cells.

[0043] That is, in contrast to the above work, the present invention discloses programming a floating gate transistor to trap charge and reading the device to form a NOR flash memory cell with high density.

[0044] FIG. 3 illustrates a portion of a memory array 300 according to the teachings of the present invention. The memory in FIG. 3, is shown illustrating a number of vertical pillars, or NOR flash cells, 301-1, 301-2, . . . , 301-N, formed according to the teachings of the present invention. As one of ordinary skill in the art will appreciate upon reading this disclosure, the number of vertical pillar are formed in rows and columns extending outwardly from a substrate 303. As shown in FIG. 3, the number of vertical pillars, 301-1, 301-2, . . . , 301-N, are separated by a number of trenches 340. According to the teachings of the present invention, the number of vertical pillars, 301-1, 301-2, . . . , 301-N, serve as NOR floating gate transistors including a first source/drain region, e.g. 302-1 and 302-2 respectively. The first source/drain region, 302-1 and 302-2, is coupled to a sourceline 304. As shown in FIG. 3, the sourceline 304 is formed in a bottom of the trenches 340 between rows of the vertical pillars, 301-1, 301-2, . . . , 301-N. According to the teachings of the present invention, the sourceline 304 is formed from a doped region implanted in the bottom of the trenches 340. A second source/drain region, e.g. 306-1 and 306-2 respectively, is coupled to a bitline (not shown). A channel region 305 is located between the first and the second source/drain regions.

[0045] As shown in FIG. 3, a floating gate, shown generally as 309, is separated from the channel region 305 by a first gate insulator 307 in the trenches 340 along rows of the vertical pillars, 301-1, 301-2, . . . , 301-N. In one embodiment, according to the teachings of the present invention, the first gate insulator 307 includes a gate insulator 307 selected from the group of silicon dioxide (SiO2) formed by wet oxidation, silicon oxynitride (SON), silicon rich oxide (SRO), and aluminum oxide (Al2O3). In another embodiment, according to the teachings of the present invention, the gate insulator 307 includes an oxide-nitride-oxide (ONO) gate insulator 307. In the embodiment shown in FIG. 3, a control line 313 is formed across the number of pillars and in the trenches 340 between the floating gates. The control line 313 is separated from the pillars and the floating gates by a second gate insulator 317.

[0046] FIG. 4 illustrates an electrical equivalent circuit 400 for the portion of the memory array shown in FIG. 3. As shown in FIG. 4, a number of vertical NOR flash cells, 401-1, 401-2, . . . , 401-N, are provided. Each vertical NOR flash cell, 401-1, 401-2, . . . , 401-N, includes a first source/drain region, e.g. 402-1 and 402-2, a second source/drain region, e.g. 406-1 and 406-2, a channel region 405 between the first and the second source/drain regions, and a floating gate, shown generally as 409, separated from the channel region by a first gate insulator.

[0047] FIG. 4 further illustrates a number of bit lines, e.g. 411-1 and 411-2. According to the teachings of the present invention as shown in the embodiment of FIG. 4, a single bit line, e.g. 411-1 is coupled to the second source/drain regions, e.g. 406-1 and 406-2, for a pair of NOR flash cells 401-1 and 401-2 since, as shown in FIG. 3, each pillar contains two NOR flash cells. As shown in FIG. 4, the number of bit lines, 411-1 and 411-2, are coupled to the second source/drain regions, e.g. 406-1 and 406-2, along rows of the memory array. A number of word lines, such as wordline 413 in FIG. 4, are coupled to a control gate 412 of each NOR flash cell along columns of the memory array. According to the teachings of the present invention, a number of sourcelines, 415-1, 415-2, . . . , 415-N, are formed in a bottom of the trenches between rows of the vertical pillars, described in connection with FIG. 3, such that first source/drain regions, e.g. 402-2 and 402-3, in column adjacent NOR flash cells, e.g. 401-2 and 401-3, separated by a trench, share a common sourceline, e.g. 415-1. And additionally, the number of sourcelines, 415-1, 415-2, . . . , 415-N, are shared by column adjacent NOR flash cells, e.g. 401-2 and 401-3, separated by a trench, along rows of the memory array 400. In this manner, by way of example and not by way of limitation referring to column adjacent NOR flash cells, e.g. 401-2 and 401-3, separated by a trench, when one column adjacent NOR flash cell, e.g. 401-2, is being read its complement column adjacent NOR flash cell, e.g. 401-3, can operate as a reference cell.

[0048] FIGS. 5A-5E are cross sectional views of various embodiments of the invention from the same vantage point illustrated in FIG. 3. However, FIGS. 5A-5E are intended to illustrate the numerous floating gate and control gate configurations which are intended within the scope of the present invention. For each of the embodiments illustrated in FIGS. 5A-5E, a wordline (not shown for sake of clarity) will couple to the various control gate configurations along columns of an array, and the sourcelines and bitlines will run along rows of the array (here shown running into the plane of the drawing sheet), in the same fashion as wordline 413, sourcelines 415-1, 415-2, . . . , 415-N, and bitlines 411-1, 411-2, . . . , 411-N are arranged in FIG. 4. For each of the embodiments illustrated in FIGS. 5A-5E, a number of vertical pillars, e.g. 500-1 and 500-2, are illustrated with each pillar containing a pair of NOR flash cells. In these embodiments, a single second source/drain region 503 is shared at the top of each pillar. Each of the pillars are separated by rows of trenches 530. A buried sourceline is located at the bottom of each trench 530, e.g. a doped region implanted in the bottom of trenches 530. In these embodiments, a portion of the buried sourceline undercuts the pillars, e.g. 500-1 and 500-2, on opposing sides to serve as the respective first source/drain region for the pair of NOR flash cells. Thus, on each side of a pillar, a conduction channel 505 can be created in the body 507 of the pillar between the second source/drain region 503 and the respective sourcelines in each neighboring trench.

[0049] As one of ordinary skill in the art will understand upon reading this disclosure, the NOR flash cells are programmed by grounding the source line and applying a gate voltage and a voltage to the second source/drain region, e.g. drain region. To read this state the drain and ground or source have the normal connections and the conductivity of the transistor determined. The devices can be erased by applying a large negative voltage to the gate and positive voltage to the source. The coincidence and of gate and source bias at the same location can erase a transistor at this location, but the gate bias alone or source bias alone is not sufficient to disturb or erase the charge storage state of other transistors in the array.

[0050] FIG. 5A illustrates one embodiment of the present invention's floating gate and control gate configuration. As shown in the embodiment of FIG. 5A, a pair of floating gates 509-1 and 509-2 are formed in each trench 530 between adjacent pillars which form memory cells 500-1 and 500-2. Each one of the pair of floating gates, 509-1 and 509-2, respectively opposes the body regions 507-1 and 507-2 in column adjacent pillars 500-1 and 500-2 on opposing sides of the trench 530.

[0051] In the embodiment of FIG. 5A, a single control gate 513 is shared by the pair of floating gates 509-1 and 509-2 on opposing sides of the trench 530. As shown in FIG. 5A, the single control gate 513 is formed in the trench, such as trench 530, below the top surface of the pillars 500-1 and 500-2 and between the pair of floating gates 509-1 and 509-2. In one embodiment, according to the teachings of the present invention, each floating gate, e.g. 509-1 and 509-2, includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

[0052] FIG. 5B illustrates another embodiment of the present invention's floating gate and control gate configuration. As shown in the embodiment of FIG. 5B, a pair of floating gates 509-1 and 509-2 are formed in each trench 530 between column adjacent pillars 500-1 and 500-2. Each one of the pair of floating gates, 509-1 and 509-2, respectively opposes the body regions 507-1 and 507-2 in column adjacent pillars 500-1 and 500-2 on opposing sides of the trench 530.

[0053] In the embodiment of FIG. 5B, a pair of control gates, shown as 513-1 and 513-2, are formed in trenches, e.g. trench 530, below the top surface of the pillars, 500-1 and 500-2, and between the pair of floating gates 509-1 and 509-2. Each one of the pair of control gates, 513-1 and 513-2, addresses the floating gates, 509-1 and 509-2 respectively, on opposing sides of the trench 530. In this embodiment, the pair of control gates 513-1 and 513-2 are separated by an insulator layer.

[0054] FIG. 5C illustrates another embodiment of the present invention's floating gate and control gate configuration. As shown in the embodiment of FIG. 5C, a pair of floating gates 509-1 and 509-2 are again formed in each trench 530 between adjacent pillars which form memory cells 500-1 and 500-2. Each one of the pair of floating gates, 509-1 and 509-2, respectively opposes the body regions 507-1 and 507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of the trench 530.

[0055] In the embodiment of FIG. 5C, the control gates 513 are disposed vertically above the floating gates. That is, in this embodiment, the control gates 513 are located above the pair of floating gates 509-1 and 509-2 and not fully beneath the top surface of the pillars 500-1 and 500-2. In the embodiment of FIG. 5C, each pair of floating gates, e.g. 509-1 and 509-2, in a given trench shares a single control gate 513.

[0056] FIG. 5D illustrates another embodiment of the present invention's floating gate and control gate configuration. As shown in the embodiment of FIG. 5D, a pair of floating gates 509-1 and 509-2 are formed in each trench 530 between adjacent pillars which form memory cells 500-1 and 500-2. Each one of the pair of floating gates, 509-1 and 509-2, respectively opposes the body regions 507-1 and 507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of the trench 530.

[0057] In the embodiment of FIG. 5D, a pair of individual control gates 513-1 and 513-2 are disposed vertically above each individual one of the pair of floating gates 509-1 and 509-2. That is, the pair of individual control gates 513-1 and 513-2 are located above the pair of floating gates 509-1 and 509-2 and not fully beneath the top surface of the pillars 500-1 and 500-2.

[0058] FIG. 5E illustrates another embodiment of the present invention's floating gate and control gate configuration. As shown in the embodiment of FIG. 5E, a single floating gate 509 is formed in each trench 530 between adjacent pillars which form memory cells 500-1 and 500-2. According to the teachings of the present invention, the single floating gate 509 can be either a vertically oriented floating gate 509 or a horizontally oriented floating gate 509 formed by conventional processing techniques, or can be a horizontally oriented floating gate 509 formed by a replacement gate technique such as described in a copending application, entitled “Flash Memory with Ultrathin Vertical Body Transistors,” by Leonard Forbes and Kie Y. Ahn, application Ser. No. 09/780,169. The same is incorporated herein in full. In one embodiment of the present invention, the floating gate 509 has a vertical length facing the channel regions 505-1 and 505-2 of less than 100 nm. In another embodiment, the floating gate 509 has a vertical length facing the channel regions 505-1 and 505-2 of less than 50 nm. In one embodiment, as shown in FIG. 5E, the floating gate 509 is shared, respectively, with the body regions 507-1 and 507-2, including channel regions 505-1 and 505-2, in adjacent pillars 500-1 and 500-2 located on opposing sides of the trench 530.

[0059] In the embodiment of FIG. 5E, the control gates 513 are disposed vertically above the floating gates. That is, in this embodiment, the control gates 513 are located above the floating gate 509 and not fully beneath the top surface of the pillars 500-1 and 500-2.

[0060] FIGS. 6A-B and 7 are useful in illustrating the use of charge storage in the floating gate to modulate the conductivity of the NOR flash memory cell according to the teachings of the present invention. That is, FIGS. 6A-6B illustrates the operation of the novel NOR flash memory cell 601 formed according to the teachings of the present invention. And, FIG. 7 illustrates the operation of a conventional DRAM cell 501. As shown in FIG. 7, the gate insulator 702 is made thicker than in a conventional DRAM cell, e.g. 701 and is equal to or greater than 10 nm or 100 Å (10−6 cm). In the embodiment shown in FIG. 7A a NOR flash memory cell is illustrated having dimensions of 0.1 μm (10−5 cm) by 0.1 μm. The capacitance, Ci, of the structure depends on the dielectric constant, εi, (given here as 0.3×10−12F/cm), and the thickness of the insulating layers, t, (given here as 10−6 cm), such that Ci=εi/t, Farads/cm2 or 3×10−7F/cm2. In one embodiment, a charge of 1012 electrons/cm2 is programmed into the floating gate of the NOR flash memory cell. This produces a stored charge Δ Q=1012 electrons/cm2×1.6×10−19 Coulombs. In this embodiment, the resulting change in the threshold voltage (Δ Vt) of the NOR flash memory cell will be approximately 0.5 Volts (Δ Vt=Δ Q/Ci or 1.6×10−7/3×10−7=½ Volt). For Δ Q=1012 electrons/cm3 in the dimensions given above, this embodiment of the present invention involves trapping a charge of approximately 100 electrons in the floating gate of the NOR flash memory cell.

[0061] FIG. 6B aids to further illustrate the conduction behavior of the novel NOR flash memory cell of the present invention. As one of ordinary skill in the art will understand upon reading this disclosure, if the NOR flash memory cell is being driven with a control gate voltage of 1.0 Volt (V) and the nominal threshold voltage without the floating gate charged is ½ V, then if the floating gate is charged the floating gate transistor of the present invention will be off and not conduct. That is, by trapping a charge of approximately 100 electrons in the floating gate of the NOR flash memory cell, having dimensions of 0.1 μm (10−5 cm) by 0.1 μm, will raise the threshold voltage of the NOR flash memory cell to 1.0 Volt and a 1.0 Volt control gate potential will not be sufficient to turn the device on, e.g. Vt=1.0 V, I=0.

[0062] Conversely, if the nominal threshold voltage without the floating gate charged is ½ V, then I=μCOXx (W/L)×((Vgs−Vt)2/2), or 12.5 μA, with μCOX=μCi=100 μA/V2 and W/L=1. That is, the NOR flash memory cell of the present invention, having the dimensions describe above will produce a current I=100 μA/V2×(¼)×(½)=12.5 μA. Thus, in the present invention an un-written, or un-programmed NOR flash memory cell can conduct a current of the order 12.5 μA, whereas if the floating gate is charged then the NOR flash memory cell will not conduct. As one of ordinary skill in the art will understand upon reading this disclosure, the sense amplifiers used in DRAM arrays, and as describe above, can easily detect such differences in current on the bit lines.

[0063] By way of comparison, in a conventional DRAM with 30 femtoFarad (fF) storage capacitors charged to 50 femtoColumbs (fC), if these are read over 5 nS then the average current on the bit line is only 10 μA. This is illustrated in connection with FIG. 7. As shown in FIG. 7, storing a 50 fC charge on the storage capacitor equates to storing 300,000 electrons.

[0064] According to the teachings of the present invention, the floating gate transistors in the array are utilized not just as passive on or off switches as transfer devices in DRAM arrays but rather as active devices providing gain. In the present invention, to program the floating gate transistor “off,” requires only a stored charge in the floating gate of about 100 electrons if the area is 0.1 μm by 0.1 μm. And, if the NOR flash memory cell is un-programmed, e.g. no stored charge trapped in the floating gate, and if the floating gate transistor is addressed over 10 nS a of current of 12.5 μA is provided. The integrated drain current then has a charge of 125 fC or 800,000 electrons. This is in comparison to the charge on a DRAM capacitor of 50 fC which is only about 300,000 electrons. Hence, the use of the floating gate transistors in the array as active devices with gain, rather than just switches, provides an amplification of the stored charge, in the floating gate, from 100 to 800,000 electrons over a read address period of 10 nS.

[0065] In FIG. 8 a memory device is illustrated according to the teachings of the present invention. The memory device 840 contains a memory array 842, row and column decoders 844, 848 and a sense amplifier circuit 846. The memory array 842 consists of a plurality of NOR flash memory cells 800, formed according to the teachings of the present invention whose word lines 880 and bit lines 860 are commonly arranged into rows and columns, respectively. The bit lines 860 of the memory array 842 are connected to the sense amplifier circuit 846, while its word lines 880 are connected to the row decoder 844. Address and control signals are input on address/control lines 861 into the memory device 840 and connected to the column decoder 848, sense amplifier circuit 846 and row decoder 844 and are used to gain read and write access, among other things, to the memory array 842.

[0066] The column decoder 848 is connected to the sense amplifier circuit 846 via control and column select signals on column select lines 862. The sense amplifier circuit 846 receives input data destined for the memory array 842 and outputs data read from the memory array 842 over input/output (I/O) data lines 863. Data is read from the cells of the memory array 842 by activating a word line 880 (via the row decoder 844), which couples all of the memory cells corresponding to that word line to respective bit lines 860, which define the columns of the array. One or more bit lines 860 are also activated. When a particular word line 880 and bit lines 860 are activated, the sense amplifier circuit 846 connected to a bit line column detects and amplifies the conduction sensed through a given NOR flash memory cell and transferred to its bit line 860 by measuring the potential difference between the activated bit line 860 and a reference line which may be an inactive bit line. Again, in the read operation the source region of a given cell is couple to a grounded array plate (not shown). The operation of Memory device sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein.

[0067] FIG. 9 is a block diagram of an electrical system, or processor-based system, 900 utilizing NOR flash memory 912 constructed in accordance with the present invention. That is, the NOR flash memory 912 utilizes the modified NOR flash cell architecture as explained and described in detail in connection with FIGS. 2-6. The processor-based system 900 may be a computer system, a process control system or any other system employing a processor and associated memory. The system 900 includes a central processing unit (CPU) 902, e.g., a microprocessor, that communicates with the NOR flash memory 912 and an I/O device 908 over a bus 920. It must be noted that the bus 920 may be a series of buses and bridges commonly used in a processor-based system, but for convenience purposes only, the bus 920 has been illustrated as a single bus. A second I/O device 910 is illustrated, but is not necessary to practice the invention. The processor-based system 900 can also includes read-only memory (ROM) 914 and may include peripheral devices such as a floppy disk drive 904 and a compact disk (CD) ROM drive 906 that also communicates with the CPU 902 over the bus 920 as is well known in the art.

[0068] It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device 900 has been simplified to help focus on the invention. At least one of the NOR flash memory cell in NOR flash memory 912 includes a programmed flash cell.

[0069] It will be understood that the embodiment shown in FIG. 9 illustrates an embodiment for electronic system circuitry in which the novel memory cells of the present invention are used. The illustration of system 900, as shown in FIG. 9, is intended to provide a general understanding of one application for the structure and circuitry of the present invention, and is not intended to serve as a complete description of all the elements and features of an electronic system using the novel memory cell structures. Further, the invention is equally applicable to any size and type of memory device 900 using the novel memory cells of the present invention and is not intended to be limited to that described above. As one of ordinary skill in the art will understand, such an electronic system can be fabricated in single-package processing units, or even on a single semiconductor chip, in order to reduce the communication time between the processor and the memory device.

[0070] Applications containing the novel memory cell of the present invention as described in this disclosure include electronic systems for use in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Such circuitry can further be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and others.

CONCLUSION

[0071] Two transistors occupy an area of 4F squared when viewed from above, or each memory cell consisting of one transistor has an area of 2F squared. NAND flash memories are ideally as small as 4F squared in conventional planar device technology, with practical devices having a cell area of 5F squared. The vertical NOR flash memory cells described here have a higher density than conventional planar NAND cells but they would operate at speeds higher than or comparable to conventional planar NOR flash memories. The NOR flash memories described here then have both high density and high speed.

[0072] It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. A NOR flash memory cell, comprising: a vertical floating gate transistor extending outwardly from a substrate, the floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a sourceline formed in a trench adjacent to the vertical floating gate transistor, wherein the first source/drain region is coupled to the sourceline; a transmission line coupled to the second source/drain region; and wherein the floating gate transistor is a programmed floating gate transistor having a charge trapped in the floating gate such that the programmed floating gate transistor operates at reduced drain source current.

2. The NOR flash memory cell of claim 1, wherein the first source/drain region of the floating gate transistor includes a source region and the second source/drain region of the floating gate transistor includes a drain region.

3. The NOR flash memory cell of claim 1, wherein the transmission line includes a bit line.

4. The NOR flash memory cell of claim 1, wherein the gate insulator has a thickness of approximately 10 nanometers (nm).

5. A NOR flash memory cell, comprising: a vertical floating gate transistor formed according to a modified DRAM fabrication process, the floating gate transistor having a source region, a drain region, a channel region between the source and the drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a wordline coupled to the control gate; a sourceline formed in a trench adjacent to the vertical floating gate transistor, wherein the source region is coupled to the sourceline; a bit line coupled to the drain region; and wherein the floating gate transistor is a programmed floating gate transistor having a charge trapped in the floating gate.

6. The NOR flash memory cell of claim 5, wherein the gate insulator has a thickness of at least 10 nanometers (nm).

7. A NOR memory array, comprising: a number of NOR flash memory cells extending from a substrate and separated by trenches, wherein each flash memory cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator, and a control gate separated from the floating gate a second gate insulator; a number of bit lines coupled to the second source/drain region of each flash memory cell along rows of the memory array; a number of word lines coupled to the control gate of each flash memory cell along columns of the memory array; a number of sourcelines along rows in the trenches between the number of flash memory cells extending from a substrate, wherein the first source/drain region of each flash memory cell is coupled to the number of sourcelines; and wherein at least one of flash memory cells is a programmed cell having a charge trapped in the floating gate.

8. The memory array of claim 7, wherein each NOR flash memory cell includes a vertical NOR flash memory cell.

9. The memory array of claim 7, wherein the first gate insulator of each NOR flash memory cell has a thickness of approximately 10 nanometers (nm).

10. The memory array of claim 7, wherein the number of NOR flash memory cells extending from a substrate operate as equivalent to a transistor having a size of approximately 2.0 lithographic features squared (2F2).

11. A NOR memory array, comprising: a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as floating gate transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator in the trenches along rows of pillars, and a control gate separated from the floating gate a second gate insulator, wherein along columns of the pillars adjacent pillars include a floating gate transistor which operates as a programmed cell on one side of a trench and a floating gate transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench; a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array; a number of word lines coupled to the control gate of each floating gate transistor along columns of the memory array; a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each floating gate transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couple to the sourceline in a shared trench.

12. The memory array of claim 11, wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates on opposing sides of the trench opposing the channel regions in column adjacent pillars.

13. The memory array of claim 12, wherein the control gate is formed in the trench below the top surface of the pillars and between the pair of floating gates, wherein each pair of floating gates shares a single control gate, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

14. The memory array of claim 12, wherein the control gates are formed in the trench below the top surface of the pillars and between the pair of floating gates such that each trench houses a pair of control gates each addressing a floating gate on opposing sides of the trench respectively, and wherein the pair of control gates are separated by an insulator layer.

15. The memory array of claim 12, wherein the control gates are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate line.

16. The memory array of claim 12, wherein a pair of control gates are disposed vertically above the floating gates.

17. The memory array of claim 11, wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the channel regions in column adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the channel regions of the pillars.

18. The memory array of claim 17, wherein the control gates are disposed vertically above the floating gates.

19. The memory array of claim 11, wherein the number of sourcelines formed in a bottom of the trenches between rows of the pillars include a doped region implanted in the bottom of the trench.

20. The memory array of claim 11, wherein the first gate insulator of each floating gate transistor has a thickness of approximately 10 nanometers (nm).

21. The memory array of claim 11, wherein each floating gate transistor operates as equivalent to a transistor having a size of approximately 2.0 lithographic features squared (2F2).

22. A memory device, comprising: a NOR memory array, wherein the memory array includes a number of vertical NOR flash cells extending outwardly from a substrate and separated by trenches, wherein each NOR flash cell includes a source region, a drain region, a channel region between the source and the drain regions, a floating gate separated from the channel region by a first gate insulator, and a control gate separated from the floating gate a second gate insulator; a number of bitlines coupled to the drain region of each vertical NOR flash cell along rows of the memory array; a number of wordlines coupled to the control gate of each vertical NOR flash cell along columns of the memory array; a number of sourcelines, wherein the first source/drain region of each vertical NOR flash cell is integrally formed with the number of sourcelines along rows in the trenches between the number of vertical NOR flash cells extending from a substrate; a wordline address decoder coupled to the number of wordlines; a bitline address decoder coupled to the number of bitlines; and one or more sense amplifiers coupled to the number of bitlines.

23. The memory device of claim 22, wherein the first gate insulator of each NOR flash cell has a thickness of approximately 10 nanometers (nm).

24. The memory device of claim 23, wherein the wordline address decoder and the bitline address decoder each include conventionally fabricated MOSFET transistors having thin gate insulators formed of silicon dioxide (SiO2).

25. The memory device of claim 23, wherein the one or more sense amplifiers include conventionally fabricated MOSFET transistors having thin gate insulators formed of silicon dioxide (SiO2).

26. An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein the memory device includes a NOR memory array, the NOR memory array including; a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein each vertical pillar comprises a pair of floating gate transistors on opposing sides of each pillar, including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a first gate insulator in the trenches along rows of pillars, and a control gate separated from the floating gate by a second gate insulator, wherein along columns of the pillars the trench between column adjacent pillars include a pair of floating gates each one opposing the channel regions of the pillar on a respective side of the trench; a number of bit lines coupled to the second source/drain region of each floating gate transistor along rows of the memory array; a number of word lines coupled to the control gate of each floating gate transistor along columns of the memory array; a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each floating gate transistor along rows of pillars, wherein along rows of the pillars the first source/drain region of each floating gate transistor in column adjacent pillars couple to the sourceline in a shared trench such that each floating gate transistor neighboring the shared trench share a common sourceline; and wherein at least one of floating gate transistors is a programmed flash cell.

27. The electronic system of claim 26, wherein the programmed flash cell includes a charge of approximately 100 electrons trapped on the floating gate of the programmed flash cell.

28. The electronic system of claim 26, wherein each floating gate transistor operates as equivalent to a floating gate transistor having a size equal to or less than 2.0 lithographic features squared (2F2).

29. The electronic system of claim 26, wherein, in a read operation, a sourceline for two column adjacent pillars sharing a trench is coupled to a ground potential, the drain regions of the column adjacent pillars sharing a trench are precharged to a fractional voltage of VDD, and the control gate for each of the column adjacent pillars sharing a trench is addressed such that a conductivity state of a floating gate transistor in the NOR memory array can be sensed.

30. The electronic system of claim 26, wherein, in a write operation, a sourceline for two column adjacent pillars sharing a trench is biased to a voltage higher than VDD, one of the drain regions of the column adjacent pillars sharing a trench is coupled to a ground potential, and the control gate for each of the column adjacent pillars sharing a trench is addressed with a wordline potential.

31. A method for operating a NOR memory array, comprising: programming one or more vertical NOR flash cells extending outwardly from a substrate and separated by trenches, wherein each NOR flash cell includes a source region, a drain region, a channel region between the source and the drain regions, a floating gate separated from the channel region by a first gate insulator in the trenches along rows of the NOR flash cells, and a control gate separated from the floating gate by a second gate insulator, wherein along columns of the NOR flash cells the trench between column adjacent NOR flash cells includes a pair of floating gates each one opposing the channel regions of the NOR flash cell on a respective side of the trench, wherein the array includes a number of sourcelines formed in a bottom of the trenches between rows of the NOR flash cells and coupled to the source regions of NOR flash cell along rows the vertical NOR flash cells, wherein along rows of the NOR flash cells the first source/drain region of each NOR flash cell in column cells couples to the sourceline in a shared trench such that each NOR flash cell neighboring the shared trench share a common sourceline, and wherein programming the one or more vertical NOR flash cells includes: applying a first voltage potential to a drain region of a vertical NOR flash cell; applying a second voltage potential to a source region of the vertical NOR flash cell; applying a control gate potential to a control gate of the vertical NOR flash cell; and wherein applying the first, second and gate potentials to the one or more vertical NOR flash cells includes creating a hot electron injection into the floating gate of the one or more NOR flash cells.

32. The method of claim 31, wherein applying a first voltage potential to the drain region of the vertical NOR flash cell includes grounding the drain region of the vertical NOR flash cell.

33. The method of claim 32, wherein applying a second voltage potential to the source region includes applying a high voltage potential (VDD) to a sourceline coupled thereto.

34. The method of claim 33, wherein applying a control gate potential to the control gate of the vertical NOR flash cell includes applying a gate potential to the control gate in order to create a conduction channel between the source and drain regions of the vertical NOR flash cell.

35. The method of claim 31, wherein the method further includes reading one or more vertical NOR flash cells by operating an addressed vertical NOR flash cell in a forward direction, wherein operating the vertical NOR flash cell in the forward direction includes: grounding a sourceline for two column adjacent NOR flash cells sharing a trench; precharging the drain regions of the column adjacent NOR flash cells sharing the trench to a fractional voltage of VDD; and applying a control gate potential of approximately 1.0 Volt to the control gate for each of the column adjacent NOR flash cells sharing the trench such that a conductivity state of the addressed vertical NOR flash cell can be compared to a conductivity state of a reference cell.

36. The method of claim 35, wherein reading the one or more NOR flash cells in the forward direction includes using a sense amplifier to detect whether an addressed NOR flash cell is a programmed NOR flash cell, wherein a programmed NOR flash cell will not conduct, and wherein an unprogrammed NOR flash cell addressed over approximately 10 ns will conduct a current of approximately 12.5 μA such that the method includes detecting an integrated drain current having a charge of 800,000 electrons using the sense amplifier.

37. The method of claim 31, wherein in creating a hot electron injection into the floating gate of the addressed NOR flash cell includes changing a threshold voltage for the NOR flash cell by approximately 0.5 Volts.

38. The method of claim 36, wherein in creating a hot electron injection into the floating gate of the addressed NOR flash cell includes trapping a stored charge in the floating gate of the addressed NOR flash cell of approximately 1012 electrons/cm2.

39. The method of claim 31, wherein in creating a hot electron injection into the floating gate of the addressed NOR flash cell includes trapping a stored charge in the floating gate of the addressed NOR flash cell of approximately 100 electrons.

40. The method of claim 38, wherein the method further includes using the NOR flash cell as active device with gain, and wherein reading a programmed NOR flash cell includes providing an amplification of a stored charge in the floating gate from 100 to 800,000 electrons over a read address period of approximately 10 ns.

41. A method for forming a NOR flash memory array, comprising: forming a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein forming the number of vertical pillars includes forming the number of vertical pillars to serve as floating gate transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator in the trenches along rows of pillars, and a control gate separated from the floating gate a second gate insulator, wherein along columns of the pillars adjacent pillars include a floating gate transistor which operates as a programmed cell on one side of a trench and a floating gate transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench; forming a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array; forming a number of word lines coupled to the control gate of each floating gate transistor along columns of the memory array; forming a number of sourcelines in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each floating gate transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couple to the sourceline in a shared trench.

42. The method of claim 41, wherein forming each floating gate includes forming each floating gate as a vertical floating gate in a trench below a top surface of each pillar, and forming a pair of floating gates in each trench on opposing sides of the trench and opposing the channel regions in column adjacent pillars.

43. The method of claim 42, wherein the method includes forming the control gate in the trench below the top surface of the pillars and between the pair of floating gates such that each pair of floating gates shares a single control gate, and wherein forming each floating gate includes forming a vertically oriented floating gate having a vertical length of less than 100 nanometers.

44. The method of claim 42, wherein the method includes forming the control gates in the trench below the top surface of the pillars and between the pair of floating gates such that each trench houses a pair of control gates each addressing a floating gate on opposing sides of the trench respectively, and wherein the pair of control gates are separated by an insulator layer.

45. The method of claim 42, wherein the method includes forming the control gates disposed vertically above the floating gates, and forming the control gates such that each pair of floating gates shares a single control gate line.

46. The method of claim 42, wherein the method includes forming a pair of control gates disposed vertically above the floating gates.

47. The method of claim 41, wherein forming each floating gate includes forming each floating gate as a horizontally oriented floating gate in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the channel regions in column adjacent pillars on opposing sides of the trench, and wherein forming each horizontally oriented floating gate includes forming each horizontally oriented floating gate to have a vertical length of less than 100 nanometers opposing the channel regions of the pillars.

48. The method of claim 47, wherein the method includes forming the control gates disposed vertically above the floating gates.

49. The method of claim 41, wherein forming the number of sourcelines in a bottom of the trenches between rows of the pillars includes implanting a doped region in the bottom of the trenches between rows of the pillars.

50. The method of claim 41, wherein forming the first gate insulator of each floating gate transistor includes forming the first gate insulator to have a thickness of approximately 10 nanometers (nm).

51. The method of claim 41, wherein forming the number of vertical pillars to serve as floating gate transistors includes forming floating gate transistors which have a density equivalent to a floating gate transistor having a size of approximately 2.0 lithographic features squared (2F2).