1. Field of the Invention
This invention relates generally to memory circuits and integrated circuit processes for fabricating memory circuits. More particularly, this invention relates to nonvolatile memory circuits and integrated processes for fabricating nonvolatile memory circuits capable of operation at high temperatures with low leakage currents.
2. Description of Related Art
In applications for automotive and military environments, integrated electronic circuits must be capable of operating in a high-temperature environment. The integrated electronic circuits must operate with no failure or decrease in operational specifications at an upper temperature of +85° C. according to standard industry temperature specifications. In automotive or military applications, the upper temperature limit is specified to be +125° C.
Non-Volatile-Memory includes One-Time-Programmable Read Only Memory (OTP ROM), Electrically Eraseable Programmable Read Only Memory (EEPROM), and Flash nonvolatile memory as well known in the art. Programmable and Eraseable nonvolatile memory in the prior art includes circuits that must endure high voltages applied to their elements. Examples of the circuits are charge-pumps, column-decoders, row-decoders, page-buffers and the memory cell array. Each of these circuits are designed to supply the desired positive or negative high-voltage levels from a low-voltage power supply voltage source (VDD) to perform the desired on-chip program and erase operations without external high voltage power supply pins.
As is known in the art, the current through a junction between a P-type and an N-type semiconductor material is dependent upon temperature and is determined by the formula of the ideal diode law:
I=I
S(eVD/nVT−1)
Where:
where:
It can be shown that the reverse leakage current or junction leakage current increases exponentially with temperature increase. The junction in this instance is a parasitic bipolar junction between the high voltage NMOS transistor source and drain junctions and the common bulk of the P-substrate or the triple p-well formed within a deep N-well over the common bulk of the P-substrate in the triple P-well structure.
“Local Oxidation of Silicon for Isolation”, P. Smeys, chapter 2, PhD Thesis, 2000, Stanford University, found Jul. 6, 2011, www.stanford.edu/class/ee311/NOTES/isolationSmeys.pdf, found Jul. 6, 2011, provides an overview of isolation technologies, particularly conventional local oxidation of silicon (LOCOS) structure. Smeys further illustrates three current leakage paths; between two neighboring devices in the same well, junction to well leakage, and latch-up triggering.
“Contribution of gate induced drain leakage to overall leakage and yield loss in digital submicron VLSI circuits,” Semenov, et al., IEEE International Integrated Reliability Workshop Final Report, 2001, October, 2001, pp. 49-53, Found: www.ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=993916&isnumber=21443, Jul. 6, 2011, and “Impact of gate induced drain leakage on overall leakage of sub-micrometer CMOS VLSI circuits,” Semenov, et al., IEEE Transactions on Semiconductor Manufacturing, Vol. 15, No. 1, pp. 9-18, February 2002, found www.ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=983439&isnumber=21193, Found: Jul. 6, 2011, discuss the impact of gate induced drain leakage (GIDL) on the overall leakage of sub-micrometer VLSI circuits. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal-oxide-semiconductor (CMOS) devices for DRAM and/or EEPROM applications and scaled CMOS digital VLSI circuits. Experimental and simulation data of GIDL current as a function of 0.35-μm CMOS technology parameters and layout of CMOS standard cells is presented.
Study has revealed that, at a higher temperature environment, the higher leakage current happens at all edges of PN parasitic junctions rather than at the overlapping PN junction areas. The edge of the PN parasitic junctions between the substrate and the sources and drains of the high voltage transistors of nonvolatile memory devices at an edge of a LOCOS field oxide multiplies a junction leakage current effect. This can be reduced by process improvement but at the sacrifice of the lower junction breakdown voltage, which is against the required high voltage specifications for proper on-chip program and erase operation of the nonvolatile memory. The reason for the higher leakage current at the distributive edges of the parasitic bipolar junction between the high voltage NMOS transistor source and drain junctions and the common bulk of the P-substrate or the triple p-well is because the much higher P-type implant at edges for the commonly used technique to have the safe field isolation between any two adjacent HV NMOS devices. These critical temperature-sensitive edges of the devices of the parasitic bipolar junctions between the high voltage NMOS transistor source and drain junctions and the common bulk of the P-substrate or the triple P-well are distributed everywhere in the high voltage areas of the nonvolatile memory integrated circuits.
An object of this invention is to provide nonvolatile memory driver circuits for minimizing leakage current resulting from operating a nonvolatile memory at elevated temperatures.
Another object of this invention is to provide a method for fabricating a nonvolatile memory array for minimizing leakage current resulting from operating a nonvolatile memory at elevated temperatures.
To accomplish at least one of these objects, in some embodiments a method for fabricating a high temperature integrated circuit includes forming a drain/source diffusion of a first conductivity type separate from a substrate and an edge of a field isolation layer such that a concentration of impurity at the edge of the field isolation layer decreases a leakage occurring with high voltage and high temperature applied to the source/drain diffusion.
In various embodiments of a nonvolatile memory array driver circuit has multiple driver transistors. Each of the multiple driver transistors has its drain connected to a high voltage distribution conductor and its source connected to the nonvolatile memory array. A gate of each of the multiple driver transistors is connected to a select circuit for choosing at least one of the multiple driver transistors for activation. Multiple anti-leakage transistors are placed between adjacent driver transistors such that each of the anti-leakage transistors has a drain connected to the source of one driver transistor of the multiple driver transistors and a source connected to an adjacent driver transistor. A gate of the anti-leakage transistors is connected to a biasing voltage source to bias the anti-leakage transistor to prevent excess junction leakage current at elevated temperatures at the edges of the parasitic PN-junctions of the driver transistors.
A buried implant layer between the drain/source diffusion and the field isolation layer and the substrate to separate the drain/source diffusion from the substrate and the field isolation layer. A concentration of an implanted impurity species material of the drain/source is 1×1015 charges/cm3 and the concentration of the first buried implant region is 1×1014 charges/cm3 such that the lower concentration at the parasitic PN junction of the buried implant diffusion layer decreases the reverse leakage current at an elevated temperature.
In other embodiments, a nonvolatile memory array driver circuit has a high voltage blocking transistor having a drain connected to a driver transistor and to a terminal connected to the memory array. A source of the high voltage blocking transistor is connected to a low voltage switching circuit for connecting an output terminal of the nonvolatile memory array driver circuit to a reference voltage level. A gate of the high voltage blocking transistor is connected to a power supply voltage source to bias the high voltage blocking transistor to a voltage level no greater than the voltage level of the power supply voltage source less a threshold voltage level of the high voltage blocking transistor when a high voltage level is applied to the output terminal. The nonvolatile memory array driver circuit further has two anti-leakage transistors connected such that a source of the first anti-leakage transistor is connected to a drain of the high voltage blocking transistor and a drain of the second anti-leakage transistor is connected to a source of the high voltage blocking transistor. A drain of the first anti-leakage transistor and a source of the second anti-leakage transistor are floating. The gates of the first and second anti-leakage transistors are connected to the power supply voltage source. The two anti-leakage transistors prevent excess junction leakage current at elevated temperatures at the edges of the parasitic PN-junctions of the driver transistors.
The memory array driver circuit is a charge-pump, column-decoder, row-decoder, page-buffer or the memory cell array that requires a high voltage for programming or erasing the nonvolatile memory circuit.
In still other embodiments, the nonvolatile memory cell includes a select transistor with a drain region of a first conductivity type implanted in a substrate and connected to communicate to a bit line. The drain region is placed above a buried implant region that prevents junction leakage current at elevated temperatures at the edges of a parasitic PN-junction of the drain region in proximity to field isolation regions bordering the nonvolatile memory cell.
In various embodiments, the nonvolatile memory cell includes a source region of the first conductivity type implanted in a substrate and connected to communicate to a source line that is in parallel with the bit line. The source region is above by a second buried implant that prevents excess junction leakage current at elevated temperatures at the edges of a parasitic PN-junction of the source region in proximity to field isolation regions bordering the nonvolatile memory cell.
The concentration of the implanted impurity species material of the drain of the select transistor is 1×1015 charges/cm3 and the concentration of the first buried implant region is 1×1014 charges/cm3 such that the lower concentration at the parasitic PN junction of the buried implant diffusion layer decreases the reverse leakage current at an elevated temperature. Similarly, the concentration of an implanted impurity species material of the source of the FLOTOX EEPROM transistor is 1×1015 charges/cm3 and the concentration of the second buried implant region is 1×1014 charges/cm3 such that the lower concentration at the parasitic PN junction of the second buried implant diffusion layer decreases the reverse leakage current at an elevated temperature.
In some embodiments, a method for fabricating a nonvolatile memory cell includes forming a drain region of a first conductivity type implanted in a substrate. The drain region is connected to communicate with a bit line. Prior to forming the drain region a buried implant is diffused into the substrate beneath the location of the drain region to prevent excess junction leakage current at elevated temperatures at the edges of a parasitic PN-junction of the drain region in proximity to field isolation regions bordering the nonvolatile memory cell.
In various embodiments, the method for fabricating the nonvolatile memory cell includes implanting a source region of the first conductivity type in the substrate. The source region connected to communicate to a source line that is in parallel with the bit line. Prior to forming the source region a second buried implant is diffused into the substrate beneath the location of the source region to prevent excess junction leakage current at elevated temperatures at the edges of a parasitic PN-junction of the drain region in proximity to field isolation regions bordering the nonvolatile memory cell.
a illustrates the schematic circuit for a 2-transistor, FLOTOX EEPROM cell of the prior art.
b and 1c are respectively a top view and a cross sectional view that illustrate the physical layout for the two-transistor FLOTOX EEPROM cell of
d is a cross sectional view of the drain of the select transistor of the FLOTOX EEPROM cell of
a is a schematic diagram of a two-byte section of an array of FLOTOX EEPROM cells of the prior art.
b is a diagram of a top view of the two-byte section of the array of FLOTOX EEPROM cells of
c is a diagram illustrating a cross section of control gate biasing select transistors of the two-byte section of the array of FLOTOX EEPROM cells of
a and 4b are respectively a top view and a cross sectional view that illustrate the physical layout for various embodiments of a two-transistor FLOTOX EEPROM cell as formed in a substrate embodying the principles of the present invention.
c is a cross sectional view of the drain of the select transistor for some embodiments of the FLOTOX EEPROM cell of
a is a schematic diagram of various embodiments of a two-byte section of an array of FLOTOX EEPROM cells embodying the principles of the present invention.
b is a diagram of a top view of the various embodiments of the two-byte section of the array of FLOTOX EEPROM cells of
c is a diagram illustrating a cross section of the various embodiments of control gate biasing select transistors with the anti-leakage transistors of the two-byte section portion of the array of FLOTOX EEPROM cells of
a and 6b are respectively a top view and a cross sectional view that illustrate the physical layout for various embodiments of a two-transistor FLOTOX EEPROM cell as formed in a substrate embodying the principles of the present invention.
c is a cross sectional view of the drain of the select transistor for the embodiments of the FLOTOX EEPROM cell of
d is a cross sectional view of the source of the FLOTOX EEPROM transistor for the embodiments of the FLOTOX EEPROM cell of
a is a schematic diagram of various embodiments of a two-byte section of an array of FLOTOX EEPROM cells embodying the principles of the present invention.
b is a diagram of a top view of the various embodiments of the two-byte section of the array of FLOTOX EEPROM cells of
a illustrates the schematic circuit for a 2-transistor FLOTOX EEPROM cell of the prior art. The EEPROM cell of the prior art includes of two transistors N1 and N2. The select transistor, N1 is a polycrystalline silicon (polysilicon) NMOS device with its gate connected to a select gate signal SG. The source of the select transistor N1 is connected to the drain of the floating gate tunnel oxide (FLOTOX) EEPROM transistor N2. The FLOTOX EEPROM transistor N2 is a double polysilicon floating gate device. A first layer of polysilicon is the floating-gate FG that is used to store the charges representing the binary “0” and binary “1” of the stored data. The second layer of the polysilicon is a control gate CG that is connected to the word line WL. The drain of the select transistor N1 is connected to a vertical metal bit line BL. The source of the EEPROM transistor N2 is connected to a common horizontal implanted source line SL.
b and 1c illustrate the physical layout for the two-transistor FLOTOX EEPROM cell of
The control gate CG is connected to a control gate biasing voltage line CGB that provides the necessary voltages to the control gate CG for programming, erasing, and reading the data from the FLOTOX EEPROM cell.
d is a cross sectional view of the drain of the select gate of the FLOTOX EEPROM cell of
a is a schematic diagram of a portion of an array of FLOTOX EEPROM cells of the prior art.
The gates of the select transistors N0a, N1a, . . . , N7a and N0d, N1d, . . . , N7d are formed of the first layer polysilicon 100a and 100b that are aligned to form the word lines WL0 and WL1. The control gates of the FLOTOX EEPROM transistors N0b, N1b, . . . , N7b and N0c, N1c, . . . , N7c are formed of the second layer polysilicon 105a and 105b that are similarly aligned to form the control gate biasing lines CGB0 and CBG1.
The global bit line GBL provides the control gate biasing voltage levels for the control gates of the FLOTOX EEPROM transistors N0b, N1b, . . . , N7b and N0c, N1c, . . . , N7c for programming, erasing, and reading. The control gate biasing voltage levels are transferred from the global bit line GBL to the control gate biasing lines CGB0 and CBG1 through the control gate biasing select transistors N10 and N11. The drains 115a and 115b of the control gate biasing select transistors N10 and N11 are is respectively connected to the global bit line GBL. The sources 120a and 120b of the control gate biasing select transistors N10 and N11 are respectively connected to the control gate biasing lines CGB0 and CBG1. The control gates 125a and 125b are the first layer polysilicon 100a and 110b that forms the word lines WL0 and W11.
The control gate biasing select transistors N10 and N11 are fabricated as either the single layer polysilicon native NMOS transistor with threshold voltage level Vt of +0.3V or a single layer polysilicon enhancement NMOS transistor with a threshold voltage level Vt of around +0.7V. Lower threshold voltage level of the native control gate biasing select transistors N10 and N11 is preferable to the higher threshold voltage level of an enhancement device but at the cost of a bigger layout area in EEPROM byte circuit layout design of the prior art.
The control gate biasing select transistors N10 and N11 are separated by a field oxide isolation layer 130. As described in Smeys and Semenov, the leakage current at high temperatures occurs at the edges of the PN junction of the substrate P-sub and the N+ implants 120a and 120b at the boundary of the field oxide isolation layer 100.
The high voltage NMOS transistors N50 is used to block high voltage applied to the word line WLn from being applied to the drains regions of the low voltage NMOS transistor N52 and the high voltage NMOS transistor N51 for area reduction. In addition, the gate of the high voltage NMOS transistor N50 is connected to the power supply voltage source VDD. The breakdown voltages (BVDS) of the drain region of the high voltage NMOS transistor N50 and the high voltage PMOS transistors P50 connected to the word line WLn is increased by approximately 1-2V. The permits a higher program and erase high voltage level for faster write time.
The required voltages applied to the word line WLn during Program and Erase operations is +16V typically. During the high voltage Program and Erase operations, the voltage level of the signal applied to the node XT and signal applied from the terminal VPX to the N-well bulk of the high voltage PMOS transistor P50 have a magnitude of approximately +16V. Similarly, the voltage level applied to the node XDB swings between approximately +16V and the substrate voltage source VSS during Program and Erase operation. However, the node XDB varies between the power supply voltage source VDD and VSS during Read operation. The voltage applied to the node XTB varies between the power supply voltage source VDD and the substrate voltage source VSS in all operations. With the gate of the high voltage NMOS transistor N50 being connected to the power supply voltage source VDD in all operations, the highest voltage level at the drains of the high voltage NMOS transistor N51 and the low voltage NMOS transistor N52 is kept below the voltage level of the power supply voltage source VDD less the threshold voltage level of the high voltage NMOS transistor N50(VDD−Vt(N50)) in the program, erase and read operations.
In a low voltage read operation, the signals of applied to the nodes XT and VPX have a magnitude equal to the power supply voltage VDD. The drain region of the high voltage NMOS transistor N50 and the high voltage PMOS transistors P50 connected to the word line WLn has a parasitic high voltage PN junction areas and PN junction edges in the layout that result in a larger junction leakage current at the edges in higher temperature operations. As a result, this last stage of a high voltage row-decoder circuit of the prior art is prone to failure in higher temperature operation.
The source regions 120a and 120b of the control gate biasing select transistors N10 and N11, the drain regions 5 of the select transistors N0a, N1a, . . . , N7a and N0d, N1d, . . . , N7d and the drain of the high voltage NMOS blocking transistor N50 are fabricated as high voltage N-type regions that aligned with field oxide isolation layers 130 of
The impurity concentration at the boundary of the field oxide isolation layers and the P-type substrate P-sub is approximately three fold that of the P-type substrate P-sub. The total leakage at higher temperature is more dominated by the edge boundary at the field oxide isolation layer, rather than other areas of the drain/source regions. The present invention effectively reduces the impurity concentration of PN junction structures at an edge boundary of the field oxide isolation layers to reduce the leakage current. This accomplished by placing a buried implant layer BN+ to separate the drain regions of the select transistors N0a, N1a, . . . , N7a and N0d, N1d, . . . , N7d from the P-type substrate P-sub. The field oxide isolation layer 130 between the source regions 120a and 120b of control gate biasing select transistors N10 and N11 is eliminated and a high voltage NMOS transistor N12 is placed between them. For the high voltage NMOS blocking transistor N50 in the word line driver, two transistors are formed in series with the high voltage NMOS blocking transistor N50 to reduce the impurity concentration of PN junction structures at the boundary of the field oxide isolation layers to reduce the leakage current.
a and 4b are respectively a top view and a cross sectional view that illustrate the physical layout for the two-transistor FLOTOX EEPROM cell as formed in a substrate P-sub embodying the principles of the present invention.
a is a schematic diagram of a two-byte section of an array of FLOTOX EEPROM cells embodying the principles of the present invention.
The array of the FLOTOX EEPROM cells MC10, MC11, . . . , MC17 and MC20, MC21, . . . , MC27 embodying the principles of the present invention are structured and operate essentially identically to those as shown in
The buried implant diffusion layers 200, 210a, 210b, 215a, and 215b prevent the excess leakage current from increasing significantly when the drain regions 5 and 210a and 210b and the source regions 215a and 215b are connected to a high voltage and the operating temperature is elevated. As described above, the reverse saturation current is inversely proportional to the carrier donor and acceptor concentrations at the n side and p side of a PN junction. The concentration of the N+ material of the drain 5 of the select transistor N1 is 1×1015 electrons/cm3 and the concentration of the for the buried implant diffusion layers BN+ 200, 210a, 210b, 215a, and 215b is 1×1014 electrons/cm3. The lower concentration at the PN junction of the buried implant diffusion layer 200 means that the reverse leakage current at an elevated temperature is decreased.
a and 6b are respectively a top view and a cross sectional view that illustrate the physical layout for some embodiments of a two-transistor FLOTOX EEPROM cell as formed in a substrate P-sub embodying the principles of the present invention.
The structure of the FLOTOX EEPROM cell as shown is essentially identical to that of
A buried implant diffusion layer 310 is implanted such that it is placed to contain the source region 300 of the FLOTOX EEPROM transistor N2 in a fashion similar to the buried implant diffusion layer 200 that is implanted beneath the drain 5 of the select transistor N1. As with the buried implant diffusion layer 200, the field oxide isolation layers 55 are eliminated such that in an array of the FLOTOX EEPROM cells MC10, MC11, . . . , MC17 and MC20, MC21, . . . , MC27 embodying the principles of the present invention, the buried implant diffusion layers 310 of adjacent FLOTOX EEPROM cells MC10, MC11, . . . , MC17 and MC20, MC21, . . . , MC27 are connected. In fact in practice, a single masking feature will define the buried implant diffusion layers 310. The buried implant diffusion layer 310 prevents the excess leakage current from increasing significantly when the source region 300 is connected to a high voltage and the operating temperature is elevated. As described above, the reverse saturation current is inversely proportional to the carrier donor and acceptor concentrations at the n side and p side of a PN junction. The concentration of the N+ material of the drain 5 of the select transistor N1 1×1015 electrons/cm3 and the concentration of the for the buried implant diffusion layer BN+ 200 is 1×1014 electrons/cm3. The lower concentration at the PN junction of the buried implant diffusion layer 310 means that the reverse leakage current at an elevated temperature is decreased.
a is a schematic diagram of a two-byte section of an array of FLOTOX EEPROM cells MC10, MC11, . . . , MC17 and MC20, MC21, . . . , MC27 embodying the principles of the present invention.
The array of the FLOTOX EEPROM cells MC10, MC11, . . . , MC17 and MC20, MC21, . . . , MC27 embodying the principles of the present invention are structured and operate essentially identically to those as shown in
The source of the 300 of the FLOTOX EEPROM transistor N2, as shown in
The buried implant diffusion layers 200, 210a, 210b, 215a, and 215b the are as described in
The basic structure and operation of the word line driver circuit of a row-decoder circuit of
The addition of the high voltage NMOS transistor N51 and the low voltage NMOS transistor N52 allows the layout area to remain almost the same with less penalty in die size while achieving performance enhancement in higher temperature operation. The PN junction area and PN junction edges of the drain/source region of the high voltage NMOS transistors N50 and N51 connected to the word line WLn is greatly reduced such that the circuit is able to operate at higher temperature environment.
The addition of the high voltage NMOS transistor N53a and the low voltage NMOS transistor N53b takes advantage of the available layout room in the row decoder to reduce the parasitic bipolar PN junction area and PN junction edges can be achieved for higher temperature operation of the present invention. Since, the drain region of the high voltage NMOS transistor N50 and the high voltage PMOS transistors P50 connected to the word line WLn have the only high voltage PN junction area and PN junction edges within the row decoder circuit, decreasing of the carrier concentrations at the parasitic bipolar PN junction area and PN junction edges is accomplished with the addition of the high voltage NMOS transistor N53a and the low voltage NMOS transistor N53b.
Buried implant layers are diffused (Box 445) into the substrate for high temperature operation of the high voltage transistors such as the FLOTOX EEPROM transistors and the select gate transistor of the FLOTOX EEPROM cells. The concentration of the for the buried implant diffusion layers is 1×1014 electrons/cm3. This lower concentration at the PN junction of the buried implant diffusion layers means that a reverse leakage current at an elevated temperature is decreased when compared to the normal concentration of the source/drain regions of the high voltage FLOTOX EEPROM transistors and the select gate transistor of the FLOTOX EEPROM cells and other high voltage transistors in the supporting driver circuits of the array of FLOTOX EEPROM cells. This concentration of the N+ material of the drain/source regions of the select transistor and the source of the FLOTOX EEPROM transistor is 1×1015 electrons/cm3. This elevated concentration would cause a larger reverse leakage current at an elevated temperature if not for the buried layer embodying the principles of this invention. In the case of a P-type substrate, the donor species are Boron, arsenic, or preferably phosphorus.
In the FLOTOX EEPROM cells of
The N-type sources and drains are implanted (Box 450) with a donor impurity to form the sources and drains of the FLOTOX EEPROM transistors and the select gate transistor of the FLOTOX EEPROM cells as well as the NMOS and PMOS transistors of the supporting circuits. An inter-level dielectric layer is deposited (Box 455) on the surface of the substrate and etched to make opening for metal contacts to the drain/source regions. The metal contacts are formed (Box 460). Metal layers are deposited and etched (Box 465) with inter-level dielectric layers between each metal layer. The etched metal layers form the interconnections such as the bit lines BL0, BL1, . . . , BL7 of
The substrate as described above is a p-type substrate with n-type drains, sources, and buried implant layers may also be n-type substrate with p-type drains, sources, and buried implant layers and still be in keeping with the principles of this invention. The invention as shown with a FLOTOX EEPROM array, other nonvolatile memory arrays or even other high voltage applications may employ the buried implant layers for minimizing leakage current resulting from operating a nonvolatile memory at elevated temperatures and be in keeping with embodying the principles of this invention. While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
This application claims priority under 35 U.S.C. §119 to U.S. Provisional Patent Application U.S. Provisional Patent Application Ser. No. 61/400,113, filed on Jul. 21, 2010, assigned to the same assignee as the present invention, and incorporated herein by reference in its entirety.
Number | Date | Country | |
---|---|---|---|
61400113 | Jul 2010 | US |