Claims
- 1. A multi-bit semiconductor memory device having a plurality of output buffer circuits, each of said output buffer circuits comprising:
- a data output terminal;
- an output switching means for pulling up a potential of said data output terminal to a HIGH level;
- a charge discharging switching means for pulling down the potential of said data output terminal to a LOW level;
- driving means for driving said output switching means to respond to read-out data; and
- delay means connected between a drive terminal connected with said output switching means and said charge discharging switching means;
- wherein said charge discharging switching means carries out a pull-down operation in response to an output of said delay means, each said delay means of said output buffer circuits provides different delay times from each other, so that the timings of pull-down operations in said output buffer circuits are shifted with each other.
- 2. A device according to claim 1, wherein said output buffer circuits comprise complementary MOS transistor inverters.
- 3. A device according to claim 1, wherein said output buffer circuits comprise push-pull buffer circuits.
Priority Claims (2)
Number |
Date |
Country |
Kind |
60-49350 |
Mar 1985 |
JPX |
|
60-54666 |
Mar 1985 |
JPX |
|
Parent Case Info
This application is a continuation of application Ser. No. 839,260 filed Mar. 13, 1986, now abandoned.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
4532613 |
Takemae et al. |
Jul 1985 |
|
4583204 |
Takemae et al. |
Apr 1986 |
|
4661928 |
Yasuoka |
Apr 1987 |
|
Continuations (1)
|
Number |
Date |
Country |
Parent |
839260 |
Mar 1986 |
|