Patent Application
20180061793
This application claims the priority benefit of Taiwan application serial no. 105128012, filed on Aug. 31, 2016. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The present invention generally relates to a semiconductor structure and a manufacturing method thereof. More particularly, the present invention relates to a semiconductor package structure and a manufacturing method thereof
As technology advances, all kinds of electronic devices are developed towards miniaturization and multiple functions. Hence, in order for chips in electronic device to be able to transmit or receive more signals, contacts electrically connected between chips and circuit boards are also developed towards high density. In the prior art, a chip and a substrate are electrically connected mostly by disposing an anisotropic conductive film (ACF) between contacts of the chip and conductive structures of the substrate. The contacts of the chip and the conductive structures of the substrate both face the ACF. Afterwards, the contact of the chip, the ACF and the conductive structure of the substrate are laminated so that each of the contacts of the chip is electrically connected to each conductive structure of the substrate through conductive particles in the ACF.
In addition, in the manufacturing process of such package, a thermal lamination process need to be firstly performed on an ACF to attach the ACF to a bonding region of the substrate, and the chip is then laminated on the ACF under a high temperature, such that the contacts of the chip are electrically connected to the conductive structures of the substrate through conductive particles in the ACF. The above-mentioned two steps need to be performed separately. As such, the complexity of the manufacturing process increases and the applicable field is limited, so as to increase the process time, which leads to decrease of productivity. Moreover, an impedance of the ACF may become unstable after the ACF being pressed repeatedly and/or the environment thereof changes, which leads to decrease of electrical performance of the package structure. Furthermore, the ACF is expensive, so using the ACF also increases production cost.
Accordingly, the present invention is directed to a package structure and a manufacturing method thereof, which simplify the manufacturing process and improve electrical performance of the package structure.
The present invention provides a manufacturing method of a package structure, and the manufacturing method includes the following steps. A substrate is provided, wherein the substrate includes a plurality of solder pads. A patterned solder resist layer is formed on the substrate, wherein the patterned solder resist layer includes a plurality of stepped openings exposing the solder pads respectively. A polymer gel is disposed on a top surface of the patterned solder resist layer, wherein the polymer gel at least surrounds a disposing region of the solder pads and disposed between adjacent two of the solder pads. A plurality of solders are disposed on the solder pads respectively, wherein the solders are located in the stepped openings respectively. A chip is disposed on the substrate, wherein the chip includes an active surface and a plurality of bond pads located on the active surface and the bond pads are connected to the solder pads through the solders. A reflow process is performed on the solders, such that the polymer gel is filled between a top surface of the patterned solder resist layer and the active surface.
The present invention further provides a package structure, and the package structure includes a substrate, a patterned solder resist layer, a plurality of solders, a chip and a polymer gel. The substrate includes a plurality of solder pads. The patterned solder resist layer is disposed on the substrate and includes a plurality of stepped openings. The stepped openings expose the solder pads respectively. The solders are disposed on the solder pads and located in the stepped openings respectively. The chip is disposed on the substrate and includes an active surface and a plurality of bond pads. The bond pads are disposed on the active surface and connected to the solder pads by the solders. The polymer gel fills between a top surface of the patterned solder resist layer and the active surface. The polymer gel at least surrounds a disposing region of the solders and fills between two adjacent solders.
Based on the above-mentioned description, in the disclosure, the polymer gel is disposed on the top surface of the patterned solder resist layer having the stepped openings, wherein the stepped openings expose the solder pads of the substrate respectively. Moreover, the polymer gel surrounds the disposing region of the solder pads and is disposed between adjacent two of the solder pads. Then, the chip is disposed on the substrate through the solders. Accordingly, the solders would shrink after being reflowed and cured, so as to compress the polymer gel, so that the polymer gel can completely fill the gap between the top surface of the patterned solder resist layer and the active surface of the chip to achieve a sealing effect and prevent moisture from external environment to permeate into the package structure. Therefore, in the disclosure, a sealing structure for the package structure can be simultaneously formed by one mounting process, such that the conventional ACF process can be replaced, so as to simplify the manufacturing process of the package structure and reduce the production cost. Moreover, since the chip is disposed on the substrate by surface-mount technology, an impedance thereof is more stable, compared to ACF. Therefore, the disclosure may also enhance electrical performance of the package structure.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The terms used herein such as “above”, “below”, “front”, “back”, “left” and “right” are for the purpose of describing directions in the figures only and are not intended to be limiting of the invention. Moreover, in the following embodiments, the same or similar reference numbers denote the same or like components.
For example, the step of forming the patterned solder resist layer 120 on the substrate 110 may include the following steps. Firstly, a first solder resist layer 124a is formed on the substrate 110. In the present embodiment, the first solder resist layer 124a may, for example, completely cover a top surface of the substrate 110 and cover the solder pads 112. Next, a first patterning process is performed on the first solder resist layer 124a. The first patterning process may be, for example, a photolithography process. In detail, the first patterning process may include disposing a patterned photoresist layer 125 having a plurality of openings on the first solder resist layer 124a as shown in
Next, a second solder resist layer 126a as shown in
Next, in one embodiment, a pre-curing process may be performed on the polymer gel 130 to make the polymer gel 130 in a semi-cured state. To be more specific, the pre-curing process may include, for example, performing a heating process on the polymer gel 130, wherein the heating temperature of the heating process substantially ranges from 50° C. to 80° C. Certainly, the present embodiment is merely for illustration and the disclosure is not limited thereto.
Referring to
Next, a reflow process is performed on the solders 140 to fix the chip 150 on the substrate 110. After being reflowed, the solders 140 completely fill the stepped openings 122 of the patterned solder resist layer 120. At the time, the solders 140 would shrink after being reflowed and cured, so as to compress the polymer gel 130, so that the polymer gel 130 completely fill the gap between the top surface of the patterned solder resist layer 120 and the active surface 152 to achieve a sealing effect and prevent moisture from external environment to permeate into the package structure 100. As such, the manufacture of the package structure 100 as shown in
In structure, the package structure 100 formed by the above-mentioned manufacturing method may include a substrate 110, a patterned solder resist layer 120, a plurality of solders 140, a chip 150 and a polymer gel 130. The substrate 110 includes a plurality of solder pads 112. The patterned solder resist layer 120 is disposed on the substrate 110 and includes a plurality of stepped openings 122. The stepped openings 122 expose the solder pads 112 respectively. In detail, the patterned solder resist layer 120 includes the first patterned solder resist layer 124 and the second patterned solder resist layer 122 as shown in
Moreover, the solders 140 are disposed on the solder pads 112 and located in the stepped openings 122 respectively. The chip 150 is disposed on the substrate 110 and includes an active surface 152 and a plurality of bond pads 154. The bond pads 154 are disposed on the active surface 152 and connected to the solder pads 112 by the solders 140. The polymer gel 130 fills between a top surface of the patterned solder resist layer 120 and the active surface 152 of the chip 150, wherein the polymer gel 130 at least surrounds a disposing region of the solders 140 and fills between two of the solders 140, which are adjacent to each other.
In sum, in the disclosure, the polymer gel is disposed on the top surface of the patterned solder resist layer having the stepped openings, wherein the stepped openings expose the solder pads of the substrate respectively. Moreover, the polymer gel surrounds the disposing region of the solder pads and is disposed between adjacent two of the solder pads. Then, the chip is disposed on the substrate through the solders. Accordingly, the solders would shrink after being reflowed and cured, so as to compress the polymer gel, so that the polymer gel can completely fill the gap between the top surface of the patterned solder resist layer and the active surface of the chip to achieve a sealing effect and prevent moisture from external environment to permeate into the package structure.
Therefore, in the disclosure, a sealing structure for the package structure can be simultaneously formed by one mounting process, such that the conventional ACF process can be replaced, so as to simplify the manufacturing process of the package structure and reduce the production cost. Moreover, since the chip is disposed on the substrate by surface-mount technology, an impedance thereof is more stable, compared to ACF. Therefore, the disclosure may also enhance electrical performance of the package structure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 105128012 | Aug 2016 | TW | national |
