Patent Grant
12068210
The present invention relates to a package substrate and a method of manufacturing the same.
Semiconductor package substrates are used to electrically connect semiconductor chips with motherboards. Semiconductor package substrates also have a role of bridging differences in thermal expansion coefficient between a semiconductor chip and a printed wiring board mounted with a semiconductor package to improve joint reliability in system implementation. Due to such a role, semiconductor package substrates are also referred to as interposer substrates or the like. In a semiconductor package substrate, layers having different wiring widths and pitches allow conversion between the wiring width and the wiring pitch of a semiconductor chip and the wiring width and the wiring pitch of a motherboard to establish electrical connection.
In recent years, not only a conventional SoC (System on a Chip) but also a SiP (System in Package) which implements a large-scale system in a single package has been used to develop a high-performance system in a short period of time. In a SiP, for example, a CPU and a GPU, and a plurality of semiconductor chips such as large-capacity memories are arranged next to each other on a single package substrate, or chips are stacked and arranged in a three-dimensional manner.
However, core substrates used for recent package substrates include core substrates made of a material that is brittle despite having good electrical properties (brittle material). It is known that a wiring substrate is produced by laminating, on a core substrate, two or more resin layers and wiring layers having a different linear expansion coefficient from the core substrate; thus, during temperature change, the difference in the linear expansion coefficient causes a difference in expansion amount between the resin layers, the wiring layers, and the core substrate, leading to generation of stress. When the core substrate is made of a brittle material that is easily broken, the stress may cause breakage of the core substrate (e.g., Non Patent Literature 1).
As a method to prevent such breakage of the core substrate, a structure has been proposed in which a package substrate includes a core substrate, an insulating layer formed on one surface or both surfaces of the core substrate, and one or more wiring layers formed on the insulating layer and/or embedded in the insulating layer, and an outer peripheral portion of the surface of the package substrate on which the insulating layer is formed has an exposed portion at which the core substrate is exposed (e.g., Patent Literature 1). The structure having such an exposed portion can prevent stress from occurring in a cross section of the core substrate, thereby preventing damage starting from the cross section of the core substrate.
However, such a method cannot avoid stress being applied to the surface of the core substrate, and may cause breakage starting from the surface of the core substrate.
[NPL 1] “Empirical Investigations on Die Edge Defects Reductions in Die Singulation Processes for Glass-Panel Based Interposers for Advanced Packaging”, Frank Wei et al., 2015 Electronic Components & Technology Conference (2015).
[PTL 1] JP 2018-116963 A.
Thus, an object of the present invention is to provide a package substrate capable of preventing damage (e.g., breakage) affecting the reliability from starting from a surface of a core substrate made of a brittle material due to temperature change or the like, and a method of manufacturing the same.
In order to solve the above problem, intensive studies have been performed on the prevention of breakage of a core substrate, in particular, breakage starting from a surface of the core substrate. As a result, it has been found that the following technique is effective.
An aspect of the present invention is a package substrate including a core substrate made of a brittle material, at least one insulating layer formed on one surface or both surfaces of the core substrate, and one or more wiring layers formed on the insulating layer and/or in the insulating layer, the core substrate being exposed outside an outer peripheral portion of the insulating layer, the insulating layer being chamfered.
Another aspect of the present invention is a method of manufacturing a package substrate, the package substrate including a core substrate made of a brittle material, at least one insulating layer formed on one surface or both surfaces of the core substrate, and one or more wiring layers formed on the insulating layer and/or in the insulating layer, the core substrate being exposed outside an outer peripheral portion of the insulating layer, the method including a step of chamfering the insulating layer.
The package substrate and the manufacturing method according to the present invention provide an improved and even highly reliable package substrate that prevents breakage of a core substrate.
Embodiments of the present invention of will be described below with reference to the drawings. In the following description of the drawings to be referred, components or functions identical with or similar to each other are given the same or similar reference signs, unless there is a reason not to. It should be noted that the drawings are only schematically illustrated, and thus the relationship between thickness and two-dimensional size of the components, and the thickness ratio between the layers, are not to scale. Therefore, specific thicknesses and dimensions should be understood in view of the following description. As a matter of course, dimensional relationships or ratios may be different between the drawings.
Further, the embodiments described below are merely examples of configurations for embodying the technical idea of the present invention. The technical idea of the present invention does not limit the materials, shapes, structures, arrangements, and the like of the components to those described below. The technical idea of the present invention can be modified variously within the technical scope defined by the claims. The present invention is not limited to the following embodiments within the scope not departing from the spirit of the present invention.
In any group of successive numerical value ranges described in the present specification, the upper limit value or lower limit value of one numerical value range may be replaced with the upper limit value or lower limit value of another numerical value range. In the numerical value ranges described in the present specification, the upper limit values or lower limit values of the numerical value ranges may be replaced with values shown in examples. The configuration according to a certain embodiment may be applied to other embodiments.
A package substrate of the present invention is a package substrate obtained by dicing a wiring substrate composed of a laminate (buildup layer) in which an insulating layer and a wiring layer are laminated. Herein, the term “package substrate” refers to a laminate obtained by dicing a wiring substrate. Further, the term “wiring substrate” refers to connected package substrates before being diced.
(Package Substrate)
As shown in
In the package substrate of the present invention, the structures of the insulating layer 21 and the wiring layer 31 are not limited to those shown in
The insulating layer 21 may be laminated on one of the surfaces (one surface) of the core substrate 11 in the thickness direction. That is, the insulating layer 21 is formed on one surface or both surfaces of the core substrate 11. The insulating layer 21 may be formed of a single layer or a plurality of layers.
The wiring layer 31 may be formed on the insulating layer 21 or in the insulating layer 21. That is, the wiring layer 31 is formed on the insulating layer 21 and/or embedded in the insulating layer 21. The wiring layer 31 may be formed of a single layer or a plurality of layers.
(Core Substrate)
The core substrate 11 can be made of a material that improves the electrical properties of the package substrate 100. The core substrate 11 may be made of, for example, a brittle material such as a glass substrate, silicon substrate, ceramic substrate, plastic plate, or plastic tape. Among these, a glass substrate is preferable as the material of the core substrate 11.
The glass substrate used for the core substrate 11 may be made of, for example, a soda-lime glass or aluminosilicate glass. The glass substrate used for the core substrate 11 may be surface-treated by a method generally used in the art. For example, the glass substrate may be roughened, or surface-treated with hydrofluoric acid or silicon. The glass substrate used for the core substrate 11 may have a primer layer (not shown) formed on the surface of the glass substrate. The thickness of the core substrate 11 is not particularly limited, but is preferably 50 μm or more and 800 μm or less.
In the package substrate 100, the surface of the core substrate 11 on which the insulating layer 21 is provided has an exposed portion 110 at which the core substrate 11 is exposed. As shown in
(Wiring Layer)
The wiring layer 31 is made of chromium, copper, silver, tin, gold, tungsten, an alloy of these metals, a conductive resin, or the like. The wiring layer 31 can be formed by using a method in which thick plating is performed, followed by a subtractive process or a semi-additive process to form a wiring, or by using a method such as an ink-jet method, screen printing, or gravure offset printing. The wiring layer 31 is preferably formed by the semi-additive method. The wiring layer 31 only needs to have a thickness, for example, in the range of 1 μm or more and 100 μm or less.
(Insulating Layer)
The insulating layer 21 can be made of an epoxy resin material, an epoxy acrylate resin, a polyimide resin, a liquid crystalline polymer resin, or the like. These insulating materials may contain a filler. The insulating material for forming the insulating layer 21 is preferably an epoxy-containing resin having a linear expansion coefficient in the range of 7 ppm/K or more and 130 ppm/K or less, which is easily available in general. The insulating material may be a liquid material or a film material. When the insulating material is a liquid, the insulating layer 21 can be formed by a method generally used in the art, such as spin coating, die coating, curtain coating, roll coating, doctor blading, or screen printing. When the insulating material is a film, the insulating layer 21 can be formed, for example, by vacuum lamination or roll lamination. The insulating layer 21 formed as described above may be cured by heating or light irradiation. The insulating layer 21 only needs to have a thickness in the range of 1 μm or more and 200 μm or less.
In the package substrate 100 according to the present embodiment, an edge portion of the insulating layer 21 is chamfered. A chamfered region of the insulating layer 21 is referred to as a chamfered portion. Thus, the insulating layer 21 is provided with a chamfered portion 22. The chamfered portion refers to, for example, a structure in which part of the edge portion of the insulating layer 21 is removed as observed in the cross-sectional direction shown in
In the package substrate 100, as shown in
In a process of manufacturing the package substrate 100 according to the present embodiment, a volume of the portion of the insulating layer 21 chamfered to form the chamfered portion 22 is preferably 30% or more of a volume of a region of the insulating layer 21 in which a distance W parallel to a surface of the insulating layer 21 from an edge of the insulating layer 21 before being chamfered toward a center portion of the insulating layer 21 is not more than the thickness F of the insulating layer 21 (a region in which distance W≤thickness F).
As shown in
The advantage of the structure of the package substrate 100 of the present embodiment is that the edge portion of the insulating layer 21 is chamfered, and the chamfered portion 22 may have various shapes.
The shape of the chamfered portion 22 may be, for example, a shape obtained by chamfering the insulating layer 21 in a linear shape (a linear shape) as shown in
As shown in
In the present embodiment, when the chamfered portion 22 has a linear shape (see
The second portion 211 of the insulating layer 21 is a portion of the insulating layer 21 corresponding to a portion having a thickness H in cross section. The thickness H is a thickness of the remaining portion obtained by removing the chamfered portion 22 having the height G from the insulating layer 21 having the thickness F (thickness H=thickness F−height G). That is, the portion of the insulating layer 21 other than the first portion 210 corresponds to the second portion 211. As shown in
The insulating layer 21 has a structure in which the first portion 210 and the second portion 211 are stacked. For example, in the insulating layer 21 shown in
The first portion 210 and the second portion 211 of the insulating layer 21 may be formed as a single layer, that is, may be integrally formed. Alternatively, the first portion 210 and the second portion 211 of the insulating layer 21 may be formed as separate layers. When the first portion 210 and the second portion 211 are separate layers, each of the first portion 210 and the second portion 211 may be a single layer, or may have a structure in which a plurality of layers are laminated.
In the package substrate 100 according to the present embodiment, the thickness H, which is the thickness of the second portion 211 of the insulating layer 21, may be in the range of 1 μm or more and 50 μm or less. The thickness H of the second portion 211 is preferably in the range of 2.5 μm or more and 30 μm or less, and more preferably in the range of 5 μm or more and 15 μm or less. For example, if the thickness H of the second portion 211 is less than 1 μm, cracks may occur in the resin constituting the insulating layer 21, and the cracks may propagate to the core substrate 11. For example, if the thickness H of the second portion 211 is 0 μm or less, a blade used for the chamfering processing may come into contact with the core substrate 11 and causes cracking or damage in the core substrate 11 during chamfering processing in which the chamfered portion 22 of the insulating layer 21 is formed. Thus, in the case where no second portion is provided in the insulating layer 21 having the chamfered portion 22 having a linear shape, a non-defective rate (here, a ratio of the number of non-defective products to the number of manufactured products) during manufacturing of the package substrate 100 is reduced as compared with the case where the second portion 211 is provided in the insulating layer 21. Furthermore, for example, if the thickness of the second portion 211 exceeds 50 μm, the package substrate 100 may not have a sufficient stress relaxation effect (an effect of relaxing stress concentration on the surface of the core substrate 11), and breakage (e.g., back breakage) may occur in the core substrate 11.
An angle α shown in
When the chamfered portion 22 has a curved shape as shown in
For example, as shown in
An angle β shown in
As shown in
As described above, the package substrate 100 according to the present embodiment includes the core substrate 11 made of a brittle material, at least one insulating layer 21 formed on one surface or both surfaces of the core substrate 11, and one or more wiring layers 31 formed on the insulating layer 21 and/or in the insulating layer 21, and the core substrate 11 is exposed on the outer peripheral portion of the insulating layer 21, and the insulating layer 21 is chamfered.
This allows the package substrate 100 to disperse the stress applied to the portion near the edge portion of the insulating layer 21, specifically, the surface of the core substrate 11 immediately below the edge portion of the insulating layer 21, thereby relaxing stress concentration. Thus, the package substrate 100 is configured to prevent breakage starting from the surface of the core substrate 11.
In the package substrate 100 according to the present embodiment, the volume of the portion of the insulating layer 21 removed during formation of the chamfered portion 22 is referred to as a chamfer volume. Furthermore, the region of the insulating layer 21 in which the distance W in the plane direction from the edge portion of the insulating layer 21 before being chamfered toward the center portion of the insulating layer 21 is not more than the thickness F of the insulating layer 21 is referred to as a specific region. The distance W is, for example, a distance between the edge portion of the insulating layer 21 before being chamfered and an upper edge of the chamfered portion 22. In the package substrate 100 according to the present embodiment, the chamfer volume of the insulating layer 21 is preferably 30% or more of the volume of the specific region described above.
This can avoid a reduction in the stress relaxation effect due to variation in the shape of the chamfered portion 22.
The brittle material for forming the core substrate 11 is preferably glass. Thus, the package substrate 100 according to the present embodiment is more likely to have the effect of relaxing stress concentration on the surface of the core substrate 11.
Other than the components described above,
As shown in
The insulating layer 21 of the package substrate 200 according to the present embodiment is provided with a chamfered portion 23.
As shown in
A curvature radius R of the chamfered portion 23 having an arc shape may be in the range of 10 μm or more and 300 μm or less. The curvature radius R is preferably in the range of 20 μm or more and 150 μm or less, and more preferably in the range of 30 μm or more and 60 μm or less. For example, if the curvature radius R exceeds 300 μm, a joint between the linear portion 122 and the corner portion 121 of the insulating layer 21 has an angular shape instead of a smooth shape. Thus, the stress may be concentrated on the corner portion 121 of the insulating layer 21, thereby causing cracks in the resin constituting the insulating layer 21. In order to form a shape having a curvature radius R exceeding 300 μm, a special blade is required to be manufactured, leading to higher production cost for the package substrate 100. Furthermore, if the curvature radius R is less than 10 μm, the stress may be concentrated on a portion of the chamfered portion 23 having the curvature radius R, thereby causing cracks in the resin constituting the insulating layer 21.
When a ratio between the curvature radius R of the chamfered portion 23 having an arc shape and the thickness of the insulating layer 21 is 1/20 or less, cracks may occur on the curved surface of the resin constituting the insulating layer 21, and the cracks cause breakage starting from the exposed glass surface of the core substrate 11.
Thus, in the package substrate 200 according to the present embodiment, the curvature radius R of the chamfered portion 23 is preferably 1/20 or more of the thickness F of the insulating layer 21. This allows the package substrate 200 to relax stress concentration on the arc-shaped portion of the insulating layer 21 corresponding to the chamfered portion 23. This can prevent a situation where the resin is damaged at the curvature portion of the insulating layer 21 and the glass constituting the core substrate 11 is exposed, and the stress concentrated on the exposed glass surface causes breakage starting from the glass surface of the core substrate 11.
The curvature radius R is preferably 1/20 or more of the thickness F of the insulating layer 21, but is not limited to this.
The package substrate 200 according to the present embodiment may be configured such that, as shown in
For example, as shown in
For example, as shown in
As shown in
In the package substrate 200 according to the present embodiment, since at least part of the insulating layer 21 (the chamfered portion 23 in the example) has an arc shape in cross section, it is possible to more effectively relax stress concentration on the surface of the core substrate 11. This makes it possible to provide a package substrate in which no breakage occurs in the core substrate 11 even when the package substrate is highly multilayered. Furthermore, it is possible to provide a package substrate in which no breakage occurs in the insulating layer 21 even when the insulating layer 21 is made of a resin having high elasticity.
As shown in
The insulating layer 21 of the package substrate 300 according to the present embodiment is provided with a chamfered portion 24.
As shown in
In the multistage structure of the insulating layer 21, a thickness (thickness D in
In the present invention, the thickness of the first stage of the multistage structure of the insulating layer 21 is not limited to 50 μm or less.
In the insulating layer 21 of the package substrate 300 according to the present embodiment, as shown in
In the present embodiment, when a photosensitive material is used as the insulating layer 21, there is no need to perform a separate process for forming a shape of the edge portion of the insulating layer 21. The chamfered portion 24 having a multistage structure can be formed by changing the area of the insulating layer corresponding to each stage in the multistage structure by photolithography. Regardless of whether the step of removing the edge portion of the insulating layer 21 is performed, a structure in which part of the edge portion of the insulating layer 21 appears to be removed can also be included in the chamfered portion.
As shown in
As shown in
In
The present invention and the advantageous effects thereof will be described below with reference to specific examples, but the following examples do not limit the scope of application of the present invention.
First, a wiring substrate panel 1 shown in
Then, the wiring layer 31 and the insulating layer 21 were repeatedly formed to laminate five wiring layers 31 and four insulating layers 21 on each of the front and back surfaces of the core substrate 11. Thus, the insulating layers 21 including the adhesive layers had a total thickness of 132 μm. Pattern formation for the wiring layer 31 by copper plating was performed using a semi-additive method, and a laser via was formed to obtain conduction between the layers. Next, the outer layer insulating resin 41 was formed by using a photosensitive insulating resin and forming an opening in part of a connection pad or the like.
Next, as shown in
Next, as shown in
In this manner, in the present example, a chamfered shape with an arc shape having a curvature was formed at the edge portion of the insulating layer 21 by dicing blade processing. By using the dicing blade to process the shape of the edge portion of the insulating layer 21 and by controlling the shape of the dicing blade, the desired curvature radius can be obtained at the edge portion of the insulating layer 21. This allows the edge portion of the insulating layer 21 to have an arc structure capable of effectively relaxing stress concentration.
Next, as shown in
First, a wiring substrate panel 2 shown in
Then, the wiring layer 31 and the insulating layer 21 were repeatedly formed to laminate five wiring layers 31 and four insulating layers 21 on each of the front and back surfaces of the core substrate 11. The insulating layers 21 were formed so that each time an insulating layer 21 was formed, the insulating layer 21 had a width smaller by 40 μm on each side than the previous insulating layer 21. Thus, as shown in
Next, as in Example 1, the wiring substrate panel 2 was diced by using the dicing blade 62 to obtain a package substrate similar to the package substrate 300 shown in
In the present example, as described above, the edge portions of the insulating layers 21 were formed having a multistage structure by forming the insulating layers 21 by photolithography using the photosensitive resin to form the insulating layers 21 so that the insulating layers 21 had different resin formation areas. This makes it possible to obtain the desired multistage structure at the edge portions of the insulating layers 21, thereby allowing the edge portions of the insulating layers 21 to have the multistage structure capable of effectively relaxing stress concentration.
First, the wiring substrate panel 1 shown in
Next, the wiring substrate panel 1 was laser processed to remove a portion of the insulating layer 21 corresponding to an outer periphery of each dice to expose the core substrate 11. At this time, a laser scanning pattern, the number of scans, a scanning speed, and the like were set so that the edge portion of the insulating layer 21 was formed in the desired shape. The laser processing was performed by using a “laser processing apparatus manufactured by ESI”. Next, the wiring substrate panel 1 was diced by using the dicing blade 62. Thus, as shown in
In the package substrate according to the present example, the corner portions 221 of the insulating layer 21 had an arc shape in plan view as with the package substrate 400 according to the fourth embodiment (see
Thus, in the present example, the shape of the edge portion of the insulating layer 21, i.e., the chamfered shape, was formed by laser processing. The use of a laser to process the shape of the edge portion of the insulating layer 21 improves the degree of freedom in design and increases the number of possible shapes to be formed, thereby allowing the edge portion of the insulating layer 21 to have the desired shape. For example, the laser processing achieved both the arc shape in plan view of the corner portions of the insulating layer 21 as shown in
First, the wiring substrate panel 1 shown in
Next, as in Example 1, the wiring substrate panel 1 shown in
Next, as shown in
Next, as in Example 1, the wiring substrate panel 1 was diced by using the dicing blade 62 (see
First, the wiring substrate panel 1 shown in
Next, as in Example 1, as shown in
Next, the wiring substrate panel 1 was diced by using the dicing blade 62 to obtain a package substrate of the present comparative example as shown in
(Evaluation)
The package substrates of Examples 1 to 4 and Comparative Example 1 were subjected to a temperature cycle test, and it was evaluated whether breakage occurred in the core substrate 11 during temperature change.
(Temperature Cycle Test)
The package substrates of Examples 1 to 4 and Comparative Example 1 were subjected to pretreatment in accordance with JEDEC (JESD22A113) standard MSL level 3, followed by 1000 cycles of Temperature cycle test condition B (−55° C. or more and 125° C. or less) described in JEDEC standard (JESD22-A104). After the temperature cycle test, the package substrates of Examples 1 to 4 and Comparative Example 1 were checked for the occurrence of breakage. As the results of the temperature cycle test, the case where no breakage occurred in the glass constituting the core substrate 11 was evaluated as “Good”, and the case where breakage occurred in the glass constituting the core substrate 11 was evaluated as “Poor”.
(Evaluation Results)
Table 1 shows the evaluation results of the temperature cycle test.
As shown in Table 1, for the package substrates of Examples 1 to 4, the results of the temperature cycle test were “Good”, and it was verified that no breakage occurred in the glass constituting the core substrate 11 during the temperature change.
On the other hand, as shown in Table 1, for the package substrate of Comparative Example 1, the results of the temperature cycle test were “Poor”, and it was confirmed that breakage occurred in the glass constituting the core substrate 11 during temperature change.
This verified that according to the package substrate and the method of manufacturing the same of the present invention, since the edge portion of the insulating layer 21 is chamfered, it is possible to relax stress concentration on the edge portion of the insulating layer during temperature change, thereby preventing breakage of the core substrate 11.
Thus, according to the present invention, even when a package substrate that includes a core substrate made of a brittle material and is obtained by dicing a wiring substrate is subjected to significant temperature change or repeated temperature change during production, during mounting, during use, or the like, no breakage occurs in the core substrate. Therefore, the present invention provides an improved and even highly reliable package substrate.
Although the embodiments and examples of the present invention have been described, needless to say, the present invention is not limited to the above description, and without departing from the technical idea, other layers or structures may be optionally formed considering the application as a package substrate and for the purpose of improving other required physical properties such as rigidity, strength, and impact properties.
Although the present invention has been described using specific examples, the present invention is not limited to these descriptions. Various modifications of the disclosed embodiments and other embodiments of the present invention will become apparent to those skilled in the art upon reference to the description of the present invention. Therefore, it should be understood that the claims cover these modifications and embodiments included in the scope and spirit of the present invention.
The present invention can be applied to a semiconductor device including a package substrate such as an interposer interposed between a main substrate and an IC chip.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2019-005064 | Jan 2019 | JP | national |
This application is a continuation application filed under 35 U.S.C. § 111(a) claiming the benefit under 35 U.S.C. §§ 120 and 365(c) of International Patent Application No. PCT/JP2020/001351, filed on Jan. 16, 2020, which is based upon and claims the benefit of priority to Japanese Patent Application No. 2019-005064, filed on Jan. 16, 2019; the disclosures of which are incorporated herein by reference in their entireties.
| Number | Name | Date | Kind |
|---|---|---|---|
| 20100122838 | Asami et al. | May 2010 | A1 |
| 20190162778 | Kanematsu | May 2019 | A1 |
| Number | Date | Country |
|---|---|---|
| 101742813 | Jun 2010 | CN |
| 2017-073424 | Apr 2017 | JP |
| 2018-116963 | Jul 2018 | JP |
| WO-2014045633 | Mar 2014 | WO |
| Entry |
|---|
| International Searching Authority, “International Search Report,” issued in connection with International Patent Application No. PCT/JP2020/001351, dated Mar. 31, 2020. |
| International Searching Authority, “Written Opinion,” issued in connection with International Patent Application No. PCT/JP2020/001351, dated Mar. 31, 2020. |
| Office Action issued in corresponding Chinese Patent Application No. 202080007990.5 dated Mar. 22, 2024 (16 pages). |
| Number | Date | Country | |
|---|---|---|---|
| 20210351094 A1 | Nov 2021 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2020/001351 | Jan 2020 | WO |
| Child | 17376534 | US |
