Patent Application
20170083000
A portion of the disclosure of this patent document contains material, which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
This application claims the benefit of U.S. Provisional Patent Application No. 62/221,028, filed on Sep. 20, 2015, which is incorporated by reference herein in its entirety.
The present invention relates to a method for scheduling time constrained single-arm cluster tools with wafer revisiting.
The following references are cited in the specification. Disclosures of these references are incorporated herein by reference in their entirety.
In semiconductor manufacturing, cluster tools that adopt single-wafer processing technology are widely used in wafer processing for better quality control and lead time reduction. A typical cluster tool is configured with several process modules (PMs), a wafer handling robot, and two loadlocks for wafer loading and unloading. According to the number of arms equipped for the robot, a cluster tool is called a single-arm or dual-arm cluster tool as shown in
With two loadlocks, a cluster tool can operate uninterruptedly under steady state. Studies for modeling and performance evaluation of cluster tools under the steady state have been extensively done [Chan et al., 2011; Ding et al., 2006; Kim et al., 2012 and 2015; Jung an Lee, 2012; Nishi and Matsumoto, 2015; Venkatesh et al., 1997; Wikborg and Lee, 2013; Yi et al., 2008; and Zuberek, 2001]. Under the steady state, if wafer processing time dominates the process, a cluster tool is called to be process-bound, while it is called to be transport-bound if the robot is always busy. According to [Kim et al. 2003], the time taken for the robot to move from one step to another can be treated as the same and is much shorter than the wafer processing time. In this case, a cluster tool operates in the process-bound region such that a backward scheduling strategy is optimal for a single-arm tool [Lee et al., 2004, and Lopez et al., 2003] and a swap scheduling strategy is optimal for a dual-arm tool [Venkatesh et al., 1997].
The aforementioned studies are conducted under the assumption that there is no constraint on the wafer sojourn time in a PM. For some wafer fabrication processes, such as low-pressure chemical-vapor deposition, there are strict wafer residency time constraints, which requires that a wafer should be removed from a PM within a given time after it is processed [Kim, et al., 2003, Lee and Park., 2005, Rostami et al. 2001, Yoon and Lee, 2005, Qiao et al., 2012, Wu and Zhou, 2012a, Wu and Zhou, 2012b]. Without any intermediate buffer between the PMs, the scheduling problem of tools with residency time constraints is very complex and challenging. The scheduling problem of cluster tools with wafer residency time constraints is studied and techniques are developed to find an optimal periodical schedule in [Kim et al., 2003, Lee and Park, 2005, Hamidzadeh and Camporese, 2001]. To improve computational efficiency, this problem is further tackled for both single-arm and dual-arm cluster tools by using schedulability analysis and closed-form solution methods are presented in [Wu et al., 2008 and Wu and Zhou, 2010a]. They present a so called robot waiting method. By this method, a schedule is parameterized by robot waiting time and can be obtained by setting the robot waiting time.
The above-mentioned work is done for wafer fabrication processes with no wafer revisiting. Some wafer fabrication processes, such as the atomic layer deposition (ALD) process, require that a wafer should be processed by some processing steps more than once, leading to a revisiting process. With wafer revisiting, a cluster tool is no longer a flow-shop and methods developed for scheduling tools without wafer revisiting are not applicable. As shown in [Wu et al., 2013a], for a dual-arm cluster tool with wafer revisiting, a three-wafer cyclic schedule is obtained if a swap strategy is applied and the system may never reach a steady state. Furthermore, with wafer revisiting, a cluster tool is deadlock-prone, which further complicates the scheduling problem of a cluster tool. Lee and Lee, [2006] pioneer the study of scheduling single-arm cluster tools with wafer revisiting. They model the system by a Petri net and the scheduling problem is then formulated as a mixed integer programming to find an optimal periodical schedule. Following the work in [Lee and Lee, 2006], Wu et al., [2011] develop a maximal permissive deadlock-avoidance policy for a single-arm cluster tool with the ALD process. Based on the model and the control policy, analytical expressions are proposed to find the optimal schedule. For dual-arm cluster tools with wafer revisiting, a method is presented to obtain a two-wafer cyclic schedule that is better than a three-wafer schedule. Since a one-wafer cyclic schedule is easy to implement and control, this problem is further investigated in [Qiao et al., 2013] and a modified swap strategy is proposed to obtain a one-wafer periodical schedule. It is shown that such a schedule can reach the lower bound of cycle time. The scheduling problem of dual-arm cluster tools with both wafer revisiting and residency time constraints is studied and effective techniques are proposed to find an optimal one-wafer cyclic schedule in [Qiao et al., 2014].
However, to the best knowledge of the inventors, up to now, no study has been done on the scheduling problem of single-arm cluster tools with both wafer revisiting and wafer residency time constraints. Notice that it is more difficult to avoid deadlock for a single-arm cluster tool with wafer revisiting than for a dual-arm tool. Thus, scheduling single-arm cluster tools with both wafer revisiting and wafer residency time constraints is more complicated.
There is a need in the art for a method for scheduling time constrained single-arm cluster tools with wafer revisiting.
With wafer revisiting, a single-arm cluster tool is deadlock-prone and it is very difficult to schedule such a tool to satisfy wafer residency time constraints. Thus, scheduling single-arm cluster tools with wafer revisiting and residency time constraints is very challenging. Up to now, there are studies on scheduling single-arm cluster tools with wafer revisiting or wafer residency time constraints, but not both. The present invention conducts a study on scheduling single-arm cluster tools with both of them for the ALD process. Based on a p-backward strategy, a Petri net is developed to model the process. With the model, analysis on the existence of a feasible schedule is done and schedulability conditions are established. By the proposed method, a schedule is parameterized as robot waiting time. Hence, if a feasible schedule exists, a schedule can be found very efficiently by simply setting the robot waiting time. The obtained schedule is shown to be optimal in terms of productivity.
An aspect of the present invention is to provide a method for scheduling time constrained single-arm cluster tools with wafer revisiting.
According to an embodiment of the present invention, a computer-implemented method for scheduling a cluster tool, the cluster tool comprising a single-arm robot for wafer handling, a wafer-processing system comprising four process modules including PM1, PM2, PM3, and PM4, each for performing a wafer-processing step with a wafer residency time constraint where the ith process module, i ε{1, 2, . . . , 4}, is used for performing Step i of the wafer-processing steps for each wafer, and a wafer flow pattern having (PM1, (PM2, PM3)h, PM4) with (PM2, PM3)h being the revisiting process and h≧2, the method comprising:
obtaining, by a processor, a lower bound πiL of a production cycle of Step i, iε{1, 2, . . . 4}, as follows:
π1L=α1+3μ+4λ;
π2L=2α2+α3+5μ+8λ;
π3L=2α3+α2+5μ+8λ; and
π4L=α4+3μ+4λ;
obtaining, by a processor, an upper bound πiU of a production cycle of Step i, iε{1, 2, . . . 4}, as follows:
π1U=α1+3μ+4λ;
π2U=2α2+α3+5μ+8λ;
π3U=2α3+α2+5μ+8λ; and
π4U=α4+3μ+4λ;
πLmax=max{πiL,iε4};
πUmin=min{πiU,iε4};
η1=14λ+12μ+α2+α3;
if [π1L,π1U]∩[π2L,π2U]∩[π3L,π3U]∩[π4L,π4U]≠Ø and η1<πLmax, then setting ω0=ω1=ω2=ω3=0, and setting ω4=πLmax−η1;
else if [π1L,π1U]∩[π2L,π2U]∩[π3L,π3U]∩[π4L,π4U]≠Ø and πLmax≦η1≦πUmin, then setting ω0=ω1=ω2=ω3=0;
else if [π1L,π1U]∩[π2L,π2U]∩[π3L,π3U]∩[π4L,π4U]=Ø and πLmax≦η1≦πUmin, then setting ωi,iεΩ3 by
Embodiments of the present invention are described in more detail hereinafter with reference to the drawings, in which:
In the following description, a method for scheduling time constrained single-arm cluster tools with wafer revisiting is set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the invention. Specific details may be omitted so as not to obscure the invention; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.
The aim of the present invention is to cope with this challenging problem for a single-arm cluster tool. The problem is modeled by a Petri net by using a p-backward strategy explained later. With the model, analysis on the existence of a feasible schedule is carried out and conditions under which a schedule exists are presented. If it is schedulable, a schedule is very efficiently obtained by simply setting the robot waiting time. The obtained schedule is shown to be optimal in terms of cycle time.
In Section A, the present invention develops the PN model for the system. Based on it, Section B carries out the schedulability analysis, establishes the schedulability conditions, and presents scheduling algorithms to obtain the optimal schedule. Illustrative examples are used to demonstrate the proposed method in Section C.
Petri nets (PNs) are recognized as a powerful tool for dealing with concurrent activities and resource allocation. They are widely used for modeling, analysis, and control of manufacturing systems [Wu et al., 2008a, and 2011, 2013; and Kim et al., 2003 and 2013]. The present invention adopts PN to model the dynamic behavior of a single-arm cluster tool with both wafer residency time constraints and wafer revisiting.
Scheduling a cluster tool is to effectively allocate its limited resources to tasks. To do so, the present invention adopts the resource-oriented PN (ROPN) to model the system. It is a finite capacity PN and its basic concept is based on [Murata, 1989, Wu, 1999; and Wu and Zhou, 2001, and 2009]. It is denoted as PN=(P, T, I, O, M, K), where P=(p1, p2, . . . , pm) and T=(t1, t2, . . . , tn) are finite sets of places and transitions with P∩T=Ø and P∪T≠Ø; I: P×T→N={0, 1, 2, . . . } and O: P×T→N describe the relation from P to T and T to P, respectively; M: P→N is a marking with M(p) being the number of tokens in place p and M0 being the initial marking; K: P→{1, 2, 3, . . . } is a capacity function with K(p) representing the maximum number of tokens that can be held by p at a time.
Let •t={p: pεP and I(p, t)>0} be the preset of transition t and t•={p: pεP and O(p, t)>0} be its postset. Similarly, p's preset •p={tεT: O(p, t)>0} and postset p•={tεT: I(p, t)>0}. Then, the transition enabling and firing rules are defined as follows.
Definition 2.1: A transition tεT in a finite capacity PN is said to be enabled if following conditions are satisfied.
M(p)≧I(p,t),∀pεP (2.1)
K(p)≧M(p)−I(p,t)+O(p,t),∀pεP (2.2)
By Definition 2.1, when (2.1) is met, t is said to be process-enabled, and when (2.2) is met, t is said to be resource-enabled. Thus, t is enabled if it is both process and resource-enabled.
An enabled tεT at marking M can fire. The firing oft transforms the PN from M to M′ according to
M′(p)=M(p)−I(p,t)+O(p,t),∀pεP (2.3)
In wafer fabrication, ALD is a typical revisiting process and, as done in [Wu et al., 2011], the present invention focuses on the ALD process. In ALD, a wafer visits Step 1 first and then it goes to Steps 2 and 3 sequentially for processing. After being processed by Step 3, it goes back to Step 2 and the Step 3. This process is repeated for several times. To control the quality, every time the wafer visits Steps 2 and 3, the exact same processing environment is required. To ensure the processing environment requirement, each step is configured with only one PM. One assumes that PM, is configured for Step i. Thus, as presented in [Wu et al., 2011], the wafer flow pattern for this process can be denoted as (PM1, (PM2, PM3)h, PM4) with (PM2, PM3)h being the revisiting process and h≧2. For the simplicity of presentation, the present invention focuses on the case when h=2. Notice that the obtained results with h=2 can be extended to cases with h>2. Then, a single-arm cluster tool with both wafer residency time constraints and wafer revisiting is modeled by an ROPN as follows.
Let Nn{1, 2, 3, . . . , n} and Ωn=Nn∪{0}. As shown in
With the resources in the system being modeled, transitions are used to model the material flows. Timed transition tij, i, jεΩ4, models the activity that the robot moves from pi to pj with a wafer being carried. Timed transition yij, i, jεΩ4, models the activity that the robot moves from pi to pj without carrying a wafer. Transitions sn1 and sn2 represent the robot tasks that load and unload a wafer into and from pn, nεΩ4, respectively. By doing so, the structure of the model is formed.
With the developed PN structure, by putting a V-token representing a virtual wafer, the initial marking M0 is set as follows. Set M0(pi)=1, iεN4\{1}, M0(p1)=0, and M0(p0)=n to indicate that, there are always wafers in the loadloacks to be processed; M0(r)=0; M0(qij)=0, iε4 and jεΩ3, and M0(q02)=1, indicating that the robot is waiting at the loadlocks for unloading a wafer there.
With wafer revisiting process, there are two ways for a token in q33 to go, one is to q21 by firing t32 and the other is to q41 by firing t34, leading to a conflict. To eliminate such a conflict, colors are introduced to the model to form a colored PN as follows.
Definition 2.2: Transition ti in the PN is defined to have a unique color C(ti)=ci.
By Definition 2.2, the color of t32 and t34 are C32 and c34, respectively. Let Wd(g) be the d-th wafer released into the system and being processed for the g-th time by a PM. Then, one can define the color of a token as follows.
Definition 2.3: Define the color of a token Wd in q33 as C(q33, Wd)=c3, if it will go to step j for processing when it leaves q33.
By Definition 2.3, one has C(q33, Wd(q))=C(t32)=e32, 1≦q<h, and (q33, Wd(h))=C(t34)=c34. Notice that, in the model, only q33 has multiple output transitions. Hence, by Definitions 2.2 and 2.3, conflict is eliminated. Besides conflict, deadlock is an important issue for operating a single-arm tool with wafer revisiting. To avoid deadlock, one presents a control policy by the following definition.
Definition 2.4: At any marking M, transitions y20 is control-enabled only if the transition firing sequence t12→s21 has just performed; y03 is control-enabled only if s01 has just fired; y14 is control-enabled only if s11 has just fired; y42 is control-enabled only if s41 has just fired; y22 is control-enabled only if the transition firing sequence t32→s21 has just performed; y33 is control-enabled only if the transition firing sequence y42→s22→t23→s31 has just fired; and y31 is enabled only if the transition firing sequence t32→s21→y22→s22→t23→s31 has just performed.
Let M=(S1, S2, S3, S4) represent the marking of the system, where Si represents the state at Step i, iεN4. Si={Wd(g)} representing that the d-th wafer is being processed at Step i for the g-th time, or {Vd(g)} representing that the d-th virtual wafer is being processed at Step i for the g-th time, or {null} representing that Step i is idle. In this way, as above discussed, one has M0=({null}, {V3(1)}, {V2(2)}, {V1(1)}). Then, by Definition 2.4, at M0, the only enabled transition is s02. After s02 fires, R performs task sequence <t01→s11→y14→s42→t40→s01→y03→s32→t34 (according to its color)→s41→y42→s22→t23→s31→y33 waiting for the completion of the wafer at Step 3→s32→t32 (according to its color)→s21→y22→waiting for the completion of the wafer at Step 2→s22→t23→s31→y31→s12→t12→s21→y20→s02> such that a cycle is completed and there is no deadlock. This implies that, by the control policy given in Definition 2.4, the model is deadlock-free. It can be verified that this control policy is necessary and sufficient.
In order to schedule the process, it is necessary to model the time taken for performing each activity. From the PN model, both transitions and places represent tasks that take time. As done in [Lee and Lee, 2006; and Wu et al, 2011], one assumes that the time taken for each activity is deterministic and known. The time taken for the robot to move from Step i to j, i≠j, with or without holding a wafer is assumed to be same [Kim et al., 2003] and denoted by μ, i.e., it takes μ time units to fire tij and yij. Note that in the revisiting process, after loading a wafer into p3/p2, the robot waits there for the completion of the wafer and it does nothing and takes no time. Similarly, the time taken for the robot to unload (firing si2)/load (firing si1) a wafer from/into a step is assumed to be the same as well and it is denoted by λ. The time taken for processing a wafer in pi, iεΩ4, is αi with αi>0, i≅0, and α0=0.
Let δi be the longest time for which a wafer can stay in a PM at Step i without being scrapped after being processed. Then, with wafer residency time constraints, the wafer sojourn time at Step i should be within [αi, αi+δi], i.e., a token should stay in PMi for at least αi time units and no more than αi+δi time units. One uses τi and τ4 to denote the wafer sojourn time at Steps 1 and 4, respectively; and τ2j and τ3j, jεN2 to denote the wafer sojourn time for the j-th visiting Steps 2 and 3, respectively. Notice that no wafer residency time constraint is imposed on Step 0. The symbols and explanation are summarized in Table I.
From the above analysis, for a single-arm cluster tool with wafer revisiting and residency time constraints, according to [Wu et al., 2008; and Wu and Zhou, 2010b], one has the following schedulability definition.
Definition 2.5 [Wu et al., 2008; and Wu and Zhou, 2010b]: Given the wafer sojourn time interval [αi, αi+δi] for Step i, iε4, if there exists a schedule such that whenever si2, iε{1, 4}, fires, αi≦τi≦αi+δi holds, and whenever si2, iε{2, 3}, fires, αi≦τij≦αi+δi, +jεN2, holds, then, a single-arm cluster tool with wafer revisiting and residency time constraints is schedulable.
With the PN model, one discusses the scheduling problem next.
In [Wu et al., 2011], a p-backward strategy is proposed to schedule a single-arm cluster tool for the ALD process without taking wafer residency time constrains into account. Based on the PN model, the present invention adopts this strategy to explore the schedulability and scheduling problem of a single-arm cluster tool with residency time constraints for the ALD process. If schedulable, efficient algorithm is developed to find an optimal schedule.
To make the scheduling analysis, one needs to present the p-backward scheduling strategy for a single-arm cluster tool with wafer revisiting. Based on the PN model, one shows how a p-backward strategy works. Since a single-arm cluster tool with wafer revisiting is deadlock-prone, to avoid deadlock, the system must start from a proper state. One assumes that the system starts from Marking M1=({null}, {W3(1)}, {W2(2)}, {W1(1)}) and, at the same time, the robot is idle, or M1(r)=1. Notice that this marking is consistence with M0 that is set in the last section and can be reached by applying a p-backward strategy. By starting from M1 with a p-backward strategy being applied, the system evolves as follows.
Note that Marking M8 is equivalent to M1 in the sense of dynamic behavior of PN. Hence, by transforming M1 to M8, a cycle is completed. This is what a p-backward strategy does.
With the above discussion, one can analyze the cycle time for the system. Let φj be the time taken for the robot to perform σj, jεN7. Then, from the time modeling, one can easily obtain φ1=μ+ω0+λ+μ+λ=2μ+2λ+ω0. Similarly, for σ2-7, one has φ2=2μ+2λ+ω4, φ3=2μ+2λ+ω3; φ4=2μ+2λ+ω2; φ5=μ+2λ+α3; φ6=μ+2λ+α2; and φ7=2μ+2λ+ω1.
Since σ1-7 form a robot cycle, the robot cycle time is
where η1=14λ+12μ+α2+α3 is the robot task time in a cycle and
is the robot waiting time in a cycle. Notice that η1 is constant and known in advance and ω0-4 in η2 should be determined by a schedule.
Based on the fact that the cycle time of the entire system must be equal to the robot cycle time [Wu. et. al., 2008], with the robot cycle time obtained, one can analyze the wafer sojourn time at each Step. It follows from the above analysis that the wafer sojourn time at Step 1 is equal to the robot cycle time minus the time taken for performing σ1 and the time for firing s12, t12, and s21 in σ7, i.e., one has
τ1=η−(2μ+2λ+ω0)−(μ+2λ)=η−3μ−4λ−ω0 (3.2)
Similarly, for Step 4, one has
τ4=η−3λ−4λ−ω3 (3.3)
For Step 2, the sojourn time taken for a wafer to visit the step for the first time is different from that for a wafer to visit the step for the second time. One uses τ21 and τ22 to denote them, respectively. It follows from the above transition firing analysis that τ21 is equal to the robot cycle time minus the time taken for σ5-7 and the time taken for firing s22, t23, and s31 in σ4. Thus, one has
When a wafer visits Step 2 for the second time, the robot loads it into PM2 and waits here for its completion. Thus, one has
τ22=α2 (3.5)
Similarly, one can calculate the wafer sojourn time for Step 3 and one has
τ31=α3 (3.6)
τ32=η−5μ−8λ−α3−α2−ω2 (3.7)
With wafer residency time constraints, to make a schedule feasible, the cycle time for each step should be in a permissive range. Thus, one analyzes such a range for each step as follows. For Step 1, it follows from the above analysis that, to complete a wafer requires three robot moving tasks between steps (t01, t12, and y21), two wafer unloading tasks (s02 and s12), and two wafer loading tasks (s11 and s21). Thus, with the wafer staying time in Step 1, the time taken for this process is
θ1=τ1+3μ+4λ+ω0 (3.8)
To be feasible, one has τ1ε[α1, α1+δ1]. Hence, the permissive shortest cycle time at Step 1 is
θ1S=α1+3μ+4λ+ω0 (3.9)
and the permissive longest cycle time at Step 1 is
θ1L=α1+δ1+3μ+4λ+ω0 (3.10)
Similarly, the cycle time for completing a wafer at Step 4 is
θ4=τ4+3μ+4λ+ω3 (3.11)
The permissive shortest cycle at Step 4 is
θ4S=α4+3μ+4λ+ω3 (3.12)
and the permissive longest cycle time at Step 4 is
θ4L=α4+δ4+3μ+4λ+ω3 (3.13)
For Step 2 in the revisiting process, one analyzes the wafer cycle as follows. By firing s21 (σ8=<s21 (λ)>), a wafer is loaded into Step 2 for processing for the first time, which is followed by transition firing sequence σ9=(y20→sO2→t01→s11→y14→s42→t40→s01→y03→s32→t34→s41→y42). During the time for performing σ9, the wafer just loaded into Step 2 is being processed. Hence, the time taken for performing σ9 is the wafer sojourn time for the first visiting Step 2, i.e., τ21. Then, transition firing sequence σ10=<t23 (μ)→s31 (λ)→y33 (0)→waiting for the completion at Step 3 (α3)→s32 (λ)→t32 (μ)→s21 (λ) (loading the wafer into Step 2 to be processed for the second time)→y22 (0)→waiting for the completion of the wafer at Step 2 (τ22)→s22 (λ)→t23(μ)→s31(λ)→y31(μ)→waiting in q12 (ω1)→s12(λ)→t12 (μ)> is performed. By performing σ8-10, a cycle is completed at Step 2. Thus, the time taken for completing a wafer at Step 2 is
θ2=τ21+τ22+α3+5μ+8λ+ω1 (3.14)
With τ21ε[α2, α2+δ2] and τ22=α2, the permissive shortest cycle at Step 2 is
θ2S=α2+α2+α3+5μ+8λ+ω1=2α2+α3+5μ+8λ+ω1 (3.15)
and the permissive longest cycle time at Step 2 is
θ2L=α2+δ2+α2+α3+5μ+8λ+ω1=2α2+δ2+α3+5μ+8λ+ω1 (3.16)
For Step 3, similar to Step 2, one analyzes the process as follows. One has the following transition firing sequence σ11=<s31 (a wafer is loaded into Step 3 to be processed for the first time, λ)→y33 (0)→waiting for the completion of the wafer at Step 3 (τ31)→s32 (λ)→t32 (μ)→s21 (λ)→y22 (0)→waiting for the completion of the wafer at Step 2 (α2)→s22 (λ)→t23 (μ)→s31 (λ)>. Then, transition firing sequence σ12=<y31→s12→t12→s21→y20→s02→t01→s11→y14→s42→t40→s01→y03> is performed. During the time for performing σ12, a wafer for its second visiting of Step 3 is completed. Thus, the time taken for doing so is τ32. Finally, to complete a cycle, transition firing sequence σ13=<s32 (λ)→t34(μ)→s41(λ)→y42(μ)→waiting in q22 (ω2)→s22(λ)→t23 (μ)> is performed. Thus, the cycle time for Step 3 is
θ3=τ31+τ32+α2+5μ+8λ+ω2 (3.17)
With τ31=α3 and τ32ε[α3, α3+δ3], the permissive shortest cycle at Step 3 is
θ3S=2α3+α2+5μ+8λ+ω2 (3.18)
and the permissive longest cycle time at Step 3 is
θ3L=2α3+δ3+α2+5μ+8λ+ω2 (3.19)
With the above timeliness analysis, one discusses the scheduling problem next. Notice that the above derived expressions are functions of robot waiting time. Hence, the scheduling problem is to decide the robot waiting time ωi's to obtain a schedule if it exists.
Let θ be the production cycle of the system. Then, the production rate for all the steps must be θ. Also, the robot cycle should be equal to the production rate too, i.e., one has
θ=θ1=θ2=θ3=θ4=η (3.20)
Based on the above analysis, to make (3.20) hold, one needs to decide ωi's in η2. Also, to schedule a cluster tool, the production rate should be maximized, which requires to minimize η2. Furthermore, with wafer residency time constraints, schedule feasibility is essential. To be feasible, a schedule should ensure that θi is in an acceptable interval. Let πiL and πiU denote the lower and upper bounds of θi. It follows from the above analysis that when ω0=ω1=ω2=ω3=ω4=0, θiS and θiL are the lower and upper bounds of θi, respectively. Thus, by removing the robot waiting time from (3.9), (3.10), (3.12), (3.13), (3.15), (3.16), (3.18), and (3.19), one has the following lower and upper bounds of θi.
π1L=α1+3μ+4λ (3.21)
π1U=α1+δ1+3μ+4λ (3.22)
π2L=2α2+α3+5μ+8λ (3.23)
π2U=2α2+δ2+α3+5μ+8λ (3.24)
π3L=2α3+α2+5μ+8λ (3.25)
π3U=2α3+δ3+α2+5μ+8λ (3.26)
π4L=α4+3μ+4λ (3.27)
π4U=α4+δ4+3μ+4λ (3.28)
Let πLmax=max {πiL,iεN4} and πUmin=min{πiU, iεN4}, one has the following lemma.
Lemma1: If η1>πUmin, the system is not schedulable.
Proof:
It follows from the above discussion that θ=η≧η1. When η=η1, one has ω0ω1=ω2=ω3=ω4=0. In this case, if πUmin=πkU, kε{1, 4}, by (3.2) and (3.3), one has τk=η1−3μ−4λ>πkU−3μ−4λ=αk+δk+3μ+4λ−3μ−4λ=αk+δk. This implies that the wafer residency time constraints are violated for Step k, kε{1, 4}. If πUmin=π2U, by (3.4), one has τ21=η1−5μ−8λ−α3−α2>π2U−5μ−8λ−α3−α2=2α2+δ2+α3+5μ+8λ−5μ−8λ−α3−α2=α2+δ2. Hence, the wafer residency time constraints are violated for Step 2. If πUmin=π3U, by (3.4), one has τ32=η1−5μ−8λ−α3−α2>π3U−5μ−8λ−α3−α2=2α3+δ3+α2+5μ+8λ−5μ−8λ−α3−α2=α3+δ3. The wafer residency time constraints are violated for Step 3.
Then, one discusses the case when η>η1. In this case, one has and ωi≦η−η1, ∀iεΩ4. If πUmin=πkU, kε{1, 4}, by (3.2) and (3.3), one has τk=η−3μ−4λ−ωk-1≧3μ−4λ−(η1−η1)=η1−3μ−4λ>πkU−3μ−4λ=αk+δk+3μ+4λ−3μ−4λ=αk+δk. The residency time constraints are violated for Step k, kε{1, 4}. If πUmin=π2U, by (3.4), one has τ21=η−5μ−8λ−α3−α2−ω1≧η−5μ−8λ−α3−α2−(η−η1)=η1−5μ−8λ−α3−α2>π2U−5μ−8−α3−α2=2α2+α3+5μ+8λ−5μ−8λ−α3−α2=α2+δ2. The residency time constraints are violated for Step 2. If πUmin=π3U, by (3.4), one has τ32=η−5μ−8λ−α3−α2−ω2≧η−5μ−8λ−α3−α2−(η−η1)=η15μ−8λ−α3−α2>π3U−5μ−8λ−α3−α2=2α3+α2+5μ+8λ−5μ−8λ−α3−α2=α3+δ3. The residency time constraints are violated for Step 3. Thus, in any case, no matter how ωi's are set, a feasible schedule cannot be found.
Next one discusses the schedulability and scheduling problem when η1<πUmin. One has the following two cases.
[π1L,π1U]∩[π2L,π2U]∩[π3L,π3U]∩[π4L,π4U]≠Ø {circle around (1)}
[π1L,π1U]∩[π2L,π2U]∩[π3L,π3U]∩[π4L,π4U]=Ø {circle around (2)}
For Case {circle around (1)}, one has the following lemmas.
Lemma 2: If η1<πLmax, let ω0=ω1=ω2=ω3=0 and ω4=πLmax−η1, the obtained schedule is feasible.
Proof By the obtained schedule, the cycle time for the tool is θ=η=πLmax. In this case, one has πiL≦θ=η=πLmax≦πiU, iεN4. Then, for Step i, iε{1, 4}, by (3.2) and (3.3), τi=πLmax−3μ−4λ≧πiL−3μ−4λ=αi and τi=πLmax−3μ−4λ≦πiU−3μ−4λ=αi+δi, or the wafer residency time constraints are satisfied. For Step 2, by (3.4), τ21=πLmax−5μ−8λ−α3−α2≧π2L−5μ−8λ−α3−α2=α2 and τ21πLmax−5μ−8λ−α3−α2≦π2U−5μ−8λ−α3−α2=α2+δ2. By (3.5), τ22=α2. Hence, the wafer residency time constraints are satisfied for Step 2. For Step 3, by (3.6), τ31=α3. By (3.7), τ32=πLmax−5μ−8λ−α3−α2>π3L−5μ−8λ−α3−α2=α3 and τ32=πLmax−5μ−8λ−α3−α2≦π3U−5μ−8λ−α3−α2=α3+δ3. Hence, the wafer residency time constraints are satisfied for Step 3. Therefore, the obtained schedule is feasible and the system is schedulable.
Lemma 3: If πLmax≦η1≦πUmin, set ω0ω2=ω3=ω4=0, the obtained schedule is feasible.
Proof:
In this case, the cycle time θ=η=η1. Then, for Step i, iε{1, 4}, one has τi=η1−3μ−4λ≧πiL−3μ−4λ=αi and τi=η1−3μ−4λ≦πiU−3μ−4λ=αi+δi. For Step 2, one has τ21=η1−5μ−8λ−α3−α2≧π2L−5μ−8λ−α3−α2=α2 and τ21η1−5μ−8λ−α3−α2≦π2U−5μ−8λ−α3−α2=α2+δ2, and τ22=α2. For Step 3, one has τ31=α3, and τ32=η1−5μ−8λ−α3−α2≧π3L−5μ8λ−α3−α2=α3 and τ32η1−5μ−8λ−α3−α2≦π3U−5μ−8λ−α3−α2=α3+δ3. Thus, for all the steps, the wafer residency time constraints are satisfied and the obtained schedule is feasible.
For Case {circle around (2)}, there must exist at least one iε4 such that πiU<πLmax. Let E={i|πiU<πLmax, iε
4} and F=
4\E. Then, for Step i, iε
4, one sets ωi-1 as follows.
Then, one has the following lemma.
Lemma 4: For the case of [π1,L, π1U]∩[π2L, π2U]∩[π3L, π3U]#[π4L, π4U]=└, let
where ωi, iεΩ3 is determined via (3.29). Then, if ω4≧0, the obtained schedule is feasible, otherwise the system is not schedulable.
Proof:
One first shows that when ω4≧0, the obtained schedule is feasible. It follows from (3.29) and
that one has θ=η=πLmax. Then, for Step i, iε{1, 4}, if iεF, τi=πLmax−3μ−4λ≧πiL−3μ−4λ=αi and τi=πLmax−3μ−4λ≦πiU−3μ−4λ=αi+δi. If iεE, τi=πLmax3μ−4λ−(πLmax−αi−δi−4λ−3μ)=αi+δi. For Step 2, one has τ22=α2. If 2εF, τ21=πLmax−5μ−8λ−α3−α2≧π2L−5μ−8λ−α3−α2=α2 and τ21=πLmax−5μ−8λ−α3−α2<π2U−5μ−8λ−α3−α2=α2+δ2. If 2εE, τ21=πLmax5μ−8λ−α3−α2−(πLmax−α2−δ2−α2−α3−4λ−3μ)=α2+δ2. For Step 3, one has τ31=α3. If 3εF, τ32=πLmax5μ−8λ−α3−α2≧π3L−5μ−8λ−α3−α2=α3 and τ32=πLmax5μ−8λ−α3−α2<π3U−5μ−8λ−α3−α2=α3+δ3. If 3εE, τ32=πLmax−5μ−8λ−α3−α2−(πLmax−α3−δ3−α2−α3−4λ−3μ)=α3+δ3. Thus, the wafer residency time constraints are satisfied for all the steps and the obtained schedule are feasible.
Now one shows that the system is not schedulable if ω4<0. When ω4<0, the obtained schedule is meaningless, or one cannot find a feasible schedule such that θ=η=πLmax. Then, there are two choices: (1) η<πLmax and (2) η>πLmax.
If η<πLmax, one assumes that πiL=πLmax, iε4. If iε{1, 4}, for Step i, one has τi=η−3μ−4λ−ωi-1<πLmax−3μ−4λ−ωi-1=πiL−3μ−4λ−ωi-1<αi. If π2L=πLmax, one has τ21=η−5μ−8λ−α3−α2−ω1<πLmax−5μ−8λ−α3−α2−ω1=π2L−3μ−4λ−ω1≦α2. If π3L=πLmax, one has τ32=η−5μ−8λ−α3−α2−ω2<πLmax−5μ−8λ−α3−α2−ω2=π3L−3μ−4λ−ω2≦α3. This implies that the wafer residency time constraints are violated for at least one step. Thus, a feasible schedule cannot be found, it is not schedulable.
If η>πLmax, one assumes that η=πLmax+Δη and φi-1=ωi-1+Δωi-1, where ωi-1 is obtained via (3.29), iεE. Then, according to (3.1), one has
If πiL=πLmax, iεE, and iε{1, 4}, one has πLmax+Δη=αi+δi+4λ+3μ+ωi-1+Δωi-1=πLmax+Δωi-1. If πiL=πLmax, iεE, and iε{2, 3}, one has πLmax+Δη=αi+δi+8λ+5μ+α2+α3+ωi-1+Δωi-1=πLmax+Δωi-1. Thus, one has Δη=Δωi-1=πLmax and iεE. Since ω4<0,
This contradicts to (3.30), i.e., a feasible schedule cannot be found.
Up to now, one presents the conditions under which a feasible schedule can be found for a single-cluster tool with wafer revisiting and residency time constraints. Notice that, by above analysis, for each case, one presents a schedule, then check its feasibility. Thus, if a feasible schedule exists, a feasible schedule can be found by simply setting the robot waiting time. In summary, an algorithm is presented as follows to find a schedule if it exists.
Algorithm 1: Find a feasible schedule for a single-am cluster tool with wafer residency time constraints for an ALD process if it exists as
Then, if ω4≧0, a feasible schedule is obtained.
By Algorithm 1, only simple calculation is needed such that the proposed method is computationally very efficient. Another issue for scheduling problem is its productivity. The following theorem shows the optimality of the proposed method.
Theorem 1: If the system is schedulable, the obtained schedule by methods given in Lemmas 2 to 4 is optimal in terms of productivity.
Proof Let πiL=πLmax, iε4. According to Lemmas 2 and 4, if the system is scheduled such that θ=η<πLmax, from (3.2)-(3.7), one has τi<αi, if πiL=πLmax and iε{1, 4}; τ21<α2, if π2L=πLmax, and τ32<α3, if π3L=πLmax. In other words, the obtained schedule is not feasible. Thus, by the algorithms given in Lemmas 2 and 4, the obtained schedule has a minimal cycle time, or maximal productivity.
This section uses examples with wafer flow pattern (PM1, (PM2, PM3)2, PM4) to show the proposed method.
The wafer processing time at PM1-4 is α1=120 s, α2=40 s, α3=45 s, and α4=125 s, respectively. After a wafer is completed, it can stay in PM1-4 for at most δ1=30 s, δ2=20 s, δ3=20 s, and δ4=30 s, respectively. The robot task time is λ=μ=3 s.
For this example, one has π1L=141 s, π1U=171 s, π2L=164 s, π2U=184 s, π3L=169 s, π3U=189 s, π4L=146 s, π1U=176 s, πLmax=169 s, and ƒ1=163 s. One can check that [π1L, π1U]∩[π2L, π2U]∩[π3L, π3U]∩[π4L, π4U]≠Ø and η1≦πLmax. Then, according to Lemma 2, one sets ω0=ω1=ω2=ω3=0 and ω4=πLmax−η1=6 s and a feasible schedule is obtained with cycle time θ=η=πLmax=169 s.
The wafer processing time at PM1-4 is α1=95 s, α2=35 s, α3=30 s, and α4=100 s, respectively. After a wafer is completed, it can stay in PM1-4 for at most δ1=30 s, δ2=20 s, δ3=20 s, and δ4=30 s respectively. The robot task time is λ=μ=3 s.
One has π1L=116 s, π1U=146 s, π2L=139 s, π2U=159 s, π3L=134 s, π3U=154 s, π4L=121 s, π4U=151 s, πLmax=139 s, and η1=143 s. Thus, [π1L, π1U]∩[π2L, π2U]∩[π3L, π3U]∩[π4L, π4U]#Ø and πLmax≦η1≦πUmin hold, and it is schedulable. Then, according to the algorithm given in Lemma 3, one sets ω0=ω1=ω2=ω3=ω4=0 s and a feasible schedule is obtained with cycle time θ=η=η1=143 s.
The wafer processing time at PM1-4 is α1=115 s, α2=40 s, α3=45 s, and α4=125 s, respectively. After a wafer is completed, it can stay at PM1-4 for at most δ1=30 s, δ2=20 s, δ3=20 s, and δ4=30 s, respectively. The robot task time is λ=μ=3 s.
For this example, one has π1L=136 s, π1U=166 s, π2L=164 s, π2U=184 s, π3L=169 s, π3U=189 s, π4L=146 s, π4U=176 s, πLmax=169 s, and η1=163 s. It can be checked that [π1L, π1U]∩[π2L, π2U]∩[π3L, π3U]∩[π4L]=Ø and E={1}. According to Lemma 4, one sets ω0=3, ω1=ω2=ω3=0, and ω4=3. Since ω4>0, the system is schedulable and the obtained schedule is feasible with cycle time θ=η=πLmax=169 s. Based on the PN model, one shows how this schedule is implemented as follows. According to the system modeling, one has M0=({null}, {V3(1)}, {V2(2)}, {V1(1)}) and one assumes the starting time is γ0=0. Then, the system evolves as follows.
1) From γ0=0 to γ1=15, task sequence <y20→robot waits in q02→s02→t01→s11> such that M1=({W1(1)}, {W0(1)}, {W0(2)}, {W0(1)}) is reached.
Through the above sequence, a cycle of the system is formed, which demonstrates that the cycle time is 169 s.
The embodiments disclosed herein may be implemented using general purpose or specialized computing devices, computer processors, or electronic circuitries including but not limited to digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA), and other programmable logic devices configured or programmed according to the teachings of the present disclosure. Computer instructions or software codes running in the general purpose or specialized computing devices, computer processors, or programmable logic devices can readily be prepared by practitioners skilled in the software or electronic art based on the teachings of the present disclosure.
In some embodiments, the present invention includes computer storage media having computer instructions or software codes stored therein which can be used to program computers or microprocessors to perform any of the processes of the present invention. The storage media can include, but is not limited to, floppy disks, optical discs, Blu-ray Disc, DVD, CD-ROMs, and magneto-optical disks, ROMs, RAMs, flash memory devices, or any type of media or devices suitable for storing instructions, codes, and/or data.
The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiment is therefore to be considered in all respects as illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
| Number | Date | Country | |
|---|---|---|---|
| 62221028 | Sep 2015 | US |
