Phase change memory devices and program methods

Abstract

A phase change memory device is disclosed. It includes a memory cell array including a plurality of memory cells programmed in relation to a phase change material, and a write driver circuit configured to provide a set current and a reset current to a selected memory cell. The write driver circuit includes a set current driver configured to provide the set current and a reset current driver configured to provide the reset current.

Description

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a circuit diagram illustrating a memory cell of a conventional phase change memory device;

FIG. 2 is a circuit diagram illustrating another memory cell of a conventional phase change memory device;

FIG. 3 is a graph illustrating characteristics of the phase change material of FIGS. 1 and 2;

FIG. 4 is a circuit diagram illustrating a write driver circuit of a conventional phase change memory device;

FIG. 5 is a block diagram illustrating a phase change memory device according to the present invention;

FIG. 6 is a circuit diagram illustrating an example of a write driver circuit of FIG. 5; and

FIG. 7 is a circuit diagram illustrating another example of a write driver circuit of FIG. 5.

Claims

1. A phase change memory device, comprising: a memory cell array including a plurality of memory cells programmed in relation to a phase change material; anda write driver circuit configured to provide a set current and a reset current to a selected memory cell,wherein the write driver circuit comprises a set current driver configured to provide the set current and a reset current driver configured to provide the reset current.

2. The phase change memory device of claim 1, wherein the write driver circuit further comprises: a pulse controller configured to receive a set pulse or a reset pulse according to a logic level of input data, and generate a set control signal in response to the set pulse or a reset control signal in response to the reset pulse;a set current controller responsive to the set control signal and configured to control the magnitude of the set current in response to a set DC voltage; anda reset current controller responsive to the reset control signal and configured to control the magnitude of the reset current in response to a reset DC voltage.

3. The phase change memory device of claim 2, wherein the pulse controller comprises: a first transmission gate configured to receive the set pulse;a second transmission gate configured to receive the reset pulse;a set control signal generator configured to generate the set control signal in response to the input data and the set pulse; anda reset control signal generator configured to generate the reset control signal in response to the input data and the reset pulse.

4. The phase change memory device of claim 2, wherein the set current controller comprises: a PMOS transistor connected between a power terminal and a set node and having a gate receiving a set node voltage;a first NMOS transistor connected to the set node and configured to form a current path in response to the set DC voltage; anda second NMOS transistor coupled between the first NMOS transistor and ground and configured to form a current path in response to the set control signal.

5. The phase change memory device of claim 4, wherein the set current controller further comprises: a set current cutoff circuit configured to prevent the set current from being generated by controlling the set node voltage when the set pulse is disabled.

6. The phase change memory device of claim 5, wherein the set current cutoff circuit comprises a PMOS transistor coupled between a power terminal and the set node and configured to form a current path in response to the set pulse.

7. The phase change memory device of claim 4, wherein the set current driver controls the magnitude of the set current according to the set node voltage.

8. The phase change memory device of claim 2, wherein the set current controller comprises a transfer circuit configured to transfer the set current voltage to the set current driver in response to the set control signal.

9. The phase change memory device of claim 8, wherein the transfer circuit comprises an inverter and a transmission gate.

10. The phase change memory device of claim 2, wherein the reset current controller comprises: a PMOS transistor connected between a power terminal and a reset node, and having a gate receiving the reset control signal; anda transmission gate transferring the reset DC voltage to the reset node in response to the reset control signal.

11. The phase change memory device of claim 9, wherein the reset DC voltage is 0 V.

12. The phase change memory device of claim 10, wherein the reset current driver controls the magnitude of the reset current according to the reset node voltage.

13. The phase change memory device of claim 11, wherein the reset current driver comprises a PMOS transistor configured to generate the reset current according to the reset node voltage.

14. The phase change memory device of claim 1, wherein each one of the plurality of memory cells comprises: a memory element containing the phase change material; anda select element for selecting the memory cell,the select element including a diode connected between the memory element and a wordline.

15. A method of programming a phase change memory device, the phase change memory device comprising an array of memory cells each programmed in relation to a phase change material, and a write driver circuit including a set current driver and a reset current driver configured to provide set current and reset current to a selected memory cell respectively, the method comprising: receiving a set pulse or a reset pulse in accordance with a logic level of input data;generating a reset control signal in response to the input data and the reset pulse;receiving a reset DC voltage in response to the reset control signal; andproviding the reset current to the selected memory cell in response to the reset DC voltage.

16. The method of claim 15, wherein the reset current driver controls the magnitude of the reset current in relation to the reset DC voltage.

17. The method of claim 15, further comprising: generating a set control signal in response to the input data and the set pulse; andproviding the set current to the selected memory cell in response to the set control signal and a set DC voltage.

18. The method of claim 17, wherein the set current driver controls the magnitude of the set current in relation to the set DC voltage.