As semiconductor device sizes continue to shrink some lithography technologies suffer from optical restrictions, which lead to resolution issues and reduced lithography performance. In comparison, extreme ultraviolet (EUV) lithography can achieve much smaller semiconductor device sizes and/or feature sizes through the use of reflective optics and radiation wavelengths of approximately 13.5 nanometers or less.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
One of the issues with extreme ultraviolet (EUV) lithography is that EUV radiation is highly absorbed by most matter due to the short wavelength of EUV radiation. As a result, only a small fraction of EUV radiation that is generated by an EUV source is finally available at a substrate that is to be patterned. Thus, elements used in deep ultraviolet lithography photoresist materials (e.g., carbon (C), hydrogen, and oxygen (O), among other examples) may not be suitable for EUV lithography, as these elements may not provide sufficient absorption of EUV radiation. One way of compensating for the loss of EUV radiation intensity at the substrate is to use highly-absorptive metallic photoresist materials. However, these materials may suffer from surface roughness issues and air/water sensitivity, which can decrease the patterning performance of the photoresist layers that are formed using the materials.
Some implementations described herein provide photoresist materials that include various types of tin (Sn) clusters having one or more types of ligands. As an example, a photoresist material described herein may include tin clusters bearing two or more different types of carboxylate ligands. As another example, a photoresist material described herein may include tin oxide clusters that include carbonate ligands. The two or more different types of carboxylate ligands and the carbonate ligands may reduce, minimize, and/or prevent crystallization of the photoresist materials described herein, which may increase the coating performance of the photoresist materials and may decrease the surface roughness of photoresist layers formed using the photoresist materials described herein.
The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some implementations, the deposition tool 102 includes a spin coating tool that is capable of depositing a photoresist layer on a substrate such as a wafer. In some implementations, the deposition tool 102 includes a chemical vapor deposition (CVD) tool such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some implementations, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some implementations, the example environment 100 includes a plurality of types of deposition tools 102.
The exposure tool 104 is a semiconductor processing tool that is capable of exposing a photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep UV light source, an extreme UV light (EUV) source, and/or the like), an x-ray source, an electron beam (e-beam) source, and/or the like. The exposure tool 104 may expose a photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include a pattern for forming one or more structures of a semiconductor device, may include a pattern for etching various portions of a semiconductor device, and/or the like. In some implementations, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.
The developer tool 106 is a semiconductor processing tool that is capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool 104. In some implementations, the developer tool 106 develops a pattern by removing unexposed portions of a photoresist layer. In some implementations, the developer tool 106 develops a pattern by removing exposed portions of a photoresist layer. In some implementations, the developer tool 106 develops a pattern by dissolving exposed or unexposed portions of a photoresist layer through the use of a chemical developer.
In some implementations, one or more of the deposition tool 102, the exposure tool 104, and/or the developer tool 106 may be configured to perform various types of baking operations such as a pre-exposure bake operation or a post-exposure bake operation. Baking the substrate may include elevating the temperature of the photoresist layer for a time duration. In some implementations, the deposition tool 102, the exposure tool 104, and the developer tool 106 are included in a track unit designed for multiple photoresist-related processes including coating, baking, and developing.
The etch tool 108 is a semiconductor processing tool that is capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etch tool 108 may include a wet etch tool, a dry etch tool, and/or the like. In some implementations, the etch tool 108 includes a chamber that is filled with an etchant, and the substrate is placed in the chamber for a particular time period to remove particular amounts of one or more portions of the substrate. In some implementations, the etch tool 108 may etch one or more portions of the substrate using a plasma etch or a plasma-assisted etch, which may involve using an ionized gas to isotopically or directionally etch the one or more portions.
Wafer/die transport tool 110 includes a mobile robot, a robot arm, a tram or rail car, an overhead hoist transport (OHT) system, an automated material handling system (AMHS), and/or another type of device or system that is used to transport wafers and/or dies between semiconductor processing tools 102-108 and/or to and from other locations such as a wafer rack, a storage room. In some implementations, wafer/die transport tool 110 may be a programmed device that is configured to travel a particular path and/or may operate semi-autonomously or autonomously.
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A layer 204 may be formed over and/or on the substrate 202. The layer 204 may be a layer that is to be etched based on a pattern in a photoresist layer. The layer 204 may be etched to form various types of semiconductor devices, openings, trenches, vias, interconnects, contacts, and/or other types of semiconductor structures. The layer 204 may include a dielectric layer, a metallization layer, a hard mask layer, and/or another type of semiconductor layer. In some implementations, the layer 204 is omitted, and the pattern is used to etch the substrate 202.
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The photoresist layer 208 may include one or more of the photoresist materials described herein, such as a tin-based photoresist material or a tin oxide-based photoresist material. The photoresist material(s) that is used to form the photoresist layer 208 may include one or more types of tin (Sn) clusters, and a plurality of different types of carboxylate ligands or a plurality of carbonate ligands. The combination of the tin clusters and the plurality of different types of carboxylate ligands or a plurality of carbonate ligands may reduce, minimize, and/or prevent crystallization of the photoresist material used to form the photoresist layer 208, which may increase the coating performance of the photoresist material and may decrease the surface roughness of photoresist layer 208. The decreased surface roughness may reduce and/or minimize blurring and broken pattern lines in the pattern that is to be formed in the photoresist layer 208, and may enable decreases in half pitch sizes of the pattern that is to be formed in the photoresist layer 208, among other examples.
The deposition tool 102 may deposit the photoresist material using a deposition technique, such as a spin-coating technique, to form the photoresist layer 208. The deposition tool 102 may spin the substrate 202 at a spin rate in a range of approximately 800 revolutions per minute (RPM) to approximately 2200 RPM and for a time duration in a range of approximately 10 seconds to approximately 1 minute to ensure that the photoresist material is fully distributed across the surface of the ARC 206. However, other values for the spin rate and for the time duration are within the scope of the present disclosure.
The deposition tool 102 may form the photoresist layer 208 to a thickness of approximately 20 nanometers to approximately 30 nanometers to achieve a low surface roughness, to reduce and/or minimize blurring and broken pattern lines, to achieve a half pitch of the pattern that is to be formed in the photoresist layer 208 in a range of approximately 35 nanometers to approximately 18 nanometers or lower, and/or to achieve a low radiation dosage energy in a range of approximately 180 milli-Joules per centimeter area to approximately 150 mJ/cm2 or lower. However, other values for the thickness of the photoresist layer 208 are in within the scope of the present disclosure.
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One or more of the deposition tool 102, the exposure tool 104, or an integrated tool that includes the deposition tool 102 and the exposure tool 104 may perform the pre-exposure bake operation. In some implementations, the pre-exposure bake operation is performed for a time duration that is in a range of approximately 30 seconds to approximately 600 seconds to ensure that the photoresist layer 208 is fully baked (and the solvent is fully removed) without unduly reducing throughput of photoresist pattern formation. However, other values for the time duration are within the scope of the present disclosure. In some implementations, the pre-exposure bake operation is performed at a temperature that is in a range of approximately 65 degrees Celsius to approximately 200 degrees Celsius to ensure that the solvent is removed from the photoresist material while reducing and/or minimizing metal cluster cross-linking in the photoresist layer 208 (which might lead to a reduction in resolution between exposed and unexposed portions of the photoresist layer 208). However, other values for the temperature are within the scope of the present disclosure.
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In some implementations, the radiation 218 is transmitted through the mask 214 and onto the photoresist layer 208 based on the pattern 216. In some implementations, the radiation 218 includes EUV radiation, and the radiation 218 is reflected off of the mask 214 and onto the photoresist layer 208 based on the pattern 216. The wavelength of the radiation 218 may be in a range of approximately 0.005 nanometers to approximately 250 nanometers. Accordingly, the radiation 218 may include e-beam radiation (which may be used to directly expose the photoresist layer 208 without the use of a mask or reticle), EUV radiation, or deep UV radiation, among other examples.
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One or more of the deposition tool 102, the exposure tool 104, the developer tool 106, or an integrated tool that includes the deposition tool 102, the exposure tool 104, and/or the developer tool 106 may perform the post-exposure bake operation(s). In some implementations, each post-exposure bake operation is performed for a time duration that is in a range of approximately 60 seconds to approximately 600 seconds to ensure sufficient cross-linking density in the exposed portions 210 of the photoresist layer 208 without causing over cross-linking (which may lead to an increased amount of photoresist residue remaining on the substrate 202 after a development operation). However, other values for the time duration for each post-exposure bake operation are within the scope of the present disclosure.
In some implementations, a post-exposure bake operation may be performed at a temperature that is in a range of approximately 90 degrees Celsius to approximately 250 degrees Celsius to ensure sufficient cross-linking density in the exposed portions 210 of the photoresist layer 208 without causing over cross-linking. In implementations where a plurality of post-exposure bake operations are performed, a first post-exposure bake operation may be performed at a temperature that is in a range of approximately 130 degrees Celsius to approximately 220 degrees Celsius, and a second post-exposure bake operation may be performed at a temperature that is in a range of approximately 160 degrees Celsius to approximately 250 degrees Celsius, to ensure sufficient cross-linking density in the exposed portions 210 of the photoresist layer 208 without causing over cross-linking. However, other values for the temperatures of the post-exposure operations are within the scope of the present disclosure.
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The tin cluster (or tin oxide (SnOx) cluster) 312 may include a collection of tin (or tin oxide) atoms ranging from 3-tin to 12-tin. For example, the tin cluster 312 may include a 3-tin cluster, a 4-tin cluster, a 6-tin cluster, a 10-tin cluster, a 12-tin cluster, or another tin cluster. Generally, the lower the cluster number, the smaller the cluster size. As an example, a 4-tin cluster may range from approximately 0.4 nanometers in size to approximately 1 nanometer in size, whereas a 6-tin cluster may range from approximately 0.6 nanometers in size to approximately 1 nanometer in size. The line width roughness (LWR) performance of the photoresist material 318 may increase the smaller the cluster size of the tin cluster 312. However, smaller cluster sizes may provide fewer cross-linking sites and fewer ligand sites, which may result in increased radiation exposure for patterning a photoresist layer formed using the photoresist material 318. In some implementations, a single tin cluster number is used to form the photoresist material 318. In some implementations, a plurality of different tin cluster numbers are used to form the photoresist material 318.
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The precipitation reaction may include a reflux, in which the constituents (e.g., the compound 322 and the silver salt 324) are heated for a time duration (e.g., to approximately 110 degrees Celsius or another temperature for approximately 8 hours or another time duration). The heating of the constituents causes the formation of a vapor, which is continually cooled back into liquid form (e.g., as condensation) using a condenser. The condensate of the vapor is returned back to the original reaction chamber to continually undergo the above-described process for the time duration to distill the reaction. The constituents may be refluxed with dichloromethane (DCM), tetrahydrofuran (THF), or one or more other assisting chemicals. The reflux reaction may result in the formation of the photoresist material 326 illustrated in
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Bus 510 includes a component that enables wired and/or wireless communication among the components of device 500. Processor 520 includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and/or another type of processing component. Processor 520 is implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor 520 includes one or more processors capable of being programmed to perform a function. Memory 530 includes a random access memory, a read only memory, and/or another type of memory (e.g., a flash memory, a magnetic memory, and/or an optical memory).
Storage component 540 stores information and/or software related to the operation of device 500. For example, storage component 540 may include a hard disk drive, a magnetic disk drive, an optical disk drive, a solid state disk drive, a compact disc, a digital versatile disc, and/or another type of non-transitory computer-readable medium. Input component 550 enables device 500 to receive input, such as user input and/or sensed inputs. For example, input component 550 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system component, an accelerometer, a gyroscope, and/or an actuator. Output component 560 enables device 500 to provide output, such as via a display, a speaker, and/or one or more light-emitting diodes. Communication component 570 enables device 500 to communicate with other devices, such as via a wired connection and/or a wireless connection. For example, communication component 570 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and/or an antenna.
Device 500 may perform one or more processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 530 and/or storage component 540) may store a set of instructions (e.g., one or more instructions, code, software code, and/or program code) for execution by processor 520. Processor 520 may execute the set of instructions to perform one or more processes described herein. In some implementations, execution of the set of instructions, by one or more processors 520, causes the one or more processors 520 and/or the device 500 to perform one or more processes described herein. In some implementations, hardwired circuitry may be used instead of or in combination with the instructions to perform one or more processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.
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Process 600 may include additional implementations, such as any single implementation or any combination of implementations described below and/or in connection with one or more other processes described elsewhere herein.
In a first implementation, the radiation includes EUV radiation. In a second implementation, alone or in combination with the first implementation, process 600 includes performing (e.g., by the deposition tool 102, the exposure tool 104, and/or another semiconductor processing tool), prior to exposing the photoresist layer 208 to the radiation 218, a pre-exposure bake of the photoresist layer 208 for a duration that is in a range of approximately 30 seconds to approximately 600 seconds. In a third implementation, alone or in combination with one or more of the first and second implementations, process 600 includes performing (e.g., by the deposition tool 102, the exposure tool 104, and/or another semiconductor processing tool), prior to exposing the photoresist layer 208 to the radiation 218, a pre-exposure bake of the photoresist layer 208 at a temperature that is in a range of approximately 65 degrees Celsius to approximately 200 degrees Celsius.
In a fourth implementation, alone or in combination with one or more of the first through third implementations, process 600 includes performing (e.g., by the exposure tool 104, the developer tool 106, and/or another semiconductor processing tool), after exposing the photoresist layer 208 to the radiation 218 and prior to developing the pattern, a post-exposure bake of the photoresist layer 208 for a duration that is in a range of approximately 60 seconds to approximately 600 seconds. In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, process 600 includes performing (e.g., by the exposure tool 104, the developer tool 106, and/or another semiconductor processing tool), after exposing the photoresist layer 208 to the radiation 218 and prior to developing the pattern, a post-exposure bake of the photoresist layer 208 at a temperature that is in a range of approximately 90 degrees Celsius to approximately 250 degrees Celsius.
In a sixth implementation, alone or in combination with one or more of the first through fifth implementations, process 600 includes performing (e.g., by the exposure tool 104, the developer tool 106, and/or another semiconductor processing tool) a first post-exposure bake of the photoresist layer 208 after exposing the photoresist layer 208 to the radiation 218 and prior to developing the pattern 220, and performing (e.g., by the exposure tool 104, the developer tool 106, and/or another semiconductor processing tool) a second post-exposure bake of the photoresist layer 208 after the first post-exposure bake. In a seventh implementation, alone or in combination with one or more of the first through sixth implementations, a temperature of the second post-exposure bake is greater relative to a temperature of the first post-exposure bake.
In an eighth implementation, alone or in combination with one or more of the first through seventh implementations, a temperature of the first post-exposure bake is in a range of approximately 130 degrees Celsius to approximately 220 degrees Celsius, and a temperature of the second post-exposure bake is in a range of approximately 160 degrees Celsius to approximately 250 degrees Celsius. In a ninth implementation, alone or in combination with one or more of the first through eighth implementations, forming the photoresist layer 208 includes forming the photoresist layer 208 to a thickness in a range of approximately 20 nanometers to approximately 40 nanometers.
In a tenth implementation, alone or in combination with one or more of the first through ninth implementations, a wavelength of the radiation 218 is in a range of approximately 0.005 nanometers to approximately 250 nanometers. In an eleventh implementation, alone or in combination with one or more of the first through tenth implementations, the plurality of different types of organic ligands include a plurality of different types of carboxylic acids. In a twelfth implementation, alone or in combination with one or more of the first through eleventh implementations, the plurality of inorganic ligands include a plurality of carbonate ligands.
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In this way, photoresist materials described herein may include various types of tin (Sn) clusters having one or more types of ligands. As an example, a photoresist material described herein may include tin clusters bearing two or more different types of carboxylate ligands. As another example, a photoresist material described herein may include tin oxide clusters that include carbonate ligands. The two or more different types of carboxylate ligands and the carbonate ligands may reduce, minimize, and/or prevent crystallization of the photoresist materials described herein, which may increase the coating performance of the photoresist materials and may decrease the surface roughness of photoresist layers formed using the photoresist materials described herein.
As described in greater detail above, some implementations described herein provide a method. The method includes forming a photoresist layer over a substrate. A photoresist material, that is used to form the photoresist layer, includes a plurality of tin clusters and at least one of a plurality of different types of organic ligands or a plurality of inorganic ligands. The method includes exposing the photoresist layer to radiation to form a pattern in the photoresist layer. The method includes developing the pattern after exposing the photoresist layer to the radiation.
As described in greater detail above, some implementations described herein provide an EUV photoresist material. The EUV photoresist material includes a plurality of tin clusters. The EUV photoresist material includes a plurality of carboxylate ligands of the plurality of tin clusters, where the plurality of carboxylate ligands include two or more different types of carboxylic acids.
As described in greater detail above, some implementations described herein provide EUV photoresist material. The EUV photoresist material includes a plurality of tin oxide clusters. The EUV photoresist material includes a plurality of carbonate ligands of the plurality of tin oxide clusters.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.