Claims
- 1. A method of removing a hardmask from a semiconductor wafer comprising the steps of:
introducing a polishing slurry into a wafer-polishing device to cover a wafer with the polishing slurry, the wafer containing a silicon carbide hardmask layer and a Low-k dielectric, the polishing slurry having a pH of less than 6 and containing an aqueous dispersion of zirconia particles having a positive zeta potential, and the polishing device having a polishing pad; and planarizing the wafer with motion between the wafer and the polishing pad to remove the silicon carbide and the Low-k dielectric with the silicon carbide removal being at a rate of at least one half the rate of the Low-k dielectric as measured in Å/min.
- 2. The method of claim 1 wherein the step of planarizing the wafer also removes a metallic conductor from the wafer.
- 3. The method of claim 1 wherein the planarizing removes an organosilicate of the formula (SiwCxOyHz) as the Low-k dielectric.
- 4. The method of claim 1 wherein the planarizing stops on a PECVD SiO2 hardmask layer.
- 5. The method of claim 1 wherein the planarizing occurs at a pH between 3.5 and 5.
- 6. A method of removing a hardmask from a semiconductor wafer comprising the steps of:
introducing a polishing slurry into a wafer-polishing device to cover a wafer with the polishing slurry, the wafer containing a top hardmask layer of silicon carbide, a bottom hardmask layer of PECVD SiO2 and an organosilicate Low-k dielectric of the formula (SiwCxOyHz), the polishing slurry having a pH of less than 6 and containing an aqueous dispersion of zirconia particles having a positive zeta potential, and the polishing device having a polishing pad; and planarizing the wafer with motion between the wafer and the polishing pad to remove the top hardmask layer of silicon carbide and a first portion of the organosilicate Low-k dielectric with the top hardmask layer of silicon carbide removal being at a rate of at least one half the rate of the organosilicate Low-k dielectric and at least twice the rate of the second hardmask layer of PECVD SiO2 as measured in Å/min. to stop on the bottom hardmask layer of PECVD SiO2 and protect a second portion of the organosilicate Low-k dielectric, the second portion of the organosilicate Low-k dielectric being below the bottom hardmask layer of PECVD SiO2.
- 7. The method of claim 6 wherein the step of planarizing the wafer also removes a metallic conductor from the wafer.
- 8. The method of claim 6 wherein the planarizing removes copper interconnect at rate at least ten times greater than the bottom hardmask of PECVD SiO2 as measured in Å/min.
- 9. The method of claim 6 wherein the planarizing removes the organosilicate Low-k dielectric selected from the group consisting of CDO and SiCOH.
- 10. The method of claim 6 wherein the planarizing occurs at a pH between 3.5 and 5.
Parent Case Info
[0001] This application claims the benefit of U.S. Provisional Application No. 60/338,107, filed Dec. 6, 2001.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60338107 |
Dec 2001 |
US |