The present application is based on and claims priority of Japanese patent application No. 2008-181287 filed on Jul. 11, 2008, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor manufacturing apparatus for manufacturing a semiconductor device. More particularly, the present invention relates to a plasma processing apparatus using a dry etching technique for etching, by using the plasma, semiconductor materials, such as silicon and a silicon oxide film, according to a mask pattern shape formed of a resist material, and the like.
2. Description of the Related Art
The dry etching is a semiconductor fine processing method in which process gases are introduced into a vacuum chamber having vacuum evacuation means, so as to be converted into plasma by electromagnetic waves, and in which the surface of a sample to be processed other than a masked portion of the surface is etched by being exposed to the plasma and thereby a desired shape is obtained. A high-frequency voltage different from that for generating the plasma is applied to a silicon wafer as the sample to be processed, and ions are accelerated from the plasma by the high-frequency voltage, so as to be made incident on the surface of the sample to be processed. Thereby, the etching efficiency is improved and the perpendicularity of the processed shape is obtained.
In order to improve the mass productivity of etching, it is desired that the whole surface of the wafer as a sample to be processes can be used as devices. In particular, it is required that the wafer can be processed with such accuracy that a functional device is formed in a portion extending to the wafer edge portion. At present, it is required that a device can be formed in an area extending to a position about 3 to 10 mm inside from the wafer edge with a same accuracy as in the other portion. The requirement will become more severe, so as to result in a new requirement of a technique enabling the processing to be performed with high accuracy even in an area extending to a position about 1 to 3 mm inside from the wafer edge.
In order to cope with the requirement in dry etching, it is necessary to control the electric field distribution at the wafer edge portion. At the wafer edge portion, there occurs a phenomenon in which a distortion is caused in the thickness of a plasma sheath formed above the wafer due to the concentration of electric field formed by the high-frequency voltage, so as to thereby prevent ions from being made incident perpendicularly to the wafer surface. As a result, it becomes impossible to maintain the required processing accuracy in the wafer edge portion due to a phenomenon referred to as “tilting” in which a shape desired to be processed perpendicularly to the wafer surface is formed into a shape distorted in the direction of the plasma sheath. At present, there is taken a measure such as reducing the electric field concentration at the wafer edge portion by using a member referred to as an annular focus ring arranged at the wafer peripheral portion. However, in the conventional method, there is a problem that it is difficult to maintain the long-term stability and processing properties of the wafer edge portion for each of different plasma processing conditions, because the degree of tilting is changed due to a time-based shape change of the focus ring according to the wear thereof, and due to a difference in the plasma processing conditions.
An object of the present invention is to provide a plasma etching apparatus which is capable of suppressing the deterioration of processing properties, which is caused in the wafer edge portion as described in conjunction with the related art, and of thereby realizing a desirable etching shape in an area extending to the wafer edge portion. The present invention provides means for always maintaining the processing properties in the wafer edge portion in an optimal state by detecting a distortion of plasma sheath at the wafer edge portion and by referring to the detection value.
SUMMARY OF THE INVENTION
The plasma etching apparatus according to the present invention includes high-frequency power control means for controlling an amount of high-frequency power supplied to a focus ring as an annular conductor member arranged at the periphery of a wafer, and is configured such that the focus ring has a minute hole perpendicularly formed therein at a position close to the end portion of the wafer mounted on a lower electrode, that means for detecting a current (ions) is arranged in the bottom portion of the minute hole, and that the amount of high-frequency power supplied to the focus ring is controlled according to a value of current detected via the minute hole.
The ions accelerated by the plasma sheath are made incident into the minute hole provided in the focus ring arranged at the peripheral portion of the wafer, and are detected as a current by the current detecting means arranged in the bottom portion of the minute hole. The amount of ions which are made incident into the minute hole and which can reach the current detecting means arranged in the bottom portion of the minute hole, is changed by the structure of the plasma sheath formed above the focus ring. That is, when the plasma sheath is distorted due to the influence of the wafer end portion, the ions are made incident obliquely to the minute hole, and hence the amount of current detected by the current detecting means provided in the bottom portion of the minute hole is reduced. Further, the structure of the plasma sheath at the wafer peripheral portion is changed by the high-frequency power ratio of amounts of high-frequency power for ion acceleration applied to the focus ring and the wafer. Therefore, the structure of the plasma sheath generated at the wafer end portion can be always maintained in the same state by controlling the ratio of amounts of high-frequency power applied to the focus ring and the wafer, while monitoring the ion current detected by the current detecting means.
For example, it is possible to minimize the influence of the tilting due to the distortion of the plasma sheath, which is caused at the wafer end portion, and possible to maintain the processing properties in the wafer end portion for a long time, in such a manner that the distortion of plasma sheath caused by the wear of the focus ring is monitored by the current detecting means, and that the ratio of amounts of high-frequency power applied to the focus ring and the wafer is controlled by controlling the amount of high-frequency power supplied to the focus ring according to the monitored distortion amount.
Further, in the above description, there is roughly described the effect in the case where the present invention is applied to suppressing the time-based change due to the wear of the focus ring. However, the present invention can also be used to optimize the processing properties in the wafer edge portion in the case of a different object to be processed and a different processing condition. Thereby, even for various objects to be processed and various processing conditions, the optimization can be easily performed so as to obtain a state in which the wafer edge portion can always be processed with high accuracy.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a figure showing a basic configuration of embodiment 1 according to the present invention;
FIG. 2 is a figure explaining a state of an ion sheath in the present invention;
FIG. 3 is an illustration explaining the principle on the basis of which a distortion of ion sheath structure is detected by current detection means according to the present invention;
FIG. 4 is an illustration of an etching system as a whole in which the present invention is mounted; and
FIG. 5 is a figure showing a configuration of embodiment 2 according to the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Embodiment 1
A first embodiment according to the present invention will be described with reference to FIG. 1. FIG. 1 is an enlarged view of a wafer end portion of a lower electrode 2 in a plasma processing apparatus, on which lower electrode a silicon wafer 1 as a sample to be processed is mounted. In the plasma processing apparatus according to the present invention, the silicon wafer 1 is attracted to the lower electrode 2 via an insulating film for electrostatic chuck 3. Further, the electrostatic chuck force is controlled by a DC power source 4. The lower electrode 2 is cooled by a liquid or gas refrigerant which is made to flow through a refrigerant passage 5. A high-frequency voltage for drawing ions to the wafer is supplied to the lower electrode 2 from a high-frequency power supply 6 via a matching circuit 7 and a blocking capacitor 8.
At the periphery of the silicon wafer 1, an annular conductor member, for example, a focus ring 9 made of silicon is arranged concentrically with respect to the silicon wafer. A minute hole 10 is formed in the focus ring 9 in the vicinity of the inner circumferential portion thereof at a position close to the end portion of the silicon wafer 1 in the direction perpendicular to the surface of the focus ring, and further current detecting means 11 using, for example, a Faraday cup is arranged in the bottom portion of the minute hole 10. Further, the focus ring 9 is electrostatically attracted onto a focus ring lower electrode 12 via an insulating film for electrostatic chuck 13. Further, the focus ring 9 and the focus ring lower electrode 12 are DC-electrically isolated from the silicon wafer 1 and the lower electrode 2 by insulation members 14 and 15. High-frequency power is supplied to the focus ring 9 and the focus ring lower electrode 12 via a variable capacitor serving as high-frequency power distributing means 16. It is possible to control the amount of high-frequency power supplied to the focus ring 9 by the high-frequency power distributing means 16.
Further, the plasma processing apparatus according to the present invention includes the current voltage converter and A/D converter 20, a control section 21, a low pass filter 22, and an insulating cover 23. In FIG. 1, an ion sheath 18 is formed between the silicon wafer 1 and plasma 17, and ions 19 are drawn to the silicon wafer 1 and the focus ring 9 by the high-frequency voltage. The ions (current) drawn into the minute hole 10 of the focus ring 9 are detected as a strength of current by the current detecting means 11.
Next, there will be described an operation of the plasma processing apparatus shown in FIG. 1. FIG. 2(A) to FIG. 2(C) show states of the ion sheath 18 above the surface of the silicon wafer 1 and the focus ring 9 in the case where the plasma 17 is generated. In the state where the plasma 17 is generated, when a high-frequency voltage is applied to the silicon wafer 1 and the focus ring 9, the silicon wafer and the focus ring are negatively charged with respect to the plasma potential. Thereby, a potential difference is formed between the plasma 17 and each of the silicon wafer 1 and the focus ring 9, so that the ion sheath 18 is formed according to the potential difference. The thickness of the ion sheath 18 is determined by the potential differences between the plasma 17 and the silicon wafer 1, and between the plasma 17 and the focus ring 9. Also, the potential differences are determined by the high-frequency voltages respectively applied to the silicon wafer 1 and the focus ring 9.
The state of the ion sheath 18 shown in FIG. 2(A) is generated in the case where the high-frequency voltage applied to the focus ring 9 is higher than the high-frequency voltage applied to the silicon wafer 1, or in the case where the height of the focus ring 9 is larger than the height of the silicon wafer 1.
Further, the state of the ion sheath 18 shown in FIG. 2(C) is generated, contrary to the case of FIG. 2(A), in the case where the high-frequency voltage applied to the focus ring 9 is lower than the high-frequency voltage applied to the silicon wafer 1, or in the case where the height of the focus ring 9 is smaller than the height of the silicon wafer 1.
The state of the ion sheath 18 shown in FIG. 2(B) is an intermediate state between the states shown in FIG. 2(A) and FIG. 2(C), and is the case where the thickness of the ion sheath formed above the focus ring 9 is almost the same as the thickness of the ion sheath formed above the silicon wafer 1.
In the case of FIG. 2(A) and FIG. 2(C), the trajectory of the ions 19 accelerated in the ion sheath 18 is not made perpendicular to the surface of the silicon wafer 1 but is made oblique to the surface of the silicon wafer 1 due to the distortion of the ion sheath 18 at the end portion of the silicon wafer 1. Due to the oblique incidence of the ions 19, the end portion of the silicon wafer is processed into a shape reflecting the incident direction of the ions 19. This makes the normal processing difficult, so as to thereby influence the yield in manufacturing the semiconductor device.
An object of the present invention is to control the high-frequency voltage applied to the focus ring 9 in correspondence with the amount of distortion of the ion sheath 18 by monitoring the state of distortion, and is to correct the state of ions made incident on the end portion of the silicon wafer by monitoring the state of ions.
First, there will be described a method for monitoring the state of distortion of the ion sheath 18. The ions 19 accelerated in the ion sheath are made incident into the minute hole 10 which is provided in the focus ring 9 in the vicinity of the end portion of the silicon wafer 1. Then, the ions 19 are detected by the current detecting means 11 arranged in the bottom portion of the minute hole 10. At this time, when the structure of the ion sheath 18 is distorted as shown in FIG. 2(A) or FIG. 2(C), the ions 19 are made incident obliquely to the minute hole 10, and hence the ratio of the ions 19 reaching the current detecting means 11 arranged in the bottom portion is reduced. On the other hand, in the state where the ion sheath 18 is in the flat state as shown in FIG. 2(B), the ions 19 are made incident perpendicularly to the minute hole 10, and hence, the amount of current detected by the current detecting means 11 becomes maximum.
FIG. 3 schematically shows a relationship between the amount of current detected by the current detecting means 11 and the high-frequency voltage applied to the focus ring 9. In the present embodiment, the high-frequency voltage applied to the focus ring 9 can be controlled by the high-frequency power distributing means 16 using the variable capacitor shown in FIG. 1. As shown in FIG. 3, a state in which the distortion of the ion sheath 18 is minimized can be found in such a manner that a relative peak position of the current detected by the current detecting means 11 is searched by adjusting the high-frequency power supplied to the focus ring 9 by means of the high-frequency power distributing means 16. This function makes it possible to determine optimum high-frequency power supplied to the focus ring 9 for each processing condition.
Further, also as described above, the distortion of the ion sheath 18, which is generated at the end portion of the silicon wafer 1, is changed in dependence upon the relative potential state and height between the focus ring 9 and the silicon wafer 1. Therefore, the distortion of the ion sheath 18 is also influenced by the shape change of the focus ring 9 due to the wear thereof. This results in a time-based change in the yield in the end portion of the silicon wafer 1. Therefore, although a method for optimizing distortion of the ion sheath 18 according to a processing condition is described in the preceding paragraph, a correction corresponding to the wear of the focus ring 9 is necessary for maintaining the etching characteristic at the end portion of the silicon wafer for a long period of time. Due to the wear of the focus ring 9, the height of the focus ring 9 is made lower than the height of the silicon wafer 1, so that the ion sheath 18 is changed from the state of FIG. 2(B) to the state of FIG. 2(C). This change is detected by the current detecting means 11 as a change in the ion current through the minute hole 10, similarly to the case as described in the preceding paragraph. The current value is transmitted to the control section 21 via the current voltage converter and A/D converter 20, so that the amount of high-frequency power supplied to the focus ring 9 is automatically controlled. In the automatic control, the control section always maintains the state in which the current detected by the current detecting section becomes maximum, by determining the curve shown in FIG. 3. Thereby, it is possible to minimize deterioration of the processing properties in the end portion of the silicon wafer 1 due to the time-based distortion of the ion sheath 18. Further, at the same time, it is also possible, from the state of the curve shown in FIG. 3, to detect the use limit of the focus ring 9, so as to urge the exchange of the focus ring 9.
In the present invention, as the minute hole 10 formed in the focus ring 9 is positioned closer to the end portion of the silicon wafer 1, it is possible to more accurately monitor the influence of the tilting due to the distortion of the ion sheath at the end portion of the silicon wafer. Therefore, when the silicon wafer 1 is mounted, it is preferred that the minute hole 10 is formed so that the center position of the minute hole 10 is positioned 10 mm or less away from the end portion of the silicon wafer 1. Further, as the ratio (aspect ratio) of the depth to diameter of the minute hole 10 is increased, the sensitivity of detecting the distortion in the ion trajectory is increased. This is because the ions 19 are required to be made incident perpendicularly to the minute hole 10 to reach the current detecting means 11 through the minute hole 10, and because as the aspect ratio of the minute hole 10 is increased, the ions 19 whose incident angle is even slightly changed are made to collide with the surface of the minute hole, so as to thereby become unable to reach the current detecting means 11. However, when the aspect ratio is excessively increased, the amount of current to be detected is also reduced, so as to make it difficult to obtain the required sensibility. Therefore, the hole diameter of the minute hole 10 is sets to 0.1 mm or more to 2 mm or less, and the depth of the minute hole 10 is set to 1 mm or more to 20 mm or less. It is also preferred to set the aspect ratio between 5 and 50. By using a minute hole having a hole diameter of 0.1 mm to 2 mm and having a depth of 1 mm to 20 mm, it is possible to make the required current sensitivity compatible with the tilting amount detection.
In the embodiment as shown in FIG. 1, there is shown only one set of the minute hole 10 formed in the focus ring 9 and the current detecting means 11. However, the accuracy of evaluation of the tilting degree can be improved in such a manner that two or more sets are arranged at the periphery of the silicon wafer 1 as a sample to be processed, and that the tilting degree is evaluated on the basis of the current detection results at the plurality of places. For example, it is possible to improve the control accuracy by controlling the high-frequency voltage applied to the focus ring 9 so as to attain a state in which the number of the current detecting means 11 showing the current maximum value shown in FIG. 3 is maximized in the current detection results at the plurality of places. When the control is performed on the basis of the detection result at only one place, the possibility that an erroneous determination is performed due to the influences of abnormality in the detecting means, a slight difference in the wafer position, and the like, is increased. Therefore, for maintaining the accuracy of the determination, it is effective that the detectors configured by a plurality of minute holes 10 and the current detecting means 11 are arranged at a plurality of places in the circumferential direction of the silicon wafer 1, and that the detection results of the detectors are statistically determined. Of course, it is obvious that when the positional accuracy, and the like, of the silicon wafer 1 is sufficient, the similarly effect can be obtained even by the determination based on the current detection result at one place.
FIG. 1 is an illustration showing only a fundamental configuration according to the present invention. FIG. 4 shows an illustration of an etching system as a whole. In the embodiment shown in FIG. 4, a plasma processing apparatus forms plasma of process gases between an upper electrode 25 and the silicon wafer 1 in a vacuum chamber 27, by the interaction between a high frequency voltage of 200 MHz supplied to the upper electrode 25 from a high-frequency power supply 26 for plasma generation and a magnetic field generated by an electromagnetic coil 29. The process gases are supplied in the vacuum chamber 27 from a shower plate 28 arranged on the silicon wafer 1 side of the upper electrode 25. A high-frequency voltage of 4 MHz is applied to the silicon wafer 1 by the high-frequency power supply 6. The plasma processing apparatus is also configured such that the high-frequency voltage of 4 MHz, which is formed by branching the power supplied from the high-frequency power supply 6 via the variable capacitor arranged as the high-frequency power distributing means 16, is similarly applied to the focus ring 9. The other configuration of the plasma processing apparatus is the same as that shown in FIG. 1, and the same components are denoted by the same reference numerals, and their explanation is omitted.
The same high-frequency voltage of 4 MHz as the voltage applied to the silicon wafer 1 is applied to the upper electrode 25 via a phase and power control section 30, and a filter 33, so as to be superimposed on the above described high-frequency voltage supplied by the high-frequency power supply 26 for plasma generation. The high-frequency voltage of 4 MHz applied to the upper electrode 25 is controlled by the phase and power control section 30, so as to have a phase difference of 180° with respect to the electromagnetic wave of 4 MHz applied to the silicon wafer 1. Further, the power of the electromagnetic wave of 4 MHz applied to the upper electrode 25 is also controlled by the phase and power control section 30 independently of the electromagnetic wave of 4 MHz applied to the silicon wafer 1 and the focus ring 9. The upper electrode 25 and the lower electrode 2 are temperature-controlled by using a liquid refrigerant respectively supplied to the upper electrode 25 and the lower electrode 2 by temperature control means 31 and 32.
Next, there will be described an operation of the plasma processing apparatus shown in FIG. 4. The silicon wafer 1 and the focus ring 9 are exposed to plasma formed by the high-frequency power of 200 MHz supplied to the upper electrode 25 from the high-frequency power supply 26 for plasma generation. At this time, the electric field strength in the ion sheath is increased by applying, to the silicon wafer 1 and the focus ring 9, the high-frequency voltage of 4 MHz supplied from the high-frequency power supply 6, so that the ions can be accelerated and irradiated onto the silicon wafer 1 and the focus ring 9. At this time, the width of the ion sheath above the focus ring 9 can be controlled independently of the width of the ion sheath above the silicon wafer 1 by controlling the amount of high-frequency power of 4 MHz supplied to the focus ring 9 by the variable capacitor serving as the high-frequency power distributing means 16. This control is performed in such a manner that a value of ion current detected by the current detecting means 11 via the minute hole 10 is determined by the control section 21.
As described above with reference to FIG. 1, the amount of ion current is changed as shown in FIG. 3 in dependence upon the states of the ion sheath as shown in FIG. 2(A) to FIG. 2(C). The amount of high-frequency power supplied to the focus ring 9 is set such that the amount of ion current is in the peak position shown in FIG. 3 for each etching condition by the high-frequency power distributing means 16, so that the shape in the silicon wafer edge is preferably maintained and thereby the yield is improved. When the maximum value of the ion current detected by the current detecting means 11 is determined, the determination is not performed on the basis of the detection result of one set of current detecting means 11, but the results obtained by the plurality of minute holes 10 and current detecting means 11, which are arranged at the periphery of the silicon wafer 1, are comprehensively determined. Thereby, it is possible to more surely set the distribution ratio of power supplied to the focus ring 9.
In the above, there is described an embodiment in which the amount of high-frequency power supplied to the focus ring 9 is fixed for each condition. However, the processing properties in the silicon wafer peripheral portion may be changed with time due to the wear of the focus ring 9, or the like, at the time when the distributed power amount is fixed. In this case, the processing properties in the edge portion can be maintained to a certain degree, in such a manner that the amount of power distributed to the focus ring 9 is controlled by the high-frequency power distributing means 16 so as to maintain the peak position shown in FIG. 3, while the amount of current made incident into the current detecting means 11 is continuously monitored by the control section 21. As a result, the life of the focus ring 9 can be increased, so that the processing properties can be maintained and the cost due to wear can also be reduced.
In the embodiments shown in FIG. 1 and FIG. 4, there is described a case where the amount of high-frequency power distributed to the focus ring 9 is controlled so as to be set to the peak position of the ion current as shown in FIG. 3, but the control to set the amount of high-frequency power to the peak position is not necessarily optimal. There may be a case where the amount of high-frequency power may be set to a value within a predetermined range. Thus, it is obvious that the amount of high-frequency power is controlled so as to be set to the value in this case.
In the embodiments shown in FIG. 1 and FIG. 4, as for the frequency for generating the plasma, an electromagnetic wave of 200 MHz is used. However, it is obvious that the similar effects can also be obtained even in the case where the plasma is generated by using an electromagnetic wave of 13 MHz to 500 MHz in the same form or the same form in which the magnetic field is not used. Further, it is obvious that the present invention provides the same effects even in a plasma generation system which uses, as a form of discharge, an electron cyclotron resonance system using an electromagnetic wave in microwave band and a magnetic field, or an induction coupling system using a radio wave region.
In the embodiments shown in FIG. 1 and FIG. 4, the high-frequency voltage applied to the silicon wafer 1 and the focus ring 9 is 4 MHz. However, the same effects according to the present invention can also be obtained even when a high-frequency voltage of 400 kHz or more to 27 MHz or less is used. Further, in the embodiments shown in FIG. 1 and FIG. 4, the control of the high-frequency power supplied to the focus ring 9 is performed by branching the power supplied from the high-frequency power source to the silicon wafer 1. However, it is obvious that the same effects can also be obtained by using separate power sources respectively for the focus ring 9 and the silicon wafer 1. In this case, however, there may be a case where the cost is increased because two sets of power sources are necessary, and a case where an electric field is generated due to a phase difference between the high-frequency voltages on the silicon wafer 1 and the focus ring 9, and thereby an abnormal discharge is caused between the silicon wafer 1 and the focus ring 9. When the control is performed with the separate power sources, there may be a case where the phase control needs to be performed to suppress the abnormal discharge between the silicon wafer 1 and the focus ring 9 due to the phase difference. Further, the lower electrode 12, on which the silicon wafer 1 is mounted, and the focus ring 9 are arranged adjacent to each other, and hence are coupled to each other to some extent in terms of high frequency due to a parasitic capacitance therebetween. This tendency is increased as the frequency is increased. Thus, even when the separate power sources are used, it becomes difficult to perform the control due to the interference between the power sources. Therefore, in the case where the frequency of the high-frequency voltage applied to the silicon wafer 1 and the focus ring 9 is 1 MHz or more, it is easier to perform the control by branching the output of a single power source as shown in FIG. 1 and FIG. 4.
FIG. 5 shows another embodiment different from the embodiment shown in FIG. 1. The embodiment shown in FIG. 5 is a form in which a plurality of minute holes 10 formed at different angles are arranged in the peripheral direction of the focus ring 9, and in which current detecting means 11, 35 and 36 are arranged in the respective minute holes. In the embodiment shown in FIG. 5, in addition to the current detecting means 11 corresponding to the hole formed perpendicularly to the horizontal plane of the focus ring, there are respectively arranged current detecting means 35 and 36 for detecting current from the holes formed at angles of ±20° with respect to the hole formed perpendicularly to the horizontal plane of the focus ring. In the embodiment shown in FIG. 1, in order to estimate the incident angle of the ions, it is necessary to acquire the voltage-to-current characteristic shown in FIG. 3 by changing the voltage applied to the focus ring 9. However, the embodiment shown in FIG. 5 has a feature that the incident angle of the ions and the time-based change of the incident angle can be estimated in real time from a ratio of currents detected by the respective current detecting means, without changing the voltage applied to the focus ring.
The present invention relates to a semiconductor device manufacturing apparatus, and more particularly to a plasma etching apparatus which performs etching processing of a semiconductor material by using, as a mask, a pattern drawn by a lithography technique. According to the present invention, it is possible to easily optimize the processing properties in the end portion of the silicon wafer as a sample to be processed, and also possible to suppress the time-based change of the processing properties in the end portion of the silicon wafer due to the wear of the focus ring, or the like. According to the above described effects of the present invention, the acquisition rate of acceptable products in the end portion of the silicon wafer can be increased, so as to thereby improve the yield of the etching apparatus. Also, the focus ring can be used for a long period of time, so as to thereby reduce the cost of consumables.
Patent Application
20100006225
