This application claims the priority benefit of French Application for Patent No. 2204712, filed on May 18, 2022, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.
The present disclosure generally concerns electronic systems and devices and, in particular, their manufacturing methods. The present disclosure more particularly concerns a PN junction manufacturing method.
The manufacturing and the use of ever higher performance electronic systems and devices is a significant issue in today's industry. Further, the miniaturization of electronic systems and devices while keeping their operating performance may be a problem.
It would be desirable to be able to improve, at least partly, known electronic systems and devices, and in particular, their manufacturing methods.
There is a need in the art for higher-performance electronic systems and devices comprising a PN junction.
There is a need in the art for electronic systems and devices comprising an abrupt PN junction.
There is a need in the art for higher-performance electronic device manufacturing methods.
There is a need in the art for higher-performance PN junction manufacturing methods.
There is a need in the art for PN junction manufacturing methods enabling to obtain a more abrupt PN junction.
There is a need in the art for higher-performance diode manufacturing methods.
There is a need in the art for higher-performance bipolar transistor manufacturing methods.
There is a need in the art to overcome all or part of the disadvantages of known electronic device manufacturing methods.
There is a need in the art to overcome all or part of the disadvantages of known diodes.
There is a need in the art to overcome all or part of the disadvantages of known bipolar transistors.
An embodiment provides a PN junction manufacturing method comprising the following successive steps: forming at least one trench in a semiconductor substrate of a first conductivity type; and filling said at least one trench with a semiconductor material of a second conductivity type, different from the first conductivity type.
According to an embodiment, at least two trenches are formed in said substrate.
According to an embodiment, the step of deposition of said material is a furnace deposition step.
According to an embodiment, the step of deposition of said material is an epitaxial deposition step.
Another embodiment provides a diode manufacturing method using the previously-described PN junction manufacturing method.
Another embodiment provides a diode comprising a doped semiconductor substrate of a first conductivity type and at least one first region made of a semiconductor material of a second conductivity type, different from the first conductivity type, wherein said first region has a uniform doping.
According to an embodiment, the diode further comprises at least one second region made of a semiconductor material of a second conductivity type, different from the first conductivity type, wherein said second region has a uniform doping.
According to an embodiment, said substrate comprises at least one doped portion of the first conductivity type having a higher doping level than the other doped substrate portions of the first conductivity type, said portion surrounding said first region.
According to an embodiment, said portion surrounds the assembly of said first and second regions.
Another embodiment provides a bipolar transistor manufacturing method using the previously-described PN junction manufacturing method.
According to an embodiment, the emitter region of said bipolar transistor is formed by using the previously-described PN junction manufacturing method.
According to an embodiment, the collector region of said bipolar transistor is formed by using the previously-described PN junction manufacturing method.
Another embodiment provides a bipolar transistor comprising a doped semiconductor substrate of a first conductivity type and at least one third region made of a semiconductor material of a second conductivity type, different from the first conductivity type, wherein said third region has a uniform doping.
According to an embodiment, the third region is the emitter or the collector of the transistor.
According to an embodiment, the transistor further comprises at least one fourth region made of a semiconductor material of a second conductivity type, different from the first conductivity type, wherein said fourth region has a uniform doping.
According to an embodiment, the fourth region is the emitter or the collector of the transistor.
The foregoing features and advantages, as well as others, will be described in detail in the rest of the disclosure of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:
Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional and material properties.
For the sake of clarity, only the steps and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail.
Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected or they can be coupled via one or more other elements.
In the following disclosure, when reference is made to absolute positional qualifiers, such as the terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc., or to relative positional qualifiers, such as the terms “above”, “below”, “upper”, “lower”, etc., or to qualifiers of orientation, such as “horizontal”, “vertical”, etc., reference is made, unless specified otherwise, to the orientation of the figures.
Unless specified otherwise, the expressions “around”, “approximately”, “substantially” and “in the order of” signify within 10%, and preferably within 5%.
PN junction 100 is formed of a doped semiconductor substrate of a first conductivity type, for example, P-type doped, where are formed at least one, preferably a plurality of, trenches 102 filled with a doped semiconductor material of a second conductivity type different from the first conductivity type, for example, N-type doped.
According to an example, trenches 102 extend from an upper surface 103 of substrate 101. According to an example, trenches 102 have a depth in the range from 700 to 800 nm, and a width in the order of 90 nm.
According to an example, when the first conductivity type is type P, substrate 101 is made of a material selected from the group consisting of: silicon, and semiconductor materials comprising silicon. The material of substrate 101 is doped with dopant elements comprising elements from column 13 of Mendeleev's periodic classification of elements, that is, one or a plurality of elements among the following: boron (B), aluminum (Al), gallium (Ga), indium (In), etc. The material filling trenches 102 is doped with dopant elements comprising elements from column 15 of Mendeleev's periodic classification of elements, that is, one or a plurality of elements among the following: nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), etc. According to another example, the first conductivity type is type N, and the second conductivity type is type P.
According to a practical example, substrate 101 may be made of silicon doped with boron atoms at a dopant concentration in the order of 1.65×1012 atoms/cm3. Trenches 102 may be filled with silicon doped with arsenic atoms at a dopant concentration in the order of 5×1013 atoms/cm3. According to a variant, trenches 102 may be filled with polysilicon doped with phosphorus atoms with a dopant concentration in the order of 2×1020 atoms/cm3. According to another variant, trenches 102 may be filled with a heavily P-type doped material (P+) for example having a dopant concentration in the order of 4×102 atoms/cm3, and the substrate may be made of a heavily N-type doped material (N+), for example having a dopant concentration in the order of 5×1020 atoms/cm3.
PN junction 100 may be used as a conventional diode, it is sufficient for this purpose to install contacting areas accessible on layer 101 and on trenches 102. Thus, according to a first embodiment, PN junction 100 may enable to form a diode comprising a P-type doped substrate having trenches filled with an N-type doped semiconductor material formed therein. According to a second embodiment, PN junction 100 may enable to form a diode comprising an N-type doped substrate having trenches filled with a P-type doped semiconductor material formed therein. In these two embodiments, the substrates may be heavily doped, for example, with doping levels in the range from 1017 to 1018 atoms/cm3.
Further, according to an alternative embodiment, certain portions of substrate 101, such as the substrate portions EXT surrounding all the trenches 102, may be more heavily doped than the rest of substrate 101, such as, for example, the portions of substrate 101 located between trenches 102. According to another variant, all or part of the portions of substrate 101 located between trenches 102 may have a doping level higher than the doping level of the material filling trenches 102.
Those skilled in the art will be capable of envisaging other doping types according to the use made of PN junction 100.
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A layer 201 intended to form a hard mask is deposited on an upper surface 202 of substrate 200. Layer 201 thus enables to protect certain portions of substrate 200, during one or a plurality of manufacturing steps that may follow, such as etch steps and/or steps of deposition of material. Layer 201 may enable to protect one or a plurality of other electronic devices formed inside and/or on top of substrate 200, and may thus enable to co-integrate the PN junction with one or a plurality of other electronic devices. According to an example, layer 201 is a silicon nitride layer (SiN) having a thickness in the range from 60 to 100 nm, for example, in the order of 80 nm.
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According to a first example, material 204 is deposited by implementing a furnace deposition method (Furnace Deposition). According to a second example, material 204 is deposited by implementing an epitaxial growth method. The first example is faster to execute than the second example, but enables to have a sharper PN junction area between the material of substrate 200 and material 204.
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A plurality of methods may be implemented herein to form pads 205. A first method here comprises a deposition on surface 202 of substrate 200 of a polysilicon layer, this deposition is followed by a step of etching, for example, by photolithography, enabling to remove portions of the poly silicon layer at the level of trenches 204. These steps may be followed by a siliciding step, during which a metal layer, for example, a layer made of an alloy of nickel and palladium, is deposited over the entire obtained structure. The material of the metal layer reacts with the polysilicon to form an electrically-conductive silicide, for example, made of NiSi2 if the metal layer is made of a nickel and palladium alloy. The areas where there is no polysilicon remain insulating.
A second method comprises a step of deposition of a silicon oxide layer followed by a photolithography step, enabling to keep portions of the silicon oxide layer, forming pads 205, between the trenches to protect them against short-circuits that may be due to a future siliciding step. In the same way as in the first method, a siliciding step may follow this method. This siliciding step is, for example, identical to that described for the first method.
An advantage of this implementation mode is that it enables to form a sharp and abrupt PN junction. More particularly, PN junctions are conventionally obtained by implantation of dopant elements, which forms a doping gradient and not a sharp junction.
Bipolar transistor 300 is formed inside and on top of a wafer of substrate 301 doped with a first conductivity type, for example, type P. According to an example, substrate wafer 301 is made of P-type doped silicon.
Transistor 300 comprises doped regions 302 and 303 of a second conductivity type different from the first type, for example, type N, forming its emitter and collector regions. According to an embodiment, regions 302 and/or 303 are obtained by the method described in relation with
Transistor 300 further comprises a doped region 304 of the first conductivity type arranged between regions 302 and 303. Region 304 is the base region of transistor 300. Region 304 is, for example, formed by a method of the type of the method described in relation with
Transistor 300 further comprises a cavity 307 formed in layer 301 and extending from the upper surface of layer 301 and from a portion of a lateral surface of regions 302 and 303. According to an example, the cavity has a depth smaller than the depth of regions 302, 303, and 304. Cavity 307 has, in top view, a rectangular ring shape surrounding region 304.
Transistor 300 further comprises a cavity 308 formed in layer 301 and extending from the upper surface of layer 301 and around cavity 307. According to an example, the cavity 308 has a depth smaller than the depth of regions 302, 303, and 304, and a depth in the order of the depth of cavity 307. Cavity 308 has, in top view, a rectangular ring shape surrounding cavity 307 and regions 302, 303, and 304.
Cavities 307 and 308 are optional and may enable to form insulating trenches. According to a variant, a single cavity provided by either cavity 307 or cavity 308 is formed.
Contacting areas 309 are formed on the upper surface of layer 301, and preferably outside of cavities 307 and 308. These contacting areas 309 form substrate (base) contacts of transistor 300.
Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants may be combined, and other variants will occur to those skilled in the art.
Finally, the practical implementation of the described embodiments and variations is within the abilities of those skilled in the art based on the functional indications given hereabove.
Number | Date | Country | Kind |
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2204712 | May 2022 | FR | national |