Patent Application
20070176254
The present invention generally relates to the field of high voltage and high frequency poly emitter bipolar structures, and particularly to a processing method for improving the breakdown voltage (BVcbo) of oxide between the emitter and collector of a poly emitter bipolar structure with an inter-level dielectric (ILD) layer deposited by plasma enhanced chemical vapor deposition (PECVD).
The poly-silicon emitter bipolar has high frequency performance and been used extensively in high frequency low voltage system. Because the poly-silicon emitter bipolar with high frequency performance needs the shallow junction depth and the poly-silicon emitter bipolar with high voltage performance needs deep junction, there is tradeoff between voltage and frequency in high voltage and high frequency poly-silicon emitter bipolar process. In general, some solutions to this problem are found in the silicon semiconductor industry. Choosing high resistivity and thick epitaxy or diffused guard ring, floating guard ring and field plate technique are used to improve breakdown voltage with shallow base junction depth. However, the above methods increase the area of the devices or degrade the performance of the devices.
Referring to
U.S. Pat. No. 6,858,887 issued by Li , et al., entitled “BJT device configuration and fabrication method with reduced emitter width”, discloses a BJT device configuration including an emitter finger and the via arrangement which reduces emitter finger width, and is particularly suitable for use with compound semiconductor-based devices. Each emitter finger includes a cross-shaped metal contact which provides an emitter contact and each contact comprises two perpendicular arms which intersect at a central area. A via through an inter-level dielectric layer provides access to the emitter contact. The via is square-shaped, centered over the center point of the central area, and oriented at a 45 DEG angle to the arms. This allows the via size to be equal to or greater than the minimum process dimension, while allowing the width of the emitter finger to be as narrow as possible with the alignment tolerances still being met. However, the disclosed devices based on compound semiconductors employed for operation at very high frequencies are not feasible, since the high temperature processing is required to fabricate the polycrystalline silicon emitter which is incompatible with the processes needed to fabricate compound semiconductors, and no convenient analog to polysilicon exists in compound semiconductors.
According to the above problems, there is a need to provide a processing method and configuration for improving breakdown voltage of a poly emitter bipolar structure.
It is an objective of the present invention to provide a processing method of improving breakdown voltage (BVcbo) of a poly emitter bipolar structure with poly-silicon emitter and an ILD layer deposited by PECVD.
It is another objective of the present invention to provide a configuration of improving breakdown voltage of a poly emitter bipolar structure with poly-silicon emitter and an ILD layer deposited by PECVD.
To achieve the above and other objectives, the present invention provides a poly emitter bipolar structure with improved breakdown voltage performance. It comprises a semi-insulating substrate; a collector formed on the substrate; a base formed on the collector; an emitter formed on the base; a first metal contact on the collector which provides a collector contact for the poly emitter bipolar structures; a second metal contact on the emitter which provides an emitter contact for the poly emitter bipolar structures; an inter-level dielectric layer deposited by PECVD on the emitter and collector by optimizing PECVD deposition process condition to adjust the charge in the oxide; three via holes through the inter-level dielectric layer which provides access to the collector contact, a base contact and the emitter contact; and a fourth metal deposited to contact the collector contact, the base contact and the emitter contact to be a collector electrode, a base electrode and an emitter electrode of the poly emitter bipolar structures.
According to one aspect of the poly emitter bipolar structures of the present invention, the first metal contact and the second metal contact are formed by polysilicon doped with phosphide ion.
According to the preferred embodiment of the present invention, the breakdown voltage (BVcbo) of oxide between the emitter and collector can be improved from 30V to 45V without changing epitaxy layer thickness, resistivity, and therefore without affecting other device performance.
The present invention also provides a method for fabricating a poly emitter bipolar structure with improved breakdown voltage performance. It comprises the steps of providing a semi-insulating substrate; forming a collector on the substrate; forming a base on the collector; forming an emitter on the base; providing a first metal contact on the collector which provides a collector contact for the poly emitter bipolar structures; providing a second metal contact on the emitter which provides an emitter contact for the poly emitter bipolar structures; depositing an inter-level dielectric layer (ILD) by PECVD on the emitter and collector by optimizing PECVD deposition process condition to adjust the charge in the oxide of inter-level dielectric layer; forming three via holes through the inter-level dielectric layer which provides access to the collector contact, a base contact and the emitter contact; and depositing a fourth metal to contact the collector contact, the base contact and the emitter contact to be a collector electrode, a base electrode and a emitter electrode of the poly emitter bipolar structures.
The advantage of the poly emitter bipolar structures of the present invention is that to change the field deposition SiO2 with PECVD deposition SiO2 instead of traditional LPCVD or LTO SiO2 by optimizing PECVD deposition process condition to adjust the charge in the oxide to meet the device breakdown voltage requirement, the breakdown voltage (BVcbo) of oxide between the emitter and collector can be improved from 30V to 45V without changing epitaxy layer thickness, resistivity, and therefore without affecting other device performance.
The another advantage of the poly emitter bipolar structures of the present invention is that this invention integrate high unit capacitance diode ISO/BN with low breakdown voltage between 6˜8V, high voltage MIS capacitor with poly-silicon as upper plate and Xbase or N+ as lower plate and low forward voltage Schottky diode with PtSi/TiW/AlSiCu.
All the objects, advantages, and novel features of the present invention will become more apparent from the following detailed descriptions when taken in conjunction with the accompanying drawings.
Although the present invention has been explained in relation to several preferred embodiments, the accompanying drawings and the following detailed descriptions are the preferred embodiment of the present invention. It is to be understood that the following disclosed descriptions will be examples of the present invention, and will not limit the present invention into the drawings and the special embodiment.
Referring to
According to the preferred embodiment of the present invention, this invention provides one method to change the field deposition SiO2 with PECVD deposition SiO2 instead of traditional LPCVD or LTO SiO2. By optimizing PECVD deposition process condition to adjust the charge in the oxide to meet the device breakdown voltage requirement, the breakdown voltage (BVcbo) of oxide between the emitter and collector can be improved from 30V to 45V without changing epitaxy layer thickness, resistivity, and therefore without affecting other device performance. So the saturation voltage and cut off frequency performance have been improved. Also this invention integrate high unit capacitance diode ISO/BN with low breakdown voltage between 6˜8V, high voltage MIS capacitor with poly-silicon as upper plate and Xbase or N+ as lower plate and low forward voltage Schottky diode with PtSi/TiW/AlSiCu.
The process sequence depicted in
Although the invention has been explained in relation to its preferred embodiment, it is not used to limit the invention. It is to be understood that many other possible modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention as hereinafter claimed.
