Patent Application
20080001281
Preferred modes of the present invention will now be described in detail with reference to the drawings.
A power amplifier module according to a first example of the present invention will be described with reference to the drawings, in which
The power amplifier module 1 depicted in
The power amplifier chip 15 includes an interstage matching circuit M1 connected between an initial-stage transistor T1 and a final-stage transistor T2. The transistor T1 is constituted by a GaAsHBT or the like, e.g., and has a collector electrically connected to the interstage matching circuit M1 and to bias circuit B1, a base electrically connected to the input matching circuit M2 and electrically connected to a control pad Vctr1 via a resistor, and an emitter electrically connected to a ground pad GND. The transistor T2 is constituted by a GaAsHBT or the like, e.g., and has a collector electrically connected to the output matching circuit M3 and to bias circuit B2, a base electrically connected to the interstage matching circuit M1 and electrically connected to the control pad Vctr1 via a resistor, and an emitter electrically connected to a ground pad GND. The interstage matching circuit M1, which is a matching circuit for fully exploiting the output currents of the transistors T1 and T2, is obtained by combining inductors and capacitors, etc. The interstage matching circuit M1 has a first terminal electrically connected to the collector of transistor T1 and to bias circuit B1, a second terminal electrically connected to the base of transistor T2 and electrically connected to the control pad Vctr1 via a resistor, and a third terminal electrically connected to a ground pad GND. It should be noted that although the interstage matching circuit M1 is implemented in a form in which it is incorporated within the power amplifier chip 15, it may be mounted externally. Further, although the resistors connected to the bases of the transistors T1 and T2, respectively, are implemented in a form in which they are incorporated within the power amplifier chip 15, these may be mounted externally.
The input matching circuit M2, which is a matching circuit mainly for performing impedance matching, is obtained by combining inductor and capacitor, etc. The input matching circuit M2 has a first terminal A electrically connected to an input pad Pin, a second terminal B electrically connected to the base of transistor T1, and a third terminal G1 electrically connected to a ground pad GND.
The output matching circuit M3, which is a matching circuit adapted to furnish a predetermined distortion level while outputting a required power, is obtained by combining inductor and capacitor, etc. The output matching circuit M3 has a first terminal C electrically connected to the base of transistor T2 and to the bias circuit B2, a second D terminal electrically connected to an output pad Pout, and a third terminal G2 electrically connected to a ground pad GND.
The bias circuit B1 is a circuit for supplying the collector of transistor T1 with power Vcc1 and has a first terminal F electrically connected to the collector of transistor T1 and to the interstage matching circuit M1, a second terminal E electrically connected to power pad Vcc1 and a third terminal G3 connected to a ground pad GND. The bias circuit B2 is a circuit for supplying the collector of transistor T2 with power Vcc2 and has a first terminal H electrically connected to the collector of transistor T2 and to the output matching circuit M3, a second terminal G electrically connected to power pad Vcc2 and a third terminal G4 connected to a ground pad GND. The bias circuits B1 and B2 ideally should have a wavelength that is one-fourth the wavelength of the frequency used. However, since such bias circuits usually will not fit in a small module, these bias circuit have a small length such as 1/16 wavelength, actually.
The circuit of the power amplifier module 1 described above is implemented in the structure set forth below according to the instant example.
The power amplifier module 1 is obtained by joining a first LTCC wiring board 10 having the power amplifier chip 15, and a second LTCC wiring board 20 having an input matching circuit and an output matching circuit.
The first LTCC wiring board 10 is a wiring board obtained by alternately stacking alternating layers of an insulating layer comprising a low-temperature co-firable ceramic composition and a wiring layer comprising a highly electrically conductive material such as copper, and electrically connecting the wiring layers by vias. The first LTCC wiring board 10 is provided with a cavity 11 on its top side at the central portion thereof in order to perform the role of a carrier on which the power amplifier chip 15 is placed. The power amplifier chip 15 is mounted in the cavity 11 via an electrically conductive bonding agent (not shown) such as Ag paste. The cavity 11 has such a depth that bonding wires 16 driven into (jointed to) the first LTCC wiring board 10 from the power amplifier chip 15 will not exceed the height of the first LTCC wiring board 10. The gap within the cavity 11 is sealed by an insulating resin 17.
A plurality of vias 12 for assuring dissipation of heat and improving the state of ground are disposed immediately below the power amplifier chip 15 within the first LTCC wiring board 10. For this reason it is difficult to incorporate a matching circuit, which comprises capacitor and inductor, etc., in the first LTCC wiring board 10. The vias 12 are electrically connected to ground pads 14 placed on the bottom side of the first LTCC wiring board 10 (see
A plurality of pads A to G, G1 to G4 for being joined to the second LTCC wiring board 20 as by soldering are disposed along and in the periphery of the edges of the cavity 11 on the top surface of the first LTCC wiring board 10 (see
It should be noted that the degree of freedom of matching usually rises more if the circuitry of the output matching circuit M3 begins at a location as close as possible to the output of the transistor T2 in the power amplifier chip 15. Hence it is preferred that the output matching circuit M3 be placed at a position close to the output pad Pout. Further, in order that the input matching circuit M2 and output matching circuit M3 may prevent the power amplifier from oscillating, it is preferred that the ground pads GND of the respective matching circuits M2, M3 and bias circuits B1, B2 all be grounded by separate wiring and vias.
The first LTCC wiring board 10 has a via (not shown) electrically connected to a ground pad (not shown) of the power amplifier chip 15 via bonding wire 16, and a ground pad (not shown), which is provided on the bottom surface of the substrate, electrically connected to this via.
The second LTCC wiring board 20 is a wiring board obtained by alternately stacking alternating layers of an insulating layer comprising a low-temperature co-firable ceramic composition and a wiring layer comprising a highly electrically conductive material such as copper, and electrically connecting the wiring layers by vias. The input matching circuit M2, output matching circuit M3 and bias circuits B1, B2 are incorporated in the second LTCC wiring board 20. The second LTCC wiring board 20 can construct matching circuits if it has a stacked structure on the order of ten layers.
A plurality of pads A′ to G′, G1′ to G4′ for being joined to the first LTCC wiring board 10 as by soldering are disposed on the bottom surface of the second LTCC wiring board 20 (see
It should be noted that bypass capacitors having a capacitance of, e.g., 1000 pF, usually are provided at the leading ends of the bias circuits B1, B2. However, depending upon the size of the second LTCC wiring board 20, there are cases where it is difficult to incorporate a large capacitance of 1000 pF. In such cases, therefore, the bypass capacitors may be mounted externally. Since techniques that will enable the incorporation of large-capacitance capacitors are now be developed, however, it may be possible to incorporate such capacitor(s) in the future.
In accordance with the first example, it is possible to realize a miniaturized power amplifier module that was difficult to achieve by an extension of the prior art.
A power amplifier module according to a second example of the present invention will now be described. In the power amplifier module according to the second example, the connection between the first LTCC wiring board and the power amplifier chip uses bump-joining instead of bonding wire. As a result, the volume of the cavity can be reduced, a bonding area is no longer necessary and further miniaturization can be achieved.
A power amplifier module according to a third example of the present invention will now be described. In the power amplifier module according to the third example, the power amplifier chip is made one in which a via is provided below the bonding pad and a pad corresponding to this via is provided on the reverse side (underside) of the chip. The power amplifier chip is bump-joined to the first LTCC wiring board. As a result, the volume of the cavity can be reduced, a bonding area is no longer necessary and further miniaturization can be achieved.
As many apparently widely different modes or examples of the present invention can be made without departing from the spirit and scope thereof, it is to be understood that the invention is not limited to the specific examples thereof except as defined in the appended claims.
In a further aspect, the IC module of a stacked layer structure comprises a first wiring board and a second wiring board wiring board, each of which may be a co-fired ceramic wiring board of the stacked layer structure, typically, fired at low-temperature. More particularly, there is provided an IC module comprising: a first wiring board and a second wiring board in a stacked structure, the first wiring board having a cavity in which a heat evolving chip is embedded, and a plurality of vias, which are electrically connected to ground, immediately underlying the heat evolving chip; and the second wiring board being stackedly joined to the first wiring board and incorporating one or both of a plurality of matching circuits and a plurality of bias circuits electrically connected to the heat evolving chip.
It should be noted that other objects, features and aspects of the present invention will become apparent in the entire disclosure and that modifications may be done without departing the gist and scope of the present invention as disclosed herein and claimed as appended herewith.
Also it should be noted that any combination of the disclosed and/or claimed elements, matters and/or items may fall under the modifications aforementioned.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-178100 | Jun 2006 | JP | national |
