The present invention generally relates to metal oxide semiconductor field effect transistor (MOSFET) devices and, in particular, to a power MOSFET with reduced drain current leakage.
Reference is made to
A region 24 doped with a p-type dopant is buried in the substrate 12 at a depth offset from (i.e., below) the front side 14 and positioned extending parallel to the front side 14 on opposite sides of each trench 18. The doped region 24 forms the body (channel) region of the transistor, with the trench 18 passing completely through the doped body region 24 and into the substrate 12 below the doped body region 24. A region 26 heavily doped with an n-type dopant is provided at the front side 14 of the substrate 12 and positioned extending parallel to the front side 14 on opposite sides of each trench 18 and in contact with the top of the doped body region 24. The doped region 26 forms the source of the transistor, with the trench 18 passing completely through the doped source region 26 and further extending, as noted above, completely through the doped body region 24 into the substrate 12 below the doped body region 24.
The side walls and bottom of each trench 18 are lined with an insulating layer 20. For example, the insulating layer 20 may comprise an oxide layer (which, in an embodiment, is thermally grown from the exposed surfaces of the substrate 12 in each trench 18). Each trench 18 is filled by a polysilicon material 22, with the insulating layer 20 insulating the polysilicon material 22 from the substrate 12. The polysilicon material 22 forms the gate of the transistor 10 and the insulating layer 20 is the gate oxide layer.
A stack 30 of layers is formed over each trench 18 and laterally extends on opposite sides of each trench 18 over at least a portion of the doped regions 26 for the source. Each stack 30 comprises a nitride layer 32, and a dielectric region formed by an undoped oxide (for example, tetraethyl orthosilicate (TEOS)) layer 34 and a glass (for example, borophosphosilicate glass (BPSG)) layer 36.
A source metal contact 40 extends through the stack 30 at a position between adjacent trenches 18 to make electrical contact with the doped source regions 26. Each source metal contact 40 extends depthwise into the substrate to pass through the doped source region 26 and into the doped body region 24 (thus providing a body contact for the transistor 10 that is tied to the source). A source metal layer 42 extends over both the stack 30 and the source metal contacts 40 to provide a metal connection to and between all the source metal contacts 40. The stack 30 of layers insulates both the source metal layer 42 and the source metal contacts 40 from the gate (polysilicon region 22). A drain metal layer 44 extends over the back side 16 of the substrate 12 to provide a metal connection to the drain. A gate metal layer (not explicitly shown as it is offset in a direction perpendicular to the cross-section) makes an electrical connection to the gate (polysilicon region 22) in each trench 18, this gate metal layer and electrical connection being schematically shown by dotted line 46.
The transistor 10 could instead be a pMOS type transistor where the substrate 12 and doped source region 16 are both p-type doped and the body region 14 is n-type doped.
Reference is now made to
A region 64 doped with a p-type dopant is buried in the substrate 52 at a depth offset from (i.e., below) the front side 54 and positioned extending parallel to the front side 54 on opposite sides of each trench 58. The doped region 64 forms the body (channel) region of the transistor, with the trench 58 passing completely through the doped body region 64 and into the substrate 52 below the doped body region 64. A region 66 doped with an n-type dopant is provided at the front side 54 of the substrate 52 and positioned extending parallel to the front side 54 on opposite sides of each trench 58 and in contact with the top of the doped body region 64. The doped region 66 forms the source of the transistor, with the trench 58 passing completely through the doped source region 66 and further extending, as noted above, completely through the doped body region 64 into the substrate 52 below the doped body region 64.
The side walls and bottom of each trench 58 are lined with a first insulating layer 60a. For example, the insulating layer 60a may comprise a thick oxide layer. The trench 58 is then filled by a first polysilicon material 62a, with the insulating layer 60a insulating the first polysilicon material 62a from the substrate 52. The polysilicon material 62a is a heavily n-type doped polysilicon material (for example, Phosphorus doped with a doping concentration of 5×1020 at/cm3). During the process for fabricating the transistor 50, an upper portion of the insulating layer 60a (which would be adjacent to both the doped body region 64 and doped region 66) is removed from the trench 58 to expose a corresponding upper portion 61 of the polysilicon material 62a (see,
A stack 70 of layers is formed over the substrate 52 and laterally extends on opposite sides of each trench 58 over at least a portion of the doped regions 66 for the source. Each stack 70 comprises a nitride layer 72, a dielectric region formed by an undoped oxide (for example, tetraethyl orthosilicate (TEOS)) layer 74 and a glass (for example, borophosphosilicate glass (BPSG)) layer 76.
A source metal contact 80 extends through the stack 70 to make electrical contact with each doped source region 66. Each source metal contact 80 extends depthwise into the substrate to pass through the doped source region 66 and into the doped body region 64 (thus providing a body contact for the transistor 50 that is tied to the source). A source metal layer 82 extends over the stack 70 and source metal contacts 80 to provide a metal connection to and between all the source metal contacts 80, with the stack 70 insulating both source metal layer 82 and the source metal contacts 80 from the gate (second polysilicon region 62b). A drain metal layer 84 extends over the back side 56 of the substrate 52 to provide a metal connection to the drain. A gate metal layer (not shown as it is offset in a direction perpendicular to the cross-section) makes an electrical connection to the gate (second polysilicon region 62b) in each trench, this gate metal layer and electrical connection being schematically shown by dotted line 86. A field electrical connection (not explicitly shown) is provided between the source and the remaining lower portion of the polysilicon material 62a which forms the field plate (polysource region) electrode that is electrically insulated from the gate.
The transistor 50 could instead be a pMOS type transistor where the polysilicon material 62a is a heavily p-type doped polysilicon material, the substrate 52 and doped source region 56 are both p-type doped and the body region 54 is n-type doped.
A scanning electron micrograph (SEM) cross-sectional image of a single cell of the transistor 50 is shown in
Because the polyoxide region 68 is thermally grown from the heavily n-type doped polysilicon material 62a, this oxide will be heavily doped with the n-type dopants used to dope the polysilicon material 62a. For example, in the implementation described above, the oxide would be heavily doped with Phosphorus atoms, and the polyoxide region 68 can then include un-oxidized (or oxygen deficient) Phosphorus ions. These ions act as a sink for Oxygen atoms that are released from the Silicon-Silicon Oxide interface (which is located at the edge of each trench where the insulating layer 60a is in contact with the substrate 52) during transistor fabrication processes that use high temperatures. As a result, there is an unacceptable increase in the interface charge density. This is disadvantageous because the density of interface charge is critical for controlling IDSS (i.e., drain current at a near body-drain breakdown voltage with source-gate shorted) current leakage level. The density of interface charge disrupts the electric field in the mesa region 53 of the transistor 50 structure, this mesa region including at least the portion of the substrate 52 and the portion of the doped region 64 that is located between adjacent trenches. This disruption is shown by the simulation of interface charge density to electric field in
There is accordingly a need in the art to address concerns with IDSS current leakage in power MOSFET devices.
In an embodiment, an integrated circuit MOSFET device comprises: a substrate providing a drain; a first doped region buried in the substrate providing a body; a second doped region in the substrate providing a source, wherein the second doped region is adjacent the first doped region; a trench extending into the substrate and passing through first and second doped regions; a polyoxide region within the trench; a first conductive region within the trench providing a gate, wherein the first conductive region is adjacent to the polyoxide region; and a stack of layers extending over the first conductive region and polyoxide region within the trench. The stack of layers includes: a first ozone-assisted sub-atmospheric pressure thermal chemical vapor deposition (O3 SACVD) TEOS layer; and a second O3 SACVD TEOS layer; wherein the first and second O3 SACVD TEOS layers are separated from each other by a dielectric region.
In an embodiment, a method of making an integrated circuit device comprises: forming a trench in a substrate which includes a first polysilicon material doped with a dopant; oxidizing a portion of the first polysilicon material to form a polyoxide region within the trench, said polyoxide region including un-oxidized dopant ions; producing a stack of layers extending over the trench, wherein the stack includes: a first ozone-assisted sub-atmospheric pressure thermal chemical vapor deposition (O3 SACVD) TEOS layer; and a second O3 SACVD TEOS layer; wherein the first and second O3 SACVD TEOS layers are separated from each other by a dielectric region; performing a thermal anneal at a temperature which induces outgassing of passivation atoms from the first and second O3 SACVD TEOS layers to migrate to passivate interface charges due to the presence of un-oxidized dopant ions in the polyoxide region.
In an embodiment, a method of making an integrated circuit comprises: forming a polysilicon region that is doped with a dopant; converting a portion of the polysilicon region to a polyoxide region which includes un-oxidized dopant ions; applying a stack of layers over the polyoxide region, wherein the stack of layers includes: a first ozone-assisted sub-atmospheric pressure thermal chemical vapor deposition (O3 SACVD) TEOS layer; and a second O3 SACVD TEOS layer; wherein the first and second O3 SACVD TEOS layers are separated from each other by a dielectric region; thermally annealing at a temperature which induces outgassing of passivation atoms from the first and second O3 SACVD TEOS layers to migrate to passivate interface charges due to the presence of un-oxidized dopant ions in the polyoxide region.
In an embodiment, an integrated circuit comprises: a substrate including a polyoxide region; and a stack of layers extending over the polyoxide region in the substrate, wherein the stack of layers includes: a first ozone-assisted sub-atmospheric pressure thermal chemical vapor deposition (O3 SACVD) TEOS layer; and a second O3 SACVD TEOS layer; wherein the first and second O3 SACVD TEOS layers are separated from each other by a dielectric region.
For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:
Reference is now made to
A region 114 doped with a p-type dopant is buried in the substrate 102 at a depth offset from (i.e., below) the front side 104 and positioned extending parallel to the front side 104 on the opposite sides of each trench 108. The doped region 114 forms the body (channel) region of the transistor, with the trench 108 passing completely through the doped body region 114 and into the substrate 102 below the doped body region 114. A region 116 doped with an n-type dopant is provided at the front side 104 of the substrate 102 and positioned extending parallel to the front side 104 on opposite sides of each trench 108 and in contact with the top of the doped body region 114. The doped region 116 forms the source of the transistor, with the trench 108 passing completely through the doped source region 116 and further extending, as noted above, completely through the doped body region 114 into the substrate 102 below the doped body region 114.
The side walls and bottom of each trench 108 are lined with a first insulating layer 110a. For example, the insulating layer 110a may comprise a thick oxide layer. The trench 108 is then filled by a first polysilicon material 112a, with the insulating layer 110a insulating the first polysilicon material 112a from the substrate 102. The polysilicon material 112a is a heavily n-type doped polysilicon material (for example, Phosphorus doped with a doping concentration of 5×1020 at/cm3). During the process for fabricating the transistor 100 (see, for example,
A stack 120 of layers is formed over the substrate and laterally extends on opposite sides of each trench 108 over at least a portion of the doped regions 116 for the source. The layers of the stack 120 include: a first ozone-assisted sub-atmospheric pressure thermal chemical vapor deposition (O3 SACVD) TEOS layer 121, a nitride layer 122, an undoped oxide (for example, TEOS) layer 124, a glass (for example, BPSG) layer 126 and a second O3 SACVD TEOS layer 127. The undoped oxide layer 124 and a glass layer 126 form a dielectric region of the stack 120. The first and second O3 SACVD layers 121 and 127 are thin layers each having thicknesses on the order of 10-100,000 Angstroms. In an embodiment, the first O3 SACVD layer 121 may have a thickness of about 200 Angstroms and the second O3 SACVD layer 127 may have a thickness of about 3000 Angstroms. For comparison purposes, the nitride layer 122 may, for example, have a thickness on the order of about 700 Angtroms, the undoped oxide layer 124 may have a thickness of about 2000 Angstroms, and the glass layer 126 may have a thickness of about 5000 Angstroms.
A source metal contact 130 extends through the layers of the stack 120 at positions for making electrical contact with the doped source regions 116. Each source metal contact 130 extends depthwise into the substrate to pass through the doped source region 116 and into the doped body region 114 (thus providing a body contact for the transistor 100 that is tied to the source). A source metal layer 132 extends over the stacks 120 and source metal contacts 130 to provide a metal connection to and between all the source metal contacts 130, with the stack 120 of layer insulating both source metal layer 132 and the source metal contacts 130 from the gate (second polysilicon region 112b). A drain metal layer 134 extends over the back side 106 of the substrate 102 to provide a metal connection to the drain. A gate metal layer (not shown as it is offset in a direction perpendicular to the cross-section) makes an electrical connection to the gate (second polysilicon region 112b) in each trench, this gate metal layer and electrical connection being schematically shown by dotted line 136. A field electrical connection (not explicitly shown) is provided between the source and the remaining lower portion of the polysilicon material 112a which forms the field plate (polysource region) electrode.
A scanning electron micrograph (SEM) cross-sectional image of a single cell of the transistor 100, focusing on the area of the gate and stack, is shown in
It will be noted that O3 TEOS as used in layers 121 and 127 belongs to a silanol group which belongs to the functional group in silicon chemistry with the connectivity of Si—O—H. When subjected to a high temperature anneal, the phenomena of desorption of water and Hydrogen occurs providing for an outgassing of Hydrogen atoms. See, Li, et al., “Hydrogen outgassing induced liner/barrier reliability degradation in through silicon via's”, Appl. Phys. Lett. 104, 142906 (2014); and Hirashita, et al., “Thermal Desorption and Infrared Studies of Plasma-Enhanced Chemical Vapor Deposited SiO Films with Tetraethylorthosilicate”, Japanese Journal of Applied Physics, Volume 32, Part 1, Number 4 (1993). This outgassed Hydrogen is advantageously used for the transistor 100 in the passivation of the interface charges due to the presence of the Phosphorus ions.
Reference is now made to
It will also be noted that the presence of both the first and second O3 SACVD layers 121 and 127 in the stack 120 is needed in order to achieve the beneficial reduction in leakage level as shown in
Although the example of
While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.
This application claims priority from U.S. Provisional Application for Patent No. 63/030,642 filed May 27, 2020, the disclosure of which is incorporated by reference.
Number | Date | Country | |
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63030642 | May 2020 | US |