Patent Application
20240213343
This specification refers to embodiments of a power semiconductor device and to embodiments of a method of producing a power semiconductor device. In particular, this specification refers to an IGBT with an internal gate resistor and a corresponding production method.
Many functions of modern devices in automotive, consumer and industrial applications, such as converting electrical energy and driving an electric motor or an electric machine, rely on power semiconductor devices. For example, Insulated Gate Bipolar Transistors (IGBTs), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and diodes, to name a few, have been used for various applications including, but not limited to switches in power supplies and power converters.
A power semiconductor device usually comprises a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device. The load current is typically conducted by means of an active region of the power semiconductor device. The active region is typically surrounded by an edge termination region, which is terminated by an edge of the chip.
In case of a controllable power semiconductor device, e.g., a transistor, the load current path may be controlled by means of an insulated electrode, commonly referred to as gate electrode. For example, upon receiving a corresponding control signal, e.g., from a driver unit via a control terminal of the device, the control electrode may set the power semiconductor device in one of a forward conducting state and a blocking state.
Such switching operations may be influenced, e.g., in terms of switching speed, such as turn-on durations and/or turn-off durations, based on the ohmic resistance of the transmission path relevant for the control signal. Said ohmic resistance is typically referred to as gate resistance and, correspondingly, said relevant transmission path is typically referred to as gate resistor. The gate resistor may be divided in an external part and a part integrated in the controllable power semiconductor device chip.
As the gate resistor, in particular its gate resistance, influences the switching operations of the device, it is a typical design goal to configure the gate resistor with a specific gate resistance to provide the device with defined device characteristics. Further, the gate resistor should be designed to not jeopardize the device reliability and with little area consumption to achieve a high power/area ratio.
The subject-matter of the independent claims is presented. Features of exemplary embodiments are defined in the dependent claims.
According to an embodiment, a power semiconductor device comprises: a semiconductor body coupled to a first load terminal at a first side and to a second load terminal at a second side that is opposite to the first side with respect to a vertical direction; an active region comprising a portion of the semiconductor body and configured to conduct a load current between the first load terminal and the second load terminal, wherein the active region is surrounded by an edge termination region; a gate terminal at the first side configured to receive a control signal for controlling the load current; a first region in the active region comprising a plurality of first trenches, each first trench including a first trench electrode electrically connected to the gate terminal and a first trench insulator electrically isolating the first trench electrode from the semiconductor body; a second region comprising a plurality of second trenches, each second trench including a second trench electrode electrically connected to the gate terminal and a second trench insulator electrically insulating the second trench electrode from the semiconductor body, wherein at least one of the following applies: a) a minimal thickness of each second trench insulator amounts to at least 120% of a corresponding minimal thickness of each first trench insulator; b) an average thickness of the second trench insulators amounts to at least 120% of an average thickness the first trench insulator; c) a thickness of each second trench insulator at the bottom of the respective second trench amounts to at least 120% of a corresponding thickness of each first trench insulator at the bottom of the respective first trench; d) a minimal breakdown voltage of each second trench insulator amounts to at least 120% of a minimal breakdown voltage of each first trench insulator.
According to a further embodiment, a method of producing a power semiconductor device is presented, wherein the method includes forming the following components: a semiconductor body coupled to a first load terminal at a first side and to a second load terminal at a second side that is opposite to the first side with respect to a vertical direction; an active region comprising a portion of the semiconductor body and configured to conduct a load current between the first load terminal and the second load terminal, wherein the active region is surrounded by an edge termination region; a gate terminal at the first side configured to receive a control signal for controlling the load current; a first region in the active region comprising a plurality of first trenches, each first trench including a first trench electrode electrically connected to the gate terminal and a first trench insulator electrically isolating the first trench electrode from the semiconductor body; a second region comprising a plurality of second trenches, each second trench including a second trench electrode electrically connected to the gate terminal and a second trench insulator electrically insulating the second trench electrode from the semiconductor body, and wherein at least one of the following applies: a) a minimal thickness of each second trench insulator amounts to at least 120% of a corresponding minimal thickness of each first trench insulator; b) an average thickness of the second trench insulators amounts to at least 120% of an average thickness the first trench insulator; c) a thickness of each second trench insulator at the bottom of the respective second trench amounts to at least 120% of a corresponding thickness of each first trench insulator at the bottom of the respective first trench; d) a minimal breakdown voltage of each second trench insulator amounts to at least 120% of a minimal breakdown voltage of each first trench insulator.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
The parts in the FIGURES are not necessarily to scale, instead emphasis is being placed upon illustrating principles of the invention. Moreover, in the FIGURES, like reference numerals designate corresponding parts. In the drawings:
In the following detailed description, reference is made to the accompanying drawings which form a part hereof and in which are shown by way of illustration specific embodiments in which the invention may be practiced.
In this regard, directional terminology, such as “top”, “bottom”, “below”, “front”, “behind”, “back”, “leading”, “trailing”, “above” etc., may be used with reference to the orientation of the FIGURES being described. Because parts of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the FIGURES. Each example is provided by way of explanation, and is not meant as a limitation of the invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appended claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated by the same references in the different drawings if not stated otherwise.
The term “horizontal” as used in this specification intends to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or of a semiconductor structure. This can be for instance the surface of a semiconductor wafer or a die or a chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below can be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.
The term “vertical” as used in this specification intends to describe an orientation which is substantially arranged perpendicular to the horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor wafer/chip/die. For example, the extension direction Z mentioned below may be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y. The extension direction Z is also referred to as “vertical direction Z” herein.
In this specification, n-doped is referred to as “first conductivity type” while p-doped is referred to as “second conductivity type”. Alternatively, opposite doping relations can be employed so that the first conductivity type can be p-doped and the second conductivity type can be n-doped.
In the context of the present specification, the terms “in ohmic contact”, “in electric contact”, “in ohmic connection”, and “electrically connected” intend to describe that there is a low ohmic electric connection or low ohmic current path between two regions, sections, zones, portions or parts of a semiconductor device or between different terminals of one or more devices or between a terminal or a metallization or an electrode and a portion or part of a semiconductor device, wherein “low ohmic” may mean that the characteristics of the respective contact are essentially not influenced by the ohmic resistance. Further, in the context of the present specification, the term “in contact” intends to describe that there is a direct physical connection between two elements of the respective semiconductor device; e.g., a transition between two elements being in contact with each other may not include a further intermediate element or the like.
In addition, in the context of the present specification, the term “electric insulation” is used, if not stated otherwise, in the context of its general valid understanding and thus intends to describe that two or more components are positioned separately from each other and that there is no ohmic connection connecting those components. However, components being electrically insulated from each other may nevertheless be coupled to each other, for example mechanically coupled and/or capacitively coupled and/or inductively coupled and/or electrostatically coupled (for example, in case of a junction). To give an example, two electrodes of a capacitor may be electrically insulated from each other and, at the same time, mechanically and capacitively coupled to each other, e.g., by means of an insulation, e.g., a dielectric.
Specific embodiments described in this specification pertain to, without being limited thereto, a power semiconductor device, e.g., a power semiconductor device that may be used within a power converter or a power supply. Thus, in an embodiment, such device can be configured to carry a load current that is to be fed to a load and/or, respectively, that is provided by a power source. For example, the power semiconductor device may comprise one or more active power semiconductor unit cells, such as a monolithically integrated diode cell, a derivative of a monolithically integrated diode cell (e.g., a monolithically integrated cell of two anti-serially connected diodes), a monolithically integrated transistor cell, e.g., a monolithically integrated MOSFET or IGBT cell and/or derivatives thereof. Such diode/transistor cells may be integrated in a power semiconductor module. A plurality of such cells may constitute a cell field that is arranged within an active region of the power semiconductor device.
The term “blocking state” of the power semiconductor device may refer to conditions, when the semiconductor device is in a state configured for blocking a current flow through the semiconductor device, while an external voltage is applied. More particularly, the semiconductor device may be configured for blocking a forward current through the semiconductor device while a forward voltage bias is applied. In comparison, the semiconductor may be configured for conducting a forward current in a “conducting state” of the semiconductor device, when a forward voltage bias is applied. A transition between the blocking state and the conducting state may be controlled by a control electrode or, more particularly, a potential of the control electrode. Said electrical characteristics may, of course, only apply within a predetermined working range of the external voltage and the current density within the device. The term “forward biased blocking state” therefore may refer to conditions with the semiconductor device being in the blocking state while a forward voltage bias is applied.
The term “power semiconductor device” as used in this specification intends to describe a semiconductor device on a single chip with high voltage blocking and/or high current-carrying capabilities. In other words, such power semiconductor device is intended for high current, typically in the Ampere range, e.g., up to several ten or several hundred Ampere, and/or high voltages, typically above 15 V, more typically 100 V and above, e.g., up to at least 400 V or even more, e.g., up to at least 3 kV, or even up to 10 kV or more, depending on the respective application.
For example, the term “power semiconductor device” as used in this specification is not directed to logic semiconductor devices that are used for, e.g., storing data, computing data and/or other types of semiconductor based data processing.
The present specification in particular relates to a power semiconductor device embodied as a diode, a MOSFET or IGBT, i.e., a unipolar or bipolar power semiconductor transistor or diode or a derivate thereof, such as an RC IGBT.
For example, the power semiconductor device described below may be a single semiconductor chip, e.g., exhibiting a stripe cell configuration (or a cellular/needle cell configuration) and can be configured to be employed as a power component in a low-, medium- and/or high voltage application.
Accordingly, the power semiconductor device 1 comprises a semiconductor body 10 coupled to a first load terminal at a first side 110 and to a second load terminal at a second side 120 that is opposite to the first side 110 with respect to a vertical direction.
The power semiconductor device 1 may thus exhibit a vertical configuration according to which the load current flows substantially in parallel to the vertical direction Z.
The load terminals at the first and second side 110, 120 are not illustrated herein. E.g., the first load terminal may be a source (or emitter) terminal, and the second load terminal a drain (collector) terminal, e.g., in case of the power semiconductor device 1 being embodied as an IGBT.
The power semiconductor device 1 further comprises an active region 1-1 comprising a portion of the semiconductor body 10 and configured to conduct said load current between the first load terminal and the second load terminal, wherein the active region 1-1 is surrounded by an edge termination region 1-3 which in turn is terminated by a chip edge 1-4. Herein, the terms “active region” (sometimes also referred to as “cell field”), “edge termination region” and “chip edge” have the technical meanings the skilled person typically associates therewith in the context of power semiconductor devices such as IGBTs and MOSFETs and are hence not explained in further detail.
The power semiconductor device 1 further comprises a gate terminal 13 at the first side 110 configured to receive a control signal for controlling the load current. For example, the gate terminal 13 is a so-called gate pad. The gate terminal 13 may be contacted by a contact means, e.g., a bond wire, which may be electrically to an output of a driver unit providing the control signal.
The power semiconductor device 1 further comprises a first region 1-11—in the active region 1-1 comprising a plurality of first trenches 14 (cf.
As illustrated in
The power semiconductor device 1 further comprises a second region 1-2 comprising a plurality of second trenches 15. Each second trench includes a second trench electrode 151 electrically connected to the gate terminal 13 and a second trench insulator 152 electrically insulating the second trench electrode 151 from the semiconductor body 10. The power semiconductor device 1 may optionally comprise further trenches. The further trenches may comprise floating trenches with a trench electrode having a floating potential and/or source trenches being connected to source potential.
The second region 1-2 may or may not form a portion of the active region 1-1. The second region 1-2 may partially or entirely be a part of the active region 1-1. In another embodiment, the second region 1-2 is not part of the active region 1-1. In the latter case, for example, the second region 1-2 is not equipped with any channel structures for load current conduction.
For example, the second region 1-2—which may be a contiguous region or a spatially distributed region (as exemplarily illustrated in
For example, the gate runner 13-1 is connected to the gate terminal 13 only via one or more of the second trench electrodes 151. For example, all of the first trench electrodes are connected to the gate runner 13-1. For example, all of the first trench electrodes 141 are connected to the gate terminal 13 via the gate runner 13-1. The gate runner 13-1 may be interposed between the first gate electrodes 141 and the second trench electrodes 151. For example, the connection may be in the following order: Gate terminal 13—second trench electrodes 151—gate runner 13-1—first trench electrodes 141 (cf.
The second trenches 15 may exhibit dimensions, in terms of width and depth, comparable to the dimension of the first trenches 14 (with optional differences, as described below). As the first trenches 14, the second trenches 15 may extend from the first side 110 along the vertical direction Z towards the second side 120 (cf.
In an embodiment, the second trench electrodes 151 are connected downstream with respect to the gate terminal 13 and upstream with respect to the first trench electrodes 141. That is, the design of the second trenches 15 influences the effective gate resistance. As the gate resistance is in particular influenced by the design of the second trench electrodes 151, the gate resistor of the power semiconductor device 1 may be regarded as an internal gate resistor. As mentioned above, the gate resistor may comprise a part external and an internal part. The internal gate resistor may represent the internal part of the gate resistor. The internal gate resistor may, optionally, be accompanied by an external gate resistor connected in series. The internal gate resistor may connect the gate terminal 13 and the first trench electrodes 141.
In an embodiment, at least one of the following applies:
As indicated above, one, two or more than two of the features a) to d) may be implemented for the power semiconductor device 1.
The above-described embodiment includes the recognition that the internal gate resistors based on trench electrodes may be subjected to comparatively higher transient voltages compared to the trenches 14, in particular at the bottom of the trench. Therefore, even though efficient in terms of processing complexity, forming the second trenches 15 identical to the first trenches 14, may be inappropriate. Rather, due to the possibly higher transient voltages, the second trench insulator 152 should be designed to exhibit better isolation as compared to the first trench insulator 142.
In the following, further optional features of the power semiconductor device 1 will be described, wherein reference is made to each of
The power semiconductor device 1 may be a bipolar semiconductor device, e.g., an IGBT (wherein the IGBT can be, without being limited thereto, an npnp IGBT with an n-inversion channel or a pnpn IGBT with an p-inversion channel) or an RC IGBT. Thus, the drift region may be of the first conductivity type and for example extend along the vertical direction Z until adjoining, either directly or via a field stop layer, a collector region (not illustrated) of the second conductivity type, wherein said collector region can be electrically connected to the second load terminal. If configured, for example, as an RC IGBT, the device 1 may further comprise one or more second emitter regions (not illustrated) of the first conductivity type, wherein said second emitter region(s) can be electrically connected to the second load terminal.
As already indicated above, in an embodiment, the first trench electrodes 141 are electrically connected to the gate terminal 13 at least via the second trench electrodes 151. That is, the second trench electrodes 151 may serve as internal gate resistor.
The total extension of the first region 1-11 may be greater than the total extension of the second region 1-2. For example, the first region 1-11 (which is part of the active region 1-1) has a total horizontal area amounting to at least 70% of the total horizontal area of the active region 1-1. In an embodiment, the active region 1-1 may even consist of the first region 1-11, in which case the total horizontal areas would be of identical size. Furthermore, the second region 1-2 can have a total horizontal area corresponding to at least 5% of the total horizontal area of the active region 1-1. In case the second region 1-2 does not or only partially contribute to the active region 1-1, i.e., to a portion of the device 1 used for load current conduction, a typical design goal would be to keep the second region 1-2 as small as possible so as to no “waste” any volume that could be used for the active region. Hence, in an embodiment, the second region 1-2 can have a total horizontal area corresponding to no more than 1% of the total horizontal area of the active region 1-1.
As also already indicated above, the first region 1-11 can be configured, at least based on the first trench electrodes 141, for controlling the load current. To this end, adjacent to each or at least some of the first trenches, said channel structures may be implemented. By contrast, the second region 1-2 must not necessarily be designed for load current conduction and may hence be configured without any semiconductor source region.
Rather, in an embodiment, the second region 1-2 is configured, based on the second trench electrodes 151, to form a specific internal gate resistor. Based on the specific internal gate resistor, the power semiconductor device may be provided with specific switching characteristics and, due to the “thicker”/“stronger” second trench insulator 152, with improved reliability.
In each of the first trenches 14 and the second trenches 15, the first trench insulator 142 or, respectively, the second trench insulator 152 may exhibit a thickness that is preferably symmetric with respect to center vertical plane. This optional aspect is illustrated in
Furthermore, in an embodiment, in each of the first trenches 14 and the second trenches 15, the first trench insulator 142 or, respectively, the second trench insulator 152 exhibits an at least essentially constant thickness both at the trench sidewalls 1422; 1522 and at the trench bottom 1421; 1521. An at least essentially constant thickness may be defined as a constant thickness with only small (e.g. process-induced) variations of less than 10% or even less than 5% along the trench sidewall. This variant is illustrated in
In an embodiment, cf.
Furthermore, in an embodiment, an average depth D2 of the second trenches 15 along the vertical direction Z is within a range of 85% to 115% or within a range of 95% to 105% of an average depth D1 of the first trenches 14 along the vertical direction Z. In other words, the second trenches 15 may exhibit the substantially same total vertical extension as the first trenches 14. Likewise, the second trench electrodes 151 may exhibit the substantially same total vertical extension as the first trench electrodes 141, wherein in the embodiment illustrated in
In an embodiment, the power semiconductor device 1 is devoid of a gate resistor external of the path between the gate terminal 13 and the first trench electrodes 141. Said path in particular includes the second trench electrodes 151. For example, the device 1 is not equipped with another additional gate resistor external of this path. Rather, the gate resistance is predominantly formed by the second trench electrodes 151.
Both the first trench electrodes 141 and the second trench electrodes 151 may comprise or consist of poly-crystalline silicon, Si. The first trench insulators 142 may comprise a thermally grown oxide, e.g., silicon oxide, SiO2, and may exhibit a thickness in the range of 10 nm to 200 nm. The second trench insulators 152 comprise a deposited oxide, e.g., silicon oxide, nitride, oxynitride, tetraethoxysilane, TEOS, and may exhibit a thickness greater than 200 nm or greater than 250 nm.
The first trench insulator 142 can comprise more than one layer, e.g., two or more layers of different materials. The second trench insulator 152 can comprise more than one layer, e.g., two or more layers of different materials.
In an embodiment, the first region 1-11 does not comprise any second trench 15. Additionally or alternatively, the second region 1-2 does not comprise any first trench 14.
In a further non-illustrated embodiment, the power semiconductor device comprises a plurality of second regions 1-2. For example, the second regions 1-2 differ in the total gate resistance formed by the respective second region. Furthermore, a first subset of the first trench electrodes 141 may be connected with the gate terminal 13 via a first one of the second regions 1-2, a second subset of the first trench electrodes 141 may be connected with the gate terminal 13 via a second one of the second regions 1-2, and so on. Thereby, different subregions of the first regions 1-11 may be controlled based on the same control signal, wherein the subregions differ from each other in their switching characteristics due to the different gate resistances formed by the second regions 1-2.
Presented herein are also methods of producing a power semiconductor device.
According to a further embodiment, a method of producing a power semiconductor device is presented, wherein the method includes forming the following components: a semiconductor body coupled to a first load terminal at a first side and to a second load terminal at a second side that is opposite to the first side with respect to a vertical direction; an active region comprising a portion of the semiconductor body and configured to conduct a load current between the first load terminal and the second load terminal, wherein the active region is surrounded by an edge termination region; a gate terminal at the first side configured to receive a control signal for controlling the load current; a first region in the active region comprising a plurality of first trenches, each first trench including a first trench electrode electrically connected to the gate terminal and a first trench insulator electrically isolating the first trench electrode from the semiconductor body; a second region comprising a plurality of second trenches, each second trench including a second trench electrode electrically connected to the gate terminal and a second trench insulator electrically insulating the second trench electrode from the semiconductor body, and wherein at least one of the following applies: a) a minimal thickness of each second trench insulator amounts to at least 120% of a corresponding minimal thickness of each first trench insulator; b) an average thickness of the second trench insulators amounts to at least 120% of an average thickness the first trench insulator; c) a thickness of each second trench insulator at the bottom of the respective second trench amounts to at least 120% of a corresponding thickness of each first trench insulator at the bottom of the respective first trench; d) a minimal breakdown voltage of each second trench insulator amounts to at least 120% of a minimal breakdown voltage of each first trench insulator.
Embodiments of the method described above correspond to the embodiments of the power semiconductor device 1 described above. In so far, it is referred to the aforesaid.
In an example, forming the first trenches 14 and the second trenches 15 includes a joint trench etch processing step based on a lithographic mask including openings of different widths. Thereby, the second trenches 15 can be provided with the larger trench width W2.
Furthermore, forming the first trench electrodes 141 and the second trench electrodes 151 may include a joint electrode material deposition processing step or two separate electrode material deposition processing steps.
E.g., referring to
Regarding
Referring to
In the above, embodiments pertaining to power semiconductor device, such as MOSFETs, IGBTs, RC IGBTs and derivatives thereof, and corresponding processing methods were explained. For example, these power semiconductor devices are based on silicon (Si). Accordingly, a monocrystalline semiconductor region or layer, e.g., the semiconductor body and its regions/zones, e.g., regions etc. can be a monocrystalline Si-region or Si-layer. In other embodiments, polycrystalline or amorphous silicon may be employed.
It should, however, be understood that the semiconductor body and its regions/zones can be made of any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include, without being limited thereto, elementary semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe) to name few. The aforementioned semiconductor materials are also referred to as “homojunction semiconductor materials”. When combining two different semiconductor materials a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, without being limited thereto, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x) and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switches applications currently mainly Si, SiC, GaAs and GaN materials are used.
Spatially relative terms such as “under”, “below”, “lower”, “over”, “upper” and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the respective device in addition to different orientations than those depicted in the FIGURES. Further, terms such as “first”, “second”, and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms may refer to like elements throughout the description.
As used herein, the terms “having”, “containing”, “including”, “comprising”, “exhibiting” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features.
With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102022214248.9 | Dec 2022 | DE | national |
