Patent Application
20240274660
The present invention relates to semiconductor devices and, more particularly, to power semiconductor devices having semiconductor die with non-rectangular shapes.
Semiconductor devices are often used in applications where the semiconductor device must pass large current levels in their “on” state and block large voltages in their reverse blocking or “off” state. For example, there is demand for Metal Oxide Semiconductor Field Effect Transistors (“MOSFETs”) that can pass tens or even hundreds of Amps of current in their on state and block hundreds or even thousands of volts in their reverse blocking state. In order to support large current densities and block such high voltages, power MOSFETs and other power semiconductor devices such as power Junction Barrier Schottky (“JBS”) diodes, Insulated Gate Bipolar Junction Transistors (“IGBTs”), Junction Field Effect Transistors (“JFETs”), gate-controlled thyristors, and the like typically have a vertical structure with at least one contact on each of the two opposed sides of a thick semiconductor layer structure. Herein, the term “semiconductor layer structure” refers to a structure that includes one or more semiconductor layers, such as semiconductor substrates and/or semiconductor epitaxial layers.
The semiconductor layer structure of a power semiconductor device typically includes an “active region” that has one or more functional semiconductor devices that have a junction such as a p-n junction. The active region acts as a main junction for blocking voltage during reverse bias operation and providing current flow during forward bias operation. The power semiconductor device may also have an edge termination structure in a termination region of the semiconductor layer structure such as a series of guard rings or a Junction Termination Extension (“JTE”). The edge termination structure may be designed to reduce the build-up of electric field concentration that otherwise naturally occurs along the edges of a semiconductor die during device operation. The termination region may surround the active region when the semiconductor die is viewed in plan view. Herein, a “plan view” of a semiconductor die refers to a view of the semiconductor die that is taken along an axis that is perpendicular to a center of a major surface of the semiconductor layer structure of the semiconductor die. The plan view is typically a view of the top surface of the semiconductor die.
Multiple power semiconductor devices are usually formed on a wafer, which refers to a relatively large substrate which is typically formed of a semiconductor material such as 4H silicon carbide. A plurality of semiconductor epitaxial layers are grown or otherwise formed on the wafer to form a semiconductor layer structure. Each power semiconductor device grown on the wafer will typically have an active region and its own edge termination. After the semiconductor layer structure is formed and additional processing steps are completed (e.g., deposition of metal layers), the resultant structure may be diced to separate the individual edge-terminated power semiconductor die. Each power semiconductor die may have a unit cell structure in which the active region of each power semiconductor die includes a plurality of individual “unit cell” devices that are electrically connected in parallel. The power semiconductor die may then be packaged to provide a plurality of power semiconductor devices.
In very high power applications, power semiconductor devices are typically formed in wide band-gap semiconductor material systems (herein, the term “wide band-gap semiconductor” encompasses any semiconductor having a band-gap of at least 1.4 eV) such as, for example, silicon carbide, which has a number of advantageous characteristics including, for example, a high electric field breakdown strength, high thermal conductivity, high electron mobility, high melting point and high-saturated electron drift velocity. Relative to devices formed in other semiconductor materials such as, for example, silicon, electronic devices formed in silicon carbide may have the capability of operating at higher temperatures, at high power densities, at higher speeds, at higher power levels and/or under higher radiation densities
Silicon carbide based power devices offer a number of performance benefits, including high voltage blocking, low on-resistance, high current carrying capabilities, fast switching speeds, low switching losses and the ability to withstand high junction temperatures. These characteristics result in a notable increase in potential power density, which is power processed per area or volume.
Pursuant to some embodiments of the present invention, semiconductor devices are provided that comprise a semiconductor die that comprises a substrate that has a hexagonal crystal structure, where first and second sides of the semiconductor die extend along respective first and second crystallographic axes of the hexagonal crystal structure of the substrate.
In some embodiments, the first side and the second side meet to define an interior angle that is an obtuse angle.
In some embodiments, the semiconductor die comprises at least five sides when viewed in plan view. In some embodiments, the semiconductor die has a hexagon shape when viewed in plan view. In some embodiments, the semiconductor die has an irregular polygon shape when viewed in plan view. In some embodiments, the semiconductor die has a hexagon shape with beveled corners when viewed in plan view.
In some embodiments, the semiconductor die comprises a MOSFET that comprises an active region that comprises a plurality of unit cell transistors.
In some embodiments, a gate runner of the MOSFET comprises first and second segments that connect at an obtuse angle. In some embodiments, the first and second segments of the gate runner each extend along a periphery of the active region. In some embodiments, a gate pad of the MOSFET is located in a center of the active region, and the gate runner comprises a plurality of additional segments that extend outwardly from the gate pad.
In some embodiments, a gate runner of the MOSFET comprises first and second segments that connect at an angle of between 115° and 125°.
In some embodiments, the semiconductor die has a polygonal shape when viewed in plan view, wherein corners of the polygonal shape define interior angles that exceed 90°.
In some embodiments, the substrate comprises a silicon carbide substrate or a gallium nitride substrate.
Pursuant to further embodiments of the present invention, semiconductor devices are provided that comprise a semiconductor die that comprises at least five sides when viewed in plan view.
In some embodiments, the semiconductor die comprises a semiconductor layer that has a hexagonal crystal structure.
In some embodiments, the semiconductor die has a hexagon shape when viewed in plan view.
In some embodiments, the semiconductor die has an irregular hexagon shape when viewed in plan view.
In some embodiments, the semiconductor die has a hexagon shape with beveled corners when viewed in plan view.
In some embodiments, at least three of the sides of the semiconductor die extend along crystallographic axes of the hexagonal crystal structure of the semiconductor layer.
In some embodiments, all of the sides of the semiconductor die extend along crystallographic axes of the hexagonal crystal structure of the semiconductor layer.
In some embodiments, the semiconductor die comprises a MOSFET that comprises an active region that comprises a plurality of unit cell transistors, and a gate runner of the MOSFET comprises first and second segments that connect at an obtuse angle. In some embodiments, the obtuse angle is an angle of 120°. In some embodiments, the first and second segments of the gate runner each extend along a periphery of the active region. In some embodiments, a gate pad of the MOSFET is located in a center of the active region, and the gate runner comprises a plurality of additional segments that extend radially outwardly from the gate pad.
In some embodiments, the semiconductor die has a polygonal shape when viewed in plan view, wherein corners of the polygonal shape define interior angles that exceed 90°.
In some embodiments, the semiconductor layer comprises a silicon carbide substrate or a gallium nitride substrate.
Pursuant to additional embodiments of the present invention, semiconductor devices are provided that comprise a semiconductor die that, when viewed in plan view, has a polygonal shape with corners that define interior angles that exceed 90°.
In some embodiments, the semiconductor die comprises a semiconductor layer that has a hexagonal crystal structure.
In some embodiments, the polygonal shape is a hexagon. In some embodiments, the polygonal shape is an irregular hexagon shape.
In some embodiments, at least two sides of the semiconductor die extend along crystallographic axes of the hexagonal crystal structure of the semiconductor layer. In some embodiments, all sides of the semiconductor die extend along crystallographic axes of the hexagonal crystal structure of the semiconductor layer.
In some embodiments, the semiconductor die comprises a MOSFET that an active region that comprises a plurality of unit cell transistors, and a gate runner of the MOSFET comprises first and second segments that connect at an obtuse angle. In some embodiments, the obtuse angle is an angle of 120°. In some embodiments, the first and second segments of the gate runner each extend along a periphery of the active region. In some embodiments, a gate pad of the MOSFET is located in a center of the active region, and wherein the gate runner comprises a plurality of additional segments that extend radially outwardly from the gate pad.
In some embodiments, the semiconductor layer comprises a silicon carbide substrate or a gallium nitride substrate.
Pursuant to further embodiments of the present invention, semiconductor devices are provided that comprise a semiconductor die that has a polygonal shape when viewed in plan view with beveled corners.
In some embodiments, the semiconductor die comprises a semiconductor layer that has a hexagonal crystal structure.
In some embodiments, the polygonal shape has six major sides and the beveled corners comprise six beveled corners
In some embodiments, at least two of the sides of the semiconductor die extend along crystallographic axes of the hexagonal crystal structure of the substrate. In some embodiments, all of the sides of the semiconductor die extend along crystallographic axes of the hexagonal crystal structure of the semiconductor layer.
In some embodiments, the semiconductor die comprises a MOSFET that comprises an active region that comprises a plurality of unit cell transistors, and a gate runner of the MOSFET comprises first and second segments that connect at an obtuse angle. In some embodiments, the obtuse angle is an angle of 120°. In some embodiments, the first and second segments of the gate runner each extend along a periphery of the active region. In some embodiments, a gate pad of the MOSFET is located in a center of the active region, and the gate runner comprises a plurality of additional segments that extend radially outwardly from the gate pad.
Pursuant to further embodiments of the present invention, semiconductor devices are provided that comprise a semiconductor die a semiconductor layer structure that comprises an active region and a gate runner on the semiconductor layer structure that comprises first and second segments that connect at an obtuse angle.
In some embodiments, the obtuse angle is an angle of 1200.
In some embodiments, the first and second segments of the gate runner each extend along a periphery of the active region.
In some embodiments, the gate runner further comprises third and fourth segments, and the first through fourth segments define respective first through fourth sides of a hexagon when viewed in plan view.
In some embodiments, a gate pad of the MOSFET is located in a center of the active region, and the gate runner comprises a plurality of additional segments that extend radially outwardly from the gate pad. In some embodiments, the plurality of additional segments are radially spaced apart from each other by 60°.
In some embodiments, the semiconductor die is a hexagonally-shaped semiconductor die.
Pursuant to further embodiments of the present invention, semiconductor devices are provided that comprise a semiconductor die that has a semiconductor layer structure that comprises an active region and a gate runner on the semiconductor layer structure that comprises first, second and third segments that extend along respective first, second and third crystallographic axes of a semiconductor substrate of the semiconductor layer structure.
In some embodiments, the first, second and third segments of the gate runner each extend along a periphery of the active region.
In some embodiments, the gate runner further comprises a fourth segment, and wherein the first through fourth segments define respective first through fourth sides of a hexagon when viewed in plan view.
In some embodiments, the semiconductor die is a hexagonally-shaped semiconductor die.
Pursuant to further embodiments of the present invention, semiconductor devices are provided that comprises a semiconductor die a semiconductor layer structure that comprises an active region, a gate pad on the semiconductor layer structure, and a plurality of gate runner segments that extend radially from the gate pad to corners of the semiconductor die.
In some embodiments, the gate pad is located in a central portion of the active region.
In some embodiments, the semiconductor device further comprises an additional plurality of gate runner segments that extend along a periphery of the active region.
In some embodiments, the semiconductor die is a hexagonally-shaped semiconductor die.
In some embodiments, the gate pad is located in a center of the active region.
In some embodiments, the semiconductor layer structure includes a 4H silicon carbide substrate.
Power semiconductor devices typically have parasitic resistances, capacitances and/or inductances which may be within the semiconductor die itself, in the electrical leads that connect the semiconductor die to external components, and/or in the protective packaging for the device. These parasitic resistances, capacitances, and inductances act to store and/or dissipate electrical and thermal energy. These imperfections manifest as wasted energy during device operation. For example, the processing of electrical power results in waste heat due to conduction and switching losses. Removal of this waste heat results in a rise in temperature due to thermal resistances and capacitances.
As a power semiconductor device operates over its lifetime, it will typically heat up and cool down many, many times. Moreover, many power semiconductor devices, such as ones used in electrical vehicles, power generation substations and the like are subjected to extreme environments, including cold weather conditions, high ambient temperatures (e.g., under the hood of a vehicle), and high humidity. As the semiconductor device heats up and cools down, the materials of the semiconductor die and protective package will expand and contract. The rate at which the different materials in the die and package expand and contract is governed by their respective Coefficients of Thermal Expansion (“CTE”), which can be quite different for different materials. When two different materials are bonded together, if one material wants to expand or contract more than the other, tensile and compressive stresses are generated within each material as well as at the interfaces between them.
The stresses and strains generated by the above-described thermal cycles, repeated many times over, may fatigue the semiconductor die and/or package structures. In particular, the stresses can damage the device, resulting in a reduction of function all the way up to a catastrophic failure if, for example, cracking occurs. Stresses and strains also can greatly reduce the effectiveness of the interface, or attach, of the semiconductor die to the package. For example, the semiconductor die of a packaged semiconductor device is/are often mounted to a heat spreader, copper pad, lead frame, isolated power substrate or the like, depending on the type of package used and the application. Such heat spreaders, pads, etc. may be mounted on one or both sides of the semiconductor die, and are attached to the die via die attach materials. These die attach layers may be critical, as they may function as all three of an electrical, thermal and mechanical interface between the semiconductor die and the package. As the packaged semiconductor device goes through thermal (heating and cooling) cycles, the stresses and strains generated in the die attach layer(s) can cause cracks, ruptures, etc. which can ultimately result in a significant degradation of the die attach layers to perform their electrical, thermal and/or mechanical functions.
The thermal strains and stresses that may arise in a packaged semiconductor device may be the result of the structural geometry of the components that form the device, the methods of attaching these components, the material makeup of the assembly, and the difference between the temperature extremes encountered during device operation and a temperature which is assumed to be a stress-free state. Accordingly, one way to reduce thermal stains and stresses is to select materials that have similar coefficients of thermal expansion. Unfortunately, however, this is often not practical as the materials serve many different functions and it is often not possible or practical to trade off one performance characteristic for another. For example, softer die attach materials are often more resilient to fatigue, but also exhibit significantly worse thermal conductivity. Thus, the selection of a die attach material involves an inherent tradeoff between reliability and performance, and the improvement in reliability provided by use of the softer die attach materials may not be worth the compromise in performance.
As discussed above, semiconductor die are typically formed using “wafer level” operations in which semiconductor, insulating and metal layers/structures are grown, formed and/or deposited on a semiconductor wafer. The semiconductor wafer is then cut or “diced” into individual semiconductor die through a sawing operation in which a diamond dicing blade is used to saw the wafer into columns and rows. Consequently, most power semiconductor die have a rectangular (typically square) shape with right angled corners that result from sawing the wafer along straight lines. Corners are locations where thermal expansion and its associated stresses and strains are the highest. Corners are also an abrupt transition that can act as a failure initiation site. Moreover, the “sharper” the corner, the greater the stresses and strains and the more likely the corner is to act as a failure initiation site. Unfortunately, a rectangular shape has relatively sharp corners, and hence is challenging from a stress perspective, as the sharp corners are potential failure points. Herein, the “shape” of a semiconductor die refers to the shape of the die when viewed in plan view. Thus, a rectangularly-shaped semiconductor die is a die that appears rectangular when viewed from above.
The “mechanical robustness” of a device refers to the ability of the device to be resilient to stresses and strains, such as stresses and strains that are induced by thermal cycling or other physical forces. There are a number of potential ways to increase the mechanical robustness of a packaged semiconductor device, including reducing the mismatches in the coefficients of thermal expansion between the materials forming the device, reducing abrupt transitions in the geometry of the elements forming the semiconductor device (such as sharp corners), introducing notches or slots to relieve stress concentrations, and/or using materials that are more resilient to stress related failure modes.
Pursuant to embodiments of the present invention, semiconductor devices are provided that may exhibit increased mechanical robustness and/or which may have reduced electrical field concentrations at the device edges. In some embodiments, the semiconductor devices may include semiconductor die that have non-rectangular shapes, such as polygonal shapes that have more than four sides. Such semiconductor die may have corners that form interior angles that exceed 90°, and hence are not as “sharp” as the corners of rectangular semiconductor die that have 90° interior angles. Such “softer” corners will exhibit less stress buildup in response to thermal cycling or physical forces, and hence may be less prone to crack generation, delamination and/or device failure. In other embodiments, the semiconductor die may have rounded or beveled corners that exhibit the same advantage of less stress buildup. In each of the above embodiments, the selected shape for the semiconductor die preferably has a good packing density in order to efficiently utilize as much of the wafer as possible. It should be noted that electric field crowding effects can result in high electric field concentrations in corner regions of semiconductor die, with the amount of electric field buildup generally increasing the sharper the corners of the die. Thus, by providing semiconductor die having “softer” corners, the electric field crowding effects can be reduced in the termination region of the semiconductor die. This may improve the robustness of the semiconductor device or may allow the size of the termination region to be reduced, thereby increasing the amount of active die area.
In still other embodiments of the present invention, semiconductor die are provided that are diced along the crystallographic axes of the substrate of the semiconductor layer structure. Cuts taken along the crystallographic axes of the substrate may be “cleaner” than cuts that are taken off the crystallographic axes. The less “clean” off-axis cuts may generate disruptions within the lattice structure of the semiconductor material, and these disruptions can act as initiation sites for cracking, delamination, degradation of performance and/or device failure. Accordingly, dicing the semiconductor wafer into semiconductor die that have shapes that align with the crystal structure of the substrate of the wafer results in a more rugged semiconductor die that are more resilient stress and hence less likely to be damaged in response to thermal cycling.
Pursuant to still further embodiments of the present invention, semiconductor devices are provided that have semiconductor die with gate runners and/or gate pads that are designed/positioned to improve device performance. For example, in some embodiments, semiconductor die are provided that have gate runners that have segments that connect to each other at angles that exceed 90°, such as angles of 120°. For example, semiconductor die are provided that have gate runners that include at least first, second, third and fourth segments that form respective first, second, third and fourth sides of a hexagon. In other words, the gate runner forms at least four sides of a hexagon shape, and may include additional segments so that the gate runner has a hexagon shape or almost a complete hexagon shape (e.g., a hexagon shape with one or more small gaps). Such a gate runner can extend around at least four sides of a hexagonally-shaped semiconductor die. As another example, semiconductor die are provided that have gate runners that extend radially outwardly from a gate pad located in the center of a hexagonally-shaped semiconductor die. Such a gate runner can further include additional segments that extend at least partially around the periphery of the die. This gate runner design can have relatively short paths for the gate signal to each unit cell transistor.
The semiconductor die according to embodiments of the present invention that have novel shapes/characteristics may be formed using less traditional dicing technologies such as plasma dicing, laser ablation, stealth dicing or thermal laser separation. Plasma dicing, which is also referred to as Deep Reactive Ion Etching, refers to a dry etching process that etches narrow cuts into the wafer using a plasma gas such as Sulpher Hexafluoride. Stealth dicing refers to an internal absorption laser dicing process where a laser beam is passed along a cut line and focused beneath the surface of the wafer. The die are then separated using a tape expander. These less traditional dicing technologies allow a semiconductor wafer to be cut along more than two axes and/or to be cut to provide semiconductor die that have rounded corners.
Thus, according to various embodiments of the present invention, semiconductor devices are provided that comprise a semiconductor die that comprises a substrate that has a hexagonal crystal structure. In some embodiments, first and second sides of the semiconductor die extend along respective first and second crystallographic axes of the hexagonal crystal structure of the substrate. In other embodiments, the semiconductor die may comprise at least five sides when viewed in plan view. In still other embodiments, the semiconductor die may have a polygonal shape when viewed in plan view that has corners that define interior angles that exceed 90°. In yet additional embodiments, the semiconductor die may have a polygonal shape when viewed in plan view with beveled corners.
In any or all of the above-described embodiments, the first and second sides may meet to define an interior angle that is an obtuse angle. The semiconductor die may have, for example, a regular or irregular hexagon shape when viewed in plan view, and may or may not have beveled or rounded corners. The semiconductor die may comprise, for example, a MOSFET that comprises an active region that comprises a plurality of unit cell transistors. In some embodiments, the MOSFET may include a gate runner that comprises first and second segments that connect at an angle that is greater than 90° such as, for example, an angle of 120°. The first and second segments of the gate runner may, for example, each extend along a periphery of the active region. These MOSFETs may alternatively or additionally include a gate pad that is positioned in a center of the active region. In such embodiments, the gate runner may further comprise a plurality of additional segments that extend outwardly from the gate pad. The semiconductor die may include, for example, a 4H silicon carbide substrate.
In still other embodiments of the present invention, semiconductor devices are provided that comprise a semiconductor die that comprises a semiconductor layer structure that has an active region therein. A gate runner is provided on the semiconductor layer structure. The gate runner may, for example, comprise first and second segments that connect at an angle of 120° and/or may comprise comprises first, second and third segments that extend along respective first, second and third crystallographic axes of the semiconductor substrate. In some embodiment, the semiconductor die may further comprise a gate pad on the semiconductor layer structure. In such embodiments, a plurality of gate runner segments may extend radially from the gate pad to corners of the semiconductor die.
Embodiments of the present invention will now be described in more detail with reference to the attached figures. It will be appreciated that features of the different embodiments disclosed herein may be combined in any way to provide many additional embodiments. Thus, it will be appreciated that various features of the present invention are described below with respect to specific examples, but that these features may be added to other embodiments and/or used in place of example features of other embodiments to provide many additional embodiments. Thus, the present invention should be understood to encompass these different combinations.
Thermal and/or physical induced stresses in a semiconductor die build up more in the corners of the die than they do in the middle of the die. Generally speaking, stress induced defects in a device or material are most likely to occur in regions where the stresses are the highest, and hence the corners of a semiconductor die are the regions of the semiconductor die that are most susceptible to stress-induced failures. The sharper the interior angle of the corner, the more the stress builds up. Thus, one way to reduce the magnitude of thermally and/or physically induced stresses is to increase the magnitude of the interior angles of the corners. As shown in
It was recognized that failures in many materials will generally start at either a defect or flaw (e.g., a crystal defect, a damaged region of the crystal, or a void, crack, or chip in the crystal) or in a region where stress concentrations are the highest. Various of the approaches described herein focus on dicing a semiconductor wafer into geometrical shapes (when the die/wafer are viewed in plan view) that reduce the abruptness of geometrical transitions and/or which dice the wafer along the crystallographic axes of the wafer substrate in order to reduce stress concentrations in the semiconductor die and/or to strengthen regions of the semiconductor die where natural weaknesses may exist.
Silicon carbide based semiconductor devices are typically formed by growing semiconductor epitaxial layers on a silicon carbide substrate to form a semiconductor layer structure and then processing the wafer (e.g., depositing metal and/or insulation layers on the wafer, performing ion implantation steps, performing various etching steps, etc.) and then dicing the completed wafer into a plurality of discrete semiconductor die, each of which is a separate semiconductor device. The silicon carbide wafer on which the semiconductor epitaxial layers are grown almost always has a round shape when viewed in plan view, and these wafers are diced by sawing the wafer along longitudinal and transverse cut lines to singulate the wafer into the plurality of individual semiconductor die.
First, the relatively sharp 90° angles formed at the corners of the semiconductor die 26 act to build up stress in these regions, creating potential failure points. This can be seen, for example, with reference to
Second, when 4H silicon carbide semiconductor wafers 20 are used (4H silicon carbide is the type of silicon carbide that is almost always used to form power semiconductor devices), at most only one of the longitudinal cut lines 22 or the transverse cut lines 24 shown in
Pursuant to embodiments of the present invention, semiconductor die are provided that have polygonal shapes when viewed in plan view that have more than four sides. Herein, the “sides” of a semiconductor die refer to the surfaces that connect the top and bottom (major) surfaces of the die. For example, semiconductor die are provided that have hexagonal shapes (or generally hexagonal shapes, such as a hexagonally-shaped die that has a small bevel on each corner) when viewed in plan view. By forming the semiconductor die to have polygonal shapes that have more than four sides, the amount of stress generated in the corners of the semiconductor die can be reduced. Moreover, the use of hexagonally-shaped semiconductor die can be particularly advantageous because, as discussed above, 4H silicon carbide has a hexagonal crystal structure, and hence hexagonally-shaped 4H silicon carbide based semiconductor die can be formed by dicing a semiconductor wafer formed of such materials along the crystallographic axes of the material. Moreover, various other materials that are good candidates for power semiconductor devices such as gallium nitride based materials also have hexagonal crystal structures, and hence hexagonally-shaped power semiconductor die that are formed using gallium nitride or sapphire wafers may also be diced along crystallographic axes of the substrate material. As discussed above, dicing a semiconductor die along the crystallographic axes of the substrate can reduce or eliminate disruptions on the lattice that may result when a semiconductor die is cut off-axis.
In addition, some semiconductor die having polygonal shapes that have more than four sides such as, for example, hexagonally-shaped semiconductor die, may be “packed” to use a larger amount of the area of a circular semiconductor wafer, thus allowing more semiconductor die to be generated from a single wafer. This can be seen, for example, by comparing
Another technique which can be used to reduce the inherently higher stress concentrations that can naturally arise in the corners of a semiconductor die is to include one or more beveled cuts in the corner region that replace a sharp angle with two or more larger angles. Each bevel effectively adds an additional side at each corner of the semiconductor die. Thus, for example, if a semiconductor wafer is diced into square semiconductor die where each corner of the square has a bevel, the stress concentration that is generated in each corner may be reduced.
As shown in
A “stress-concentration factor” K is a scalar value that represents the percentage of increase in the magnitude of the maximum stress levels due to differences in the shapes of different semiconductor die. When, for example, K is equal to 1.5, this means that the magnitude of maximum stress is 50% higher than a default case.
When the corners of the semiconductor die are not rounded, the parameter “d/r” in
Thus, pursuant to some embodiments of the present invention, semiconductor die are provided that have maximum stress levels that are at least 10%, at least 15%, at least 20% or at least 25% less than the maximum stress levels in a default semiconductor die that is identical to the semiconductor die according to embodiments of the present invention except that the default semiconductor die has a rectangular shape. By “identical” it is meant that the two semiconductor die are the same in all aspects (e.g., materials, layer structure, etc.) except for shape, and have the same parameter “d” and, in some embodiments, the same parameter “r.”
As discussed above, conventionally semiconductor wafers are singulated using a diamond dicing saw. Generally speaking, this technique can only be used to make straight cuts that extend across the full length or width of the semiconductor die, and hence cannot be used to singulate a semiconductor wafer into semiconductor die having polygonal shapes with more than four sides. Thus, alternative dicing methods may be used to form the semiconductor die according to embodiments of the present invention such as, for example, dicing using a focused laser beam (including lasers that generate beams that are outside the visible spectrum, such as ultraviolet laser beams). With this type of dicing, the laser beam is passed along the cut lines, typically multiple times, and ablates away material. As the beam of energy moves across the wafer, it is not limited to straight lines or orthogonal lines. As such, more complex semiconductor die shapes can be achieved. The laser beam may fully remove the material along the cut lines (i.e., cut all the way through the wafer) or, in many cases, the laser beam may partially cut through the material along the cut lines and then the tape on which the wafer is mounted may be stretched and this may cause the remaining material to separate along the cut lines. Using a laser beam to dice a wafer can be cost effective, as it is fast and may require the removal of less material between devices, thus potentially allowing for more devices to formed on each wafer. Other less traditional dicing techniques such as plasma dicing, stealth dicing or thermal laser separation may also be used.
The semiconductor die according to embodiments of the present invention may have regular polygon shapes or irregular polygon shapes. A regular polygon is a polygon in which all of the sides have the same length. An irregular polygon, on the other hand, is a polygon in which some sides have different lengths. As discussed above, when the corners of a regular polygon are beveled at an appropriate angle, the regular polygon may be converted into an irregular polygon. Moreover, with some devices, it may be advantageous to form the semiconductor die to have an irregular polygon shape, which may provide increased flexibility in the placement and location of elements of the semiconductor die such as bond pads, gate runners, gate fingers and the like. Semiconductor die with irregular polygon shapes may also better form fit a given package, and provide an alternative technique for increasing device area.
The power diode semiconductor die 100 has a regular hexagon shape. As such, the interior angles defined by the corners of the semiconductor die exceed 90° (here each angle is) 120°, as shown in
While
The power diode semiconductor die 100 discussed above with reference to
The power MOSFET semiconductor die 110 has a hexagon shape. As shown in
The power MOSFET semiconductor die 110 has a regular hexagon shape, and hence will have the same advantages over conventional square semiconductor dies that are discussed above with reference to power diode semiconductor die 100 of
Thus, as shown in
Pursuant to further embodiments of the present invention, power MOSFET semiconductor die (and other three-terminal semiconductor die) are provided that have a variety of different designs for the gate pads and/or gate runners. For example,
It will also be appreciated that the gate pads may have shapes other than the square or pentagon shapes shown in
For example,
In some cases, three-terminal semiconductor die may require additional contact (bonding) pads that are required for secondary functions. For example, in devices that have soldered or sintered top side connections, a dedicated source kelvin wire bond pad is also provided. As another example, additional secondary bond pads may be needed in some cases for on-chip sensors, such as temperature or current sensors.
The semiconductor die according to embodiments of the present invention may be used in myriad applications, including motor drives, battery chargers, wind/solar inverters, power supplies, etc.
While the present invention is primarily described above with respect to power MOSFET implementations, it will be appreciated that the techniques described herein apply equally well to other power semiconductor devices. Thus, embodiments of the present invention are not limited MOSFETs.
While embodiments of the present invention are primarily discussed above with respect to semiconductor die that have at least five sides when viewed in plan view and/or have corners that define interior angles that are greater than 90°, it will be appreciated that embodiments of the present invention are not limited thereto. In other embodiments, the semiconductor die, when viewed in plan view, may have less than four sides (e.g., three sides to form a triangle) and/or may have corners that define interior angles that are less than 90° such as angles of 60°. Thus, it will be appreciated that all of the hexagon shaped semiconductor die discussed above can be implemented as triangular shaped die in other embodiments.
The present invention has primarily been discussed above with respect to silicon carbide based power semiconductor devices. It will be appreciated, however, that silicon carbide is used herein as an example and that the devices discussed herein may be formed in any appropriate wide band-gap semiconductor material system. As an example, gallium nitride based semiconductor materials (e.g., gallium nitride, aluminum gallium nitride, etc.) may be used instead of silicon carbide in any of the embodiments described above.
Embodiments of the present invention have been described above with reference to the accompanying drawings, in which embodiments of the invention are shown. It will be appreciated, however, that this invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth above. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.
Herein, the term “plurality” means two or more. Herein, “substantially” means within +/−10%.
It will be understood that, although the terms first, second, etc. are used throughout this specification to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. The term “and/or” includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” “comprising,” “includes” and/or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Relative terms such as “below” or “above” or “upper” or “lower” or “top” or “bottom” may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Embodiments of the invention are also described with reference to a flow chart. It will be appreciated that the steps shown in the flow chart need not be performed in the order shown.
In the drawings and specification, there have been disclosed typical embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
