CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2019-174477, filed Sep. 25, 2019, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a printed wiring board having plating bumps and a method for manufacturing the printed wiring board.
Description of Background Art
Japanese Patent Application Laid-Open Publication No. 2010-129996 describes bump formation using a plating method. The entire contents of this publication are incorporated herein by reference.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a printed wiring board includes a base insulating layer, a conductor layer formed on the base insulating layer and including conductor pads, an underlayer formed on one of the conductor pads of the conductor layer and including a metal different from a metal of the conductor layer, a solder resist layer formed on the base insulating layer such that the solder resist layer is covering the conductor layer and has openings exposing the conductor pads, respectively, and a bump formed directly on a first conductor pad of the conductor pads and including a base plating layer formed in a first opening of the openings and a top plating layer formed on the base plating layer such that a metal of the base plating layer is same as the metal of the conductor layer.
According to another aspect of the present invention, a method for manufacturing a printed wiring board includes forming a conductor layer on a base insulating layer such that the conductor layer includes conductor pads, forming a solder resist layer on the base insulating layer such that the solder resist layer covers the conductor layer and that the solder resist layer has openings exposing the conductor pads, respectively, forming on one of the conductor pads of the conductor layer an underlayer including a metal that is different from a metal of the conductor layer, and forming directly on a first conductor pad of the conductor pads a bump including a base plating layer and a top plating layer. The forming of the bump includes forming the base plating layer in a first opening of the openings and forming the top plating layer on the base plating layer such that a metal of the base plating layer is same as the metal of the conductor layer.
BRIEF DESCRIPTION OF THE DRAWINGS
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
FIG. 1 is a cross-sectional view illustrating a printed wiring board of an embodiment of the present invention;
FIG. 2A is a cross-sectional view illustrating a method for manufacturing a printed wiring board according to an embodiment of the present invention;
FIG. 2B is a cross-sectional view illustrating the method for manufacturing a printed wiring board according to the embodiment;
FIG. 2C is a cross-sectional view illustrating the method for manufacturing a printed wiring board according to the embodiment;
FIG. 2D is a cross-sectional view illustrating the method for manufacturing a printed wiring board according to the embodiment;
FIG. 2E is a cross-sectional view illustrating the method for manufacturing a printed wiring board according to the embodiment;
FIG. 2F is a cross-sectional view illustrating the method for manufacturing a printed wiring board according to the embodiment;
FIG. 2G is a cross-sectional view illustrating the method for manufacturing a printed wiring board according to the embodiment;
FIG. 2H is a cross-sectional view illustrating the method for manufacturing a printed wiring board according to the embodiment; and
FIG. 3 is a cross-sectional view illustrating a printed wiring board according to a conventional technology.
DETAILED DESCRIPTION OF THE EMBODIMENTS
Embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.
Printed Wiring Board
FIG. 1 illustrates an enlarged view of a portion of a printed wiring board 10 of the embodiment. The printed wiring board 10 may be a substrate with a core formed by alternately laminating conductor layers and resin insulating layers on one side or both sides of a core substrate (not illustrated in the drawings), the conductor layers each having a predetermined circuit pattern. In the case where the conductor layers are formed on both sides of the core substrate, conductor layers opposing each other via the core substrate may be connected to each other via through-hole conductors (not illustrated in the drawings). Alternatively, the printed wiring board 10 may be a coreless substrate obtained by alternately laminating conductor layers and resin insulating layers on a support plate (not illustrated in the drawings) instead of a core substrate, and then removing the support plate. In any case, as illustrated in FIG. 1, the printed wiring board 10 includes at least a base insulating layer 12 which is positioned the outermost among the resin insulating layers, a conductor layer 14 which is formed on the base insulating layer 12 and has a predetermined circuit pattern, and a solder resist layer 16 which is formed on the base insulating layer 12 and the conductor layer 14. Other multiple conductor layers and multiple resin insulating layers are often alternately provided below the base insulating layer 12, but are omitted in the drawings. However, it is also possible that the printed wiring board 10 is formed of one insulating layer (the base insulating layer 12) and one conductor layer (the conductor layer 14).
The base insulating layer 12 can be formed of, for example, a resin composition or the like containing an inorganic filler, such as silica or alumina, and an epoxy resin. The conductor layer 14 is formed of a conductive metal, for example, a metal containing copper as a main component.
The solder resist layer 16 has a first opening (16a) exposing a portion of the conductor layer 14 as a first conductor pad (14a), a second opening (16b) having a smaller diameter than the first opening (16a) and exposing another portion of the conductor layer 14 as a second conductor pad (14b), and a third opening (16c) having, for example, a larger diameter than the first opening (16a) and exposing yet another portion of the conductor layer 14 as a third conductor pad (14c). An aspect ratio of the first opening (16a), that is, a ratio of a depth to a diameter at a bottom thereof can be set to 0.5 or less. An aspect ratio of the second opening (16b), that is, a ratio of a depth to a diameter at a bottom thereof can be set to 0.6 or more.
An underlayer 18 is formed on the third conductor pad (14c). As the underlayer 18, for example, a nickel layer formed on a surface of the third conductor pad (14c), a palladium layer formed on the nickel layer, and a gold layer formed on the palladium layer can be exemplified. In addition, a nickel layer and a gold layer formed on the nickel layer can be exemplified.
The printed wiring board 10 further includes a first bump 20 which is formed on the first conductor pad (14a), and a second bump 22 which is formed on the second conductor pad (14b) and has a smaller diameter than the first bump 20. The first and second bumps (20, 22) are respectively formed directly on the first and second conductor pads (14a, 14b) without the underlayer 18. The first bump 20 can be used for connecting to a power source or a ground line. The second bump 22 having a smaller diameter than the first bump 20 can be used for connecting to a signal line. The third conductor pad (14c) can be used, for example, for connecting to a terminal of an electronic component such as a capacitor via the underlayer 18.
The first bump 20 has a first base plating layer 24 formed in the first opening (16a), and a first top plating layer 28 formed in a substantially hemispherical shape on the first base plating layer 24 via a first intermediate layer 26 containing, for example, nickel as a main component. The first intermediate layer 26 preferably has a thickness of 7 μm or less.
The first base plating layer 24 is formed of the same conductive metal as the conductor layer 14, for example, a metal containing copper as a main component. The first base plating layer 24 is formed to a height exceeding a surface of the solder resist layer 16 (a surface on an opposite side with respect to the base insulating layer 12). As a result, the first bump 20 is stably held in the first opening (16a). A height measured from the surface of the solder resist layer 16 to an upper end surface (24a) of the first base plating layer 24 is preferably in a range of 3 μm-15 μm.
The first top plating layer 28 is formed of a metal which has a lower melting point than the first base plating layer 24 and which is melted by a reflow treatment and is shaped into a substantially hemispherical shape as illustrated in FIG. 1, for example, a metal containing tin as a main component. A thickness of the first top plating layer 28 (a distance in a vertical direction from a lower end of the first top plating layer 28 to a top of the first top plating layer on an outer peripheral surface of the first bump 20) is preferably set in a range of 20 μm-40 μm. By setting the thickness of the first top plating layer 28 in this range, good connection reliability can be achieved between the first bump 20 and a connection pad (not illustrated in the drawings) of an electronic component such as a semiconductor chip or a memory mounted on the printed wiring board 10.
The second bump 22 has a second base plating layer 30 formed in the second opening (16b), and a second top plating layer 34 formed in a substantially hemispherical shape on the second base plating layer 30 via a second intermediate layer 32 containing, for example, nickel as a main component. The second intermediate layer 32 preferably has a thickness of 7 μm or less.
The second base plating layer 30 is formed of the same conductive metal as the conductor layer 14, for example, a metal containing copper as a main component. The second base plating layer 30 is formed to a height exceeding the surface of the solder resist layer 16 (the surface on an opposite side with respect to the base insulating layer 12). As a result, the second bump 22 is stably held in the second opening (16b). A height measured from the surface of the solder resist layer 16 to an upper end surface (30a) of the second base plating layer 30 is preferably in a range of 3 μm-15 μm.
The second top plating layer 34 is formed of a metal which has a lower melting point than the second base plating layer 30 and which is melted by a reflow treatment and is shaped into a substantially hemispherical shape as illustrated in FIG. 1, for example, a metal containing tin as a main component. A thickness of the second top plating layer 34 (a distance in the vertical direction from a lower end of the second top plating layer 34 to a top of the second top plating layer 34 on an outer peripheral surface of the second bump 22) is preferably set in a range of 20 μm-40 μm. By setting the thickness of the second top plating layer 34 in this range, good connection reliability can be achieved between the second bump 22 and a connection pad (not illustrated in the drawings) of an electronic component such as a semiconductor chip or a memory mounted on the printed wiring board 10.
In the printed wiring board 10 of the embodiment shown in FIG. 1, the first base plating layer 24 and the second base plating layer 30 are formed together, and the upper end surface (24a) of the first base plating layer 24 and the upper end surface (30a) of the second base plating layer 30 have the same height as each other. Further, the first intermediate layer 26 and the second intermediate layer 32 are formed together and have the same thickness (height) as each other.
Then, the first top plating layer 28 and the second top plating layer 34 are formed together and are adjusted in their metal plating amounts and have the same thickness (height) as each other after melting by a reflow treatment.
As a result, in the printed wiring board 10 of the embodiment illustrated in FIG. 1, even when the bumps (20, 22) of different sizes are provided, the bump 20 and the bump 22 have substantially the same in height. In addition, the first and second base plating layers (24, 30) are formed of the same conductive metal as the conductor layer 14 forming the first and second conductor pads (14a, 14b), for example, a metal containing copper as a main component, and are respectively directly formed on the first and second conductor pads (14a, 14b). Therefore, the base plating layers (24, 30) and thus the first and second bumps (20, 22) have sufficiently high connection reliability with respect to the conductor pads (14a, 14b).
Method for Manufacturing Printed Wiring Board
In the following, a method for manufacturing a printed wiring board according to an embodiment of the present invention is described with reference to FIGS. 2A-2H for manufacturing the printed wiring board 10 illustrated in FIG. 1.
FIG. 2A illustrates an intermediate in which the conductor layer 14 and the solder resist layer 16 are formed on the base insulating layer 12 using a common method, the conductor layer 14 having a predetermined circuit pattern. Other multiple conductor layers and multiple resin insulating layers are often alternately formed below the base insulating layer 12, but are omitted in the drawings. The multiple conductor layers and the multiple resin insulating layers can be laminated on a core substrate or on a support plate that can be removed afterwards. However, it is also possible that the printed wiring board 10 is formed from one resin insulating layer as the base insulating layer 12 and one conductor layer as the conductor layer 14. In this case, the resin insulating layer corresponds to the base insulating layer 12. For the base insulating layer 12, an insulating resin film for a build-up layer containing inorganic filler such as silica or alumina and an epoxy resin can be used.
As illustrated in FIG. 2B, the third opening (16c) exposing a portion of the conductor layer 14 as the third conductor pad (14c) is first formed in the solder resist layer 16 using, for example, CO2 laser, UV-YAG laser, or the like.
As illustrated in FIG. 2C, the underlayer 18 is formed on the third conductor pad (14c), for example, by laminating a nickel layer, a palladium layer, and a gold layer in this order by plating.
As illustrated in FIG. 2D, next, the first opening (16a) exposing another portion of the conductor layer 14 as the first conductor pad (14a) and the second opening (16b) exposing yet another portion of the conductor layer 14 as the second conductor pad (14b) are formed in the solder resist layer 16, for example, using CO2 laser, UV-YAG laser or the like.
As illustrated in FIG. 2E, for example, an electroless plating treatment such as an electroless copper plating treatment is performed, and a seed layer 36 is formed on the surface of the solder resist layer 16 of the intermediate, on side surfaces of the first, second and third openings (16a, 16b, 16c), and on the conductor pads (14a, 14b).
As illustrated in FIG. 2F, a plating resist 38 of a predetermined pattern that is formed of, for example, a dry film resist and has openings (38a, 38b) at planned formation sites of the first and second bumps (20, 22) (FIG. 1) is formed on the seed layer 36.
As illustrated in FIG. 2G, an electrolytic plating treatment is performed, and the first base plating layer 24 and the second base plating layer 30, which contain a conductive metal of the same kind as the conductor layer 14 forming the first and second conductor pads (14a, 14b), for example, copper as a main component, are formed on portions of the seed layer 36 exposed in the openings (38a, 38b) of the plating resist 38 (including portions of the seed layer 36 in first and second openings (16a, 16b) of the solder resist layer 16 and remaining exposed portions of the seed layer 36 in the openings (38a, 38b) of the plating resist 38). The heights measured from the surface of the solder resist layer 16 to the upper end surfaces (24a, 30a) of the first and second base plating layers (24, 30) are substantially the same.
As illustrated in FIG. 2G, further, for example, an electrolytic plating treatment is performed, and the first and second intermediate layers (26, 32) containing, for example, nickel as a main component are formed on the upper end surfaces (24a, 30a) of the first and second base plating layers (24, 30) in the openings (38a, 38b) of the plating resist 38. The thicknesses of the first and second intermediate layers (26, 32) are each preferably 7 μm or less, and are substantially the same as each other.
As illustrated in FIG. 2G, further, for example, an electrolytic plating treatment is performed, and the first and second top plating layers (28, 34) are formed on the upper end surfaces (24a, 30a) of the first and second base plating layers (24, 30) in the openings (38a, 38b) of the plating resist 38 with the first and second intermediate layers (26, 32) interposed therebetween. The first and second top plating layers (28, 34) are each formed of a metal which has a lower melting point than the first and second base plating layers (24, 30) and which is melted by a reflow treatment and is shaped into a substantially hemispherical shape, for example, a metal containing tin as a main component. The heights of the first and second top plating layers (28, 34) after a reflow treatment are preferably each in a range of 20 μm-40 μm and are substantially the same as each other.
As illustrated in FIG. 2H, the plating resist 38 is peeled off. Further, a portion of the seed layer 36 exposed by the removal of the plating resist 38 is removed by etching.
As illustrated in FIG. 1, a reflow treatment is performed, and the first top plating layer 28 and the second top plating layer 34 are shaped into substantially hemispherical shapes. Due to the reflow treatment, the first bump 20 and second bump 22 are formed each including, from a side close to the first and second conductor pads (14a, 14b), for example, a copper base plating layer, a nickel intermediate layer, and a tin top plating layer, and the heights of the first and second bumps (20, 22) are substantially the same as each other. In FIG. 1, illustration of the seed layer 36 is omitted.
Further, the first and second base plating layers (24, 30) are formed of the same conductive metal as the conductor layer 14 forming the first and second conductor pads (14a, 14b), for example, a metal containing copper as a main component, and are respectively directly formed on the first and second conductor pads (14a, 14b). Therefore, the base plating layers (24, 30) and thus the first and second bumps (20, 22) have sufficiently high connection reliability with respect to the conductor pads (14a, 14b).
As illustrated in FIG. 3, when plating bumps (20′, 22′) are formed by forming a conductor layer (14′) on a base insulating layer (12′) of a printed wiring board (10′), forming a solder resist layer (16′) on the base insulating layer (12′) and the conductor layer (14′), respectively forming base plating layers (24′, 30′) via an underlayer (18′) on conductor pads (14a′ 14b′) in openings (16a′ 16b′) formed in the solder resist layer (16′), and respectively forming top plating layers (28′, 34′) via intermediate layers (26′, 32′) on the base plating layers (24′, 30′), since the underlayer (18′) is formed of a metal different from those of the conductor pads (14a′, 14b′) and the base plating layers (24′ 30′), there is a problem that the base plating layers (24′, 30′) cannot have a sufficiently high connection reliability with respect to the conductor pads (14a′, 14b′).
A printed wiring board according to an embodiment of the present invention includes: a base insulating layer; a conductor layer that is formed on the base insulating layer and includes conductor pads; an underlayer that is formed on one of the conductor pads of the conductor layer and includes a metal different from a metal of the conductor layer; a solder resist layer that is formed on the base insulating layer and on the conductor layer and has openings exposing portions of the conductor layer as conductor pads, respectively; a bump that is directly formed on a first conductor pad of the conductor pads. The bump has: a base plating layer that is formed in a first opening of the openings and is formed of the same metal as the conductor layer; and a top plating layer that is formed on the base plating layer.
Further, a method for manufacturing a printed wiring board according to an embodiment of the present invention includes: forming a conductor layer on a base insulating layer such that the conductor layer includes conductor pads; forming a solder resist layer on the base insulating layer such that the solder resist layer covers the conductor layer and that the solder resist layer has openings exposing the conductor pads, respectively; forming on one of the conductor pads of the conductor layer an underlayer including a metal that is different from a metal of the conductor layer; and forming directly on a first conductor pad of the conductor pads a bump including a base plating layer and a top plating layer. The forming of the bump includes forming the base plating layer in a first opening of the openings and forming the top plating layer on the base plating layer such that a metal of the base plating layer is same as the metal of the conductor layer.
Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
Patent Grant
11363714
