Patent Application
20070061637
The invention described herein relates generally to methods and processes for conducting fast bit mapping of defective memory locations on semiconductor integrated circuits. Among other things, the technology finds applicability to fast bit mapping of defective memories on semiconductor integrated circuits in both packaged and wafer forms.
In the semiconductor industry it is common to test integrated circuit (IC) devices during fabrication to insure that they are functional. Currently a wide variety of testing processes are used to conduct such testing. The invention disclosed herein introduces improved methods and apparatus for testing such IC devices.
As is known to those having ordinary skill in the art IC's are manufactured on semiconductor wafers (typically formed of silicon or other semi-conducting substrates). A number of IC devices are formed on each wafer with the number of IC devices formed being a factor of the size of the device and the size of the wafer. It is common to form hundreds of IC devices on a single wafer. Each one of these devices is commonly referred to as an IC chip or alternatively as a die.
Due to the potential for (and indeed the common occurrence of) fabrication defects each die so fabricated must be tested to insure adequate functionality. Each die is tested by running a series of tests using automatic test equipment. These tests are designed to identify dice that pass all the device electrical specifications and to reject die which do not meet the electrical specifications. Such tests are carried out on each die on a silicon wafer (Wafer Test) and then repeated on a fully packaged IC (Final Test).
One such test includes a test of on chip memory functionality. This is a useful test for a number of reasons. Memory requires a high density of active elements (i.e., transistors) and therefore fabrication defects are very likely to show up in memory areas first. Additionally, in more modem designs, memory is taking up larger and larger portions of the space on each die.
As is known, memories are regular arrays of transistors that are used to store data in an IC. An example of one representative type of such memory is Static Random Access Memory (SRAM). The inventors point out that the invention is not intended to be limited to SRAM implementations only, but can be broadly applied to all types of memory. During production testing of an IC, the memories are tested using test routines built into the IC. These test routines determine if the memory passes the specification or is rejected. Typically, these routines are designed for optimum test coverage by writing and reading many different test algorithms into a memory array. They are also optimized for testing at the fastest test time and the output of such production memory testing is pass or fail only.
In one current process, a wafer is tested on Automated Test Equipment (ATE). Typical examples of such test equipment are a T6672 ATE Machine produced by Advantest Corporation of Tokyo, Japan or Vista, Quartet, and Octet machines produced by Credence Systems Corporation of Milpitas, Calif. Many other manufacturers and machine types are known to those of ordinary skill in the art.
A simplified example of a testing method currently used in the industry is now described to illustrate certain shortcomings in present diagnostic methods. Commonly, a test pattern of data is read into each die to test each memory bit in the die. For example, a series of “ones” is written into the memory of a die and then all the memory bits are read out from the dice. In a fully functional dice the data in will be the same as the data out. Thus, if the read out data bits are also all “ones”, then the die passes. This is done for each die on a wafer. If there is any variance between the data read into the die and the data read out of the die, then there is a defect in the die.
The next step is to identify where the defect is on the wafer. This is a much more difficult and time-consuming process. Using currently employed methods a “production test” is performed on each defective die. As memories are regular dense arrays, bitmapping is a technique used to identify failing bit cells. By applying specific test patterns to the memory array and then reading back the stored data and comparing it to the expected data, faulty bit cells can be identified. These faulty cells can then be mapped against their physical location in the memory array and analysis tools can then determine potential fault mechanisms based on the failing pattern signatures. Some typical examples include Single Column failure faults, Multiple Column failure faults, Single Bit failure faults, Row failure faults, Clustering Bits failure faults, and so on. One aspect of this test is to run a bit map diagnostic routine on each failed die. This means that a bit map is generated that examines every bit of memory on a die. Considering that some die can have more than 100 memory instances each having up to a million or more bits or more of memory, this can take some time. On the positive side such memory bitmapping is useful for analyzing the causes of defects and helpful in improving yield as memory arrays are generally much denser than standard logic area's. This is especially useful if such bit mapping can be done at real-time as information learned can be directly applied to fabrication processes during production.
However, balanced against the obvious utility of such bitmapping processes are the following drawbacks. Such production memory testing is normally carried out through on chip self-test algorithms. These algorithms are optimized for the test coverage (completeness) and the rapid test times. Consequently, these algorithms only provide pass or fail information. Traditional bitmapping takes a substantial amount of time. On average, bitmapping all memories of all failed die on a single wafer takes 1.5-2.5 hours in addition to the normal time used for testing the wafer. Thus, traditional bitmapping represents at least a tenfold time increase over standard pass/fail testing. Due to the substantially increased test time and the associated cost (due to delays, process bottlenecking, and additional engineering time involved) such bitmapping is generally only performed on a sampling basis and only of the lowest yielding wafers (i.e., the wafers resulting in the lowest percentage of acceptable die). Moreover, the time required to write each and every data bit from all the memory of a failed die is exorbitant. This is important because all processing is put on hold until such data is collected and then read to an analysis file.
For these reasons bitmapping is usually carried out under engineering control and limited to a sampling basis. This means that only some of the manufactured wafers can be bitmapped. In the past only the poorest yielding wafers were bitmapped. Thus, the ability to seriously examine memory on a regular basis during processing has been denied to process engineers. The inventors have recognized that these limitations of the existing techniques seriously impact their usefulness. There is a need for improving bit mapping techniques and approaches. The invention described herein discloses method and apparatus for enabling faster bitmapping and improved IC testing.
The principles of the present invention disclose a method for fast bitmapping memory instances in a semiconductor IC die.
In one embodiment, the invention describes a method for fast bitmapping defective memory arrays in semiconductor integrated circuit dice formed on a wafer. The method involves providing automated test equipment and loading a wafer onto the automated test equipment. Initial production testing is performed on each die of the wafer to determine whether all of the memory arrays of each die are functioning properly. Where a die is found to have at least one defective memory array, the particular memory arrays of the die that contain defect are identified. Then selective diagnostic testing is performed on only the failed memory arrays of each defective die to generate memory array defect data. The memory array defect data is used to generate bit maps of the failed memory arrays using the memory array data.
In another embodiment, the method of the invention describes a method for fast bitmapping defective memory arrays in a semiconductor integrated circuit device. Such method includes providing a die having N memory arrays with built-in self repair (BISR) logic and a built-in self test (BIST) capable of identifying whether each specific memory array contains defects. This die is subjected to initial production testing of all N memory arrays to determine whether they are all functioning properly. Where a memory array is found to be defective in a die, identifying which particular memory arrays contain defects. Then diagnostic testing is selectively performed only on the failed memory arrays to generate memory array defect data which is then used to generate bit maps of the failed memory arrays.
In another embodiment the invention describes a computer program product having computer program code for fast bitmapping defective memory arrays in semiconductor integrated circuit dice formed on a wafer. The program includes instructions for conducting initial production testing is performed on each die of the wafer to determine whether all of the memory arrays of each die are functioning properly. Where a die is found to have at least one defective memory array, the program includes instructions for identifying the particular memory arrays of the die that contain defects. Then instructions for selectively performing diagnostic testing are executed only on the failed memory arrays of each defective die to generate memory array defect data. The program includes instructions for generating a data file used to create bit maps of the failed memory arrays using the memory array data
These and other features and advantages of the present invention are described below with reference to the drawings.
The following detailed description will be more readily understood in conjunction with the accompanying drawings, in which:
It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the depictions in the Figures are not necessarily to scale.
The present invention has been particularly shown and described with respect to certain embodiments and specific features thereof. The embodiments set forth hereinbelow are to be taken as illustrative rather than limiting. It should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the invention.
In general terms the following discussion concerns methods, apparatus, and computer program products for conducting fast bitmapping of memory instances during production. In one general approach, a production test of each die on a semiconductor wafer is performed. The test is intended to be performed on die having a plurality of memory instances supported with built-in self repair (BISR) functions. Such memory repair functionality includes built-in self test (BIST) functions for determining if selected memory instances are defective. So in addition to detecting if a die has defective memory, the inventive production test can also determine which of the memory instances are defective using the BIST functionality. After identifying which memory instances are defective, diagnostic testing is selectively performed only on the defective memory instances instead of all memory instances as in the prior art. This selective information forms a much smaller data set than the prior art bitmaps which map all memory spaces on a die. Because the new selective data sets are so much smaller than that of the prior art, they can be quickly downloaded and/or reviewed. This makes it so that, if desired, such bitmapping can be performed in real time on all wafers not just selected wafers as is now the case. This presents a substantial improvement in collecting defect data and troubleshooting manufacturing processes. This disclosure provides methods for accomplishing this goal.
Each such memory array is generally comprised of thousands of rows and columns of transistors that operate together to function as a memory space. The very tight fabrication tolerances of manufacture for such memory circuitry when coupled with the less than perfect manufacturing technique that is the current state of the art, leads to the occasional failure of some of the memory bits of the memory circuitry. For that reason it is common to add “back-up” (or redundant) rows and columns to the memory arrays. When it is discovered that row or column of transistors contains a defect, one of the back-up rows or columns is employed as a replacement. The marginal cost of adding a few extra rows and columns to each memory array is far outweighed by the costs of scrapping the entire die for a single memory failure.
In order to implement the back-up memory rows and columns, specialized circuitry is added to each memory array to identify and diagnose memory failure and implement the back-up memory to keep the memory array operational despite the local failure of some memory elements. The common name given to this type of circuitry is built-in self repair (BISR). As stated above, BISR identifies the presence of defects and employs one or more of the available extra memory rows or columns to circumvent the defective memory elements. One portion of the BISR is a built-in self test (BIST) which is specialized to identify the presence of defects. BIST can identify, with some degree of precision, the nature of the identified defect. BIST can also be employed as a go/no go test which can identify whether a memory array has defects or not. Such a pass or fail test can be simply reflected by a single pass/fail bit for each memory instance. Thus, among other things, the BIST can provide a quick one-bit pass/fail analysis of a memory space.
This is briefly depicted in
Embodiments of the present invention take advantage of the presence of the BIST to enhance memory bitmapping in a way not possible before.
Once the wafer is loaded and the system is initialized for operation and the inspection test program is entered into the ATE testing can begin. An initial production test is performed on each die on the wafer to determine whether all of the memory arrays of each die are functioning properly (Step 305). As is known to those having ordinary skill in the art, the initial production test can be accomplished in a number of different ways. For example a known data pattern of data bits can be read into the die and then the data is read out of the die and a comparison of data in is made with data out. If the two data sets are the same, then all memory arrays on a die are defect free and determined to be functioning properly and the die passes this memory test and no further memory inspection is needed for this die. This test is performed for each die on the wafer. This is generally a pass/fail type test and is performed very quickly.
However, some memory bits may be found that have defects. This may not cause failure of the die but it does indicate that there are some imperfections in the memory spaces somewhere. For each die found having one defective memory bit it is known that at least one memory array is defective. In this case, the inventors understand “defective” to mean contains a non-functioning memory bit rather than completely non-functional. However, defect containing memory arrays can be non-functional. In any case, once a die is determined to have defective memory bits, the question becomes, where are the defective bits. Thus, the method involves identifying, in each die having at least one defective memory bit, which particular memory arrays of the die contain defects (Step 307). In one embodiment this identification process involves running the BIST to identify each memory instance having defects therein. In an advantageous alternative embodiment, the defective arrays can be identified as part of the initial production test (Step 305) by referring to the go/no go bits (223) of each memory instance. These bits quickly identify which memory instances contain defects. Accordingly this method represents a quick process by which all defect containing memory spaces can be identified. For each die, these defect containing memory spaces are identified and the specific defective memory array locations can be stored for further analysis as described below.
The following sub-routine presents one example of method of performing the appropriated tests. For each die having “m” BISR enabled memory blocks the following procedure can identify failed memory instances. Where m0 reflects the “m” block pattern and can be changed to reflect the naming of each of the “m” memory blocks. This procedure determines which memory instance has failed so that an appropriate flag can identify the failed memory instance. An example of a suitable piece of code follows:
Once the defective memory spaces are identified, special diagnostic testing is selectively performing on only the failed memory arrays of each defective die as identified previously (Step 309). The special diagnostic testing require engineering diagnostics programs having special memory diagnostic patterns which better allow bitmapping of the memory arrays. These patterns are usually generated in. WGL test pattern format and include tests for all memory instances. A few example patterns used to accomplish such testing are discussed below.
In the following code, a “for” loop is used. Each item in the pcnt[ ] array is compared against a vector location. The array contains the failing vector locations for the last executed “m” block. These vector locations can be entered from a spreadsheet provided by design, or may be available in the “m” block wgl file. For every instance that is tested in this particular “m” block pattern there is one corresponding vector location. To determine the vector location for each instance, the spreadsheet is consulted for a GO bit vector location that matches with an instance in the appropriate “m” block. A unique ID is then provided to the inst_map( ) procedure to identify which instance has failed. In this example, a BP controller number is used as the identifier, comments are also included to identify which memory instance has failed. Many memory instances can be tested in one “m” block pattern.
Where a vector location is contained in the “m” block wgl file, a UNIX command can be used to filter the wgl file for comments associated with these locations: awk /text1/,/text2/. Where text1 is “core” or some other text that is common in the instance name, text2 is a terminating string in the search and can be “cycle”. This extracts all occurrences of lines between these two texts and the vector cycle number would be part of the comment. This is only valid if the design center has updated the wgl file to contain this info, otherwise it should be part of the spreadsheet provided.
In the spreadsheet file example above, the instance name and corresponding vector number that can be used to build the pcnt[ ] array comparison table are in boldface text. The details of the spreadsheet are not standardized and can be varied from what is shown here.
The datalog13 bitmap13 set( ) and datalog13 bitmap13 reset( ) procedures called in code example 1 should be inserted into the test program prior to being called. This particular example can be used to enable the data collection facilities of the ATE in use. The following code contains these two procedures:
Many other implementation examples and details can be employed to execute the principles of the invention. In any case, regardless of specific implementation details, the overall approach allows diagnostic testing to be performed on only the memory instances having defects. Thus, this presents a considerable time savings over the prior art methods. In the past, such diagnostic testing was performed on every memory bit in the entire die to identify the defective bits. With memory array containing upwards of a million memory bits per memory array, and with each die containing as many as one hundred memory arrays (or more), the time to do such diagnostic testing was enormous. In one typical example, to test a single wafer could take between 90 to 150 minutes. In the mean time, the ATE machine cannot be used for anything else. Moreover, expensive engineering time is spent waiting for and analyzing the diagnostic data. More problematic is the fact that, under most conditions, most of the diagnostic data contains little information of value because it pertains to memory spaces that have no defects. The present invention remedies these problems by only doing diagnostic testing on memory arrays known to have defects. Time is not wasted taking data from perfectly good memory arrays. For example, using the die of
The advantage of such an approach now allows all wafers to be bitmapped and a continuous stream of defect information to be obtained throughout a production process without any serious interruption of process flows.
The inventors point out that the forgoing method is commonly implemented as a computer program product that can be stored on a computer readable media and executed on a device capable of executing computer readable instructions.
The invention can use a combination of hardware and software components. The software can be embodied as computer readable code (or computer program code) on a computer readable medium. The computer readable medium is any data storage device that can store data which can thereafter be read by a computer system. Examples of the computer readable medium include read-only memory, random-access memory, CD-ROMs, magnetic tape, and optical data storage devices. The computer readable medium can also be distributed over a network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.
The inventors point out that certain embodiments of the invention provide a number of advantageous features not found in the prior art. The present invention provides very fast bitmapping times as not all memory instances are required to be bitmapped. These very fast times can be on the order of 10 minutes per wafer which is over ten times as fast as existing approaches. These very fast bit mapping times enable the invention to be implemented cost effectively in a production environment thereby further reducing cost and time overhead. Additionally, unlike existing methods, no specialized engineering intervention is required to collect bit mapping information. This enables the expense of engineering time to be concentrated on bitmap signature analysis instead of data collection. Because the bitmapping can be performed on many more wafers, a faster “yield learning rate” can be obtained which is enhanced by the “real-time” data collection possible using the present invention. The immediacy in feeding fail signature information back into the manufacturing process is a significant improvement enabling must faster yield correction. Also, wafer lots are not placed on production hold while data is being collected.
Some of the most advantageous novel features include only the defect containing memory instances are bitmapped rather than all memory.
It is novel to use the information collected during the BISR repair test to identify failing memory instances for bitmapping purposes. Another novel feature is the modification of the special diagnostic testing patterns to allow bitmapping of only the failing memory instances on a die by die basis during production testing. Normally the diagnostic patterns are used on all memory instances. Additionally, the diagnostic patterns can be modified in real time during each IC test based on the failing BISR information. And perhaps most advantageous of all, by significantly reducing the amount of data collected during bitmapping, the time to access and read to the data collection files is greatly reduced. Also the size of the data files that need to be stored and post processed is greatly reduced
The many features and advantages of the present invention are apparent from the written description, and thus, it is intended by the appended claims to cover all such features and advantages of the invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation as illustrated and described. Hence, all suitable modifications and equivalents may be resorted to as falling within the scope of the invention.
The present invention has been particularly shown and described with respect to certain embodiments and specific features thereof. However, it should be noted that the above-described embodiments are intended to describe the principles of the invention, not limit its scope. Therefore, as is readily apparent to those of ordinary skill in the art, various changes and modifications in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims. Further, reference in the claims to an element in the singular is not intended to mean “one and only one” unless explicitly stated, but rather, “one or more”.
