Claims
- 1. A structure in an integrated circuit comprising:
- a first metal conductive element in an integrated circuit;
- a silicon oxide layer deposited over the conductive element;
- a via through the silicon oxide layer, wherein the sidewalls of the via are relatively rough, having a surface roughness characteristic of not having been exposed to either an wet or a cleanup plasma etch, and an upper surface of the first metal conductive element exposed in the via has a relatively small dip therein; and
- a second metal conductive element over the device and extending into the via, wherein a conductive contact is made between the second metal conductive element and the first metal conductive element.
- 2. The structure of claim 1, wherein said first metal conductive element comprises aluminum.
- 3. The structure of claim 2, wherein said first metal conductive element comprises a refractory metal.
- 4. The structure of claim 1, wherein the surface roughness of the via sidewalls is the result of:
- forming the silicon oxide layer over the first metal conductive element;
- forming and patterning a resist layer over the silicon oxide layer to define a via location;
- anisotropically etching the silicon oxide layer to form a via at the via location, wherein contaminate particles containing a polymer are formed on the sidewalls of the via; and
- removing the contaminate particles with a chemical that acts as a developer for the resist.
- 5. The structure of claim 4, wherein TMAH is used to remove the contaminate particles.
Parent Case Info
This is a division, of application Ser. No. 08/191,770, filed Feb. 3, 1994.
US Referenced Citations (11)
Foreign Referenced Citations (4)
Number |
Date |
Country |
2625870A1 |
Jun 1976 |
DEX |
3141680A1 |
Oct 1981 |
DEX |
64002325 |
Jun 1982 |
JPX |
1219740 |
Jan 1989 |
JPX |
Divisions (1)
|
Number |
Date |
Country |
Parent |
191770 |
Feb 1994 |
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