Claims
- 1. A method of forming an airgap between two structures, comprising the steps of:depositing a layer of material over said two structures using a two-step CVD HDP process, wherein a first of said two steps uses a high gas flow rate of at least one gas and a low substrate bias power to create a void between said two structures and a second of said two steps uses a low gas flow rate of said at least one gas and a high substrate bias power to prevent a seam from forming in said layer above said void.
- 2. The method of claim 1, wherein said layer of material comprises silicon dioxide.
- 3. The method of claim 1, wherein said first and second steps are performed in the same chamber.
- 4. The method of claim 1, wherein said first step transitions to said second step in a continuous manner.
- 5. The method of claim 1, wherein said first step has a duration in the range of 40-60 seconds.
- 6. The method of claim 1, wherein the deposition to sputter etch ratio for the first step is greater than 5.
- 7. The method of claim 1, wherein the deposition to sputter etch ratio for the first step is greater than 10.
- 8. The method of claim 1, wherein the deposition to sputter etch ratio for the second step is less than 5.
- 9. The method of claim 1, wherein the deposition to sputter etch ratio for the second step is approximately 2.9.
- 10. The method of claim 1, the deposition to sputter etch ratio of the first step is approximately 16.
- 11. A method of fabricating a silicon dioxide interlevel dielectric layer having an airgap between two narrowly spaced metal lines, comprising the steps of:depositing said silicon dioxide interlevel dielectric layer using a two step chemical vapor deposition process in a high density plasma processing chamber, wherein the first of said two steps uses a high gas flow rate of at least one gas and a low substrate bias power to create a void and wherein the second of said two steps uses a low gas flow rate of said at least one gas and a high substrate bias power to prevent the formation of a seam in said silicon dioxide interlevel dielectric layer.
- 12. The method of claim 11, wherein said first and second steps are performed in the same chamber.
- 13. The method of claim 11, wherein said first step transitions to said second step in a continuous manner.
- 14. The method of claim 11, wherein said first step has a duration in the range of 40-60 seconds.
- 15. The method of claim 11, wherein said first step uses a source RF power of approximately 3000 W, a substrate bias power in the range of 200-600 W, an O2 gas flow rate of approximately 198 sccm, a SiH4 gas flow rate approximately 98 sccm, and an Ar gas flow rate of approximately 20 sccm.
- 16. The method of claim 11, wherein said second step uses a source RF power of approximately 3000 W, a substrate bias RF power of approximately 1250 W, a O2 gas flow rate of approximately 39 sccm, a SiH4 gas flow rate of approximately 28 sccm, and an Ar gas flow rate of approximately 20 sccm.
- 17. The method of claim 11, wherein the deposition to sputter etch ratio of the first step is greater than 5.
Parent Case Info
This application claims priority under 35 USC § 119 (e) (1) of provisional application Ser. No. 60/045,626, filed May 5, 1997.
US Referenced Citations (5)
Non-Patent Literature Citations (1)
Entry |
Wolf and Tauber, “Silicon Processing for the VLSI Era”, V1—Process Technology, chp. 6, 1986. |
Provisional Applications (1)
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Number |
Date |
Country |
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60/045626 |
May 1997 |
US |