Claims
- 1. Programmable logic device circuitry comprising:
a plurality of regions of programmable logic circuitry; general purpose interconnection circuitry programmably configurable to allow outputs of substantially any of the regions to be applied to inputs of substantially any of the regions; function-specific circuitry; and routing circuitry programmably configurable to route FSB outputs of the function-specific circuitry to only a subset of the regions.
- 2. The circuitry defined in claim 1 wherein the function-specific circuitry is selected from the group consisting of parallel multiplier circuitry, parallel barrel shifter circuitry, parallel arithmetic logic unit circuitry, parallel galois field multiplier circuitry, and parallel multiplier array circuitry for SIMD processing.
- 3. The circuitry defined in claim 1 wherein the routing circuitry is adapted to route FSB outputs for output driving by output driver circuitry of the regions in the subset.
- 4. The circuitry defined in claim 3 wherein the output driver circuitry of the regions in the subset is adapted to drive signals into the general purpose interconnection circuitry.
- 5. The circuitry defined in claim 1 wherein the routing circuitry is adapted to route FSB outputs for registering by register circuitry of the regions in the subset.
- 6. The circuitry defined in claim 1 wherein the routing circuitry is adapted to route FSB outputs for processing by programmable logic circuitry of the regions in the subset.
- 7. The circuitry defined in claim 1 further comprising:
input routing circuitry adapted to selectively divert inputs of a subplurality of the regions to inputs of the function-specific circuitry.
- 8. The circuitry defined in claim 1 further comprising:
input routing circuitry adapted to apply signals from circuitry in a subplurality of the regions to inputs of the function-specific circuitry.
- 9. A programmable logic device comprising:
a plurality of regions of programmable logic, each of which is programmable to perform any of a plurality of logic functions on logic region input signals applied to that logic region in order to produce a logic region output signal of that logic region; programmable general purpose interconnection circuitry adapted to programmably selectively apply substantially any of the logic region output signals to substantially any of the logic regions as a logic region input signal of the last-mentioned logic region; function-specific circuitry adapted to perform a particular type of tasks on a plurality of FSB input signals applied to the function-specific circuitry in parallel to produce a plurality of FSB output signals output by the function-specific circuitry in parallel; and special purpose routing circuitry adapted to selectively route the FSB output signals to only a subset of the logic regions for use by circuitry of the logic regions in that subset.
- 10. The device defined in claim 9 wherein the function-specific circuitry is selected from the group consisting of multiplier circuitry, barrel shifter circuitry, arithmetic logic unit circuitry, galois field multiplier circuitry, and multiplier array circuitry for SIMD processing.
- 11. The device defined in claim 9 wherein the circuitry of the logic regions in the subset that can be used by the FSB output signals, routed by the special purpose routing circuitry, comprises output driver circuitry of those logic regions.
- 12. The device defined in claim 11 wherein the output driver circuitry is adapted to apply output signals to the general purpose interconnection circuitry.
- 13. The device defined in claim 9 wherein the circuitry of the logic regions in the subset that can be used by the FSB output signals, routed by the special purpose routing circuitry, comprises register circuitry of those logic regions.
- 14. The device defined in claim 9 wherein the circuitry of the logic regions in the subset that can be used by the FSB output signals, routed by the special purpose routing circuitry, comprises programmable logic circuitry of those logic regions.
- 15. The device defined in claim 9 wherein the FSB input signals comprise logic region input signals of a subplurality of the logic regions.
- 16. The device defined in claim 15 wherein the logic regions in the subplurality are mutually exclusive of the logic regions in the subset.
- 17. The device defined in claim 15 wherein the logic regions in the subplurality are at least partly logic regions in the subset.
- 18. The device defined in claim 15 wherein the logic regions in the subplurality are the logic regions in the subset.
- 19. The device defined in claim 9 wherein the FSB input signals comprise signals taken from circuitry in a subplurality of the logic regions.
- 20. The device defined in claim 19 wherein the circuitry of the subplurality of logic regions from which the FSB input signals are taken comprises register circuitry of those logic regions.
- 21. The device defined in claim 19 wherein the circuitry of the subplurality of logic regions from which the FSB input signals are taken comprises programmable logic circuitry of those logic regions.
- 22. A digital processing system comprising:
processing circuitry; a memory coupled to said processing circuitry; and a programmable logic device as defined in claim 9 coupled to the processing circuitry and the memory.
- 23. A printed circuit board on which is mounted a programmable logic device as defined in claim 9.
- 24. The printed circuit board defined in claim 23 further comprising:
a memory mounted on the printed circuit board and coupled to the programmable logic device.
- 25. The printed circuit board defined in claim 23 further comprising:
processing circuitry mounted on the printed circuit board and coupled to the programmable logic device.
- 26. Programmable logic device circuitry comprising:
a plurality of regions of programmable logic, each of which is programmable to perform any of a plurality of logic functions on logic region input signals applied to that logic region in order to produce a logic region output signal of that logic region; programmable general purpose interconnection circuitry adapted to programmably selectively apply substantially any of the logic region output signals to substantially any of the logic regions as logic region input signals of the last-mentioned logic regions; parallel multiplier circuitry adapted to perform substantially parallel multiplication on a plurality of multiplier input signals applied to the multiplier circuitry in parallel in order to produce a plurality of multiplier output signals output by the multiplier circuitry in parallel; and special purpose routing circuitry adapted to selectively route the multiplier output signals to only a subset of the logic regions for use by circuitry of the logic regions in that subset.
- 27. The circuitry defined in claim 26 wherein the circuitry of the logic regions in the subset that can be used by the multiplier output signals, routed by the special purpose routing circuitry, comprises output driver circuitry of those logic regions.
- 28. The circuitry defined in claim 27 wherein the output driver circuitry is adapted to apply signals to the general purpose interconnection circuitry.
- 29. The circuitry defined in claim 26 wherein the circuitry of the logic regions in the subset that can be used by the multiplier output signals, routed by the special purpose routing circuitry, comprises register circuitry of those logic regions.
- 30. The circuitry defined in claim 26 wherein the circuitry of the logic regions in the subset that can be used by the multiplier output signals, routed by the special purpose routing circuitry, comprises programmable logic circuitry of those logic regions.
- 31. The circuitry defined in claim 26 wherein the circuitry of the logic regions in the subset that can be used by the multiplier output signals, routed by the special purpose routing circuitry, comprises accumulator circuitry adapted to arithmetically accumulate successive values respectively represented by the multiplier output signals in successive time intervals.
- 32. The circuitry defined in claim 31 wherein the accumulator circuitry is adapted to employ a selectable one of addition and subtraction to arithmetically accumulate the successive values.
- 33. The circuitry defined in claim 31 wherein the accumulator circuitry is adapted to arithmetically accumulate by subtracting each successive value from a previous accumulated value, and wherein the accumulator circuitry comprises first one's complement circuitry adapted to one's-complement the accumulated value, adder circuitry adapted to add a current one of the successive values to outputs of the first one's complement circuitry, and second one's complement circuitry adapted to one's-complement outputs of the adder circuitry to produce a next accumulated value.
- 34. The circuitry defined in claim 31 further comprising circuitry adapted to sign-extend the successive values prior to their use in the accumulator circuitry.
- 35. The circuitry defined in claim 26 wherein the multiplier input signals comprise logic region input signals of a subplurality of the logic regions.
- 36. The circuitry defined in claim 35 wherein the logic regions in the subplurality are mutually exclusive of the logic regions in the subset.
- 37. The circuitry defined in claim 35 wherein the logic regions in the subplurality are at least partly logic regions in the subset.
- 38. The circuitry defined in claim 35 wherein the logic regions in the subplurality are the logic regions in the subset.
- 39. The circuitry defined in claim 26 wherein the multiplier input signals comprise signals taken from circuitry in a subplurality of the logic regions.
- 40. The circuitry defined in claim 39 wherein the circuitry of the subplurality of logic regions from which the multiplier input signals are taken comprises register circuitry of those logic regions.
- 41. The circuitry defined in claim 39 wherein the circuitry of the subplurality of logic regions from which the multiplier input signals are taken comprises programmable logic circuitry of those logic regions.
- 42. The circuitry defined in claim 26 further comprising:
second parallel multiplier circuitry adapted to perform substantially parallel multiplication on a plurality of second multiplier input signals applied to the second multiplier circuitry in parallel in order to produce a plurality of second multiplier output signals output by the second multiplier circuitry in parallel; and second special purpose routing circuitry adapted to selectively route the second multiplier output signals to only a subplurality of the logic regions for use by circuitry of the logic regions in that subplurality.
- 43. The circuitry defined in claim 42 wherein at least some of the logic regions are common logic regions to both the subset and the subplurality.
- 44. The circuitry defined in claim 43 wherein the common logic regions are configurable to arithmetically combine the multiplier output signals and the second multiplier output signals.
- 45. The circuitry defined in claim 44 wherein the common logic regions are further configurable to register signals that result from arithmetically combining the multiplier output signals and the second multiplier output signals.
- 46. The circuitry defined in claim 44 wherein the common logic regions comprise output driver circuitry usable for driving signals that result from arithmetically combining the multiplier output signals and the second multiplier output signals out into the general purpose interconnection circuitry.
- 47. Circuitry for progressively arithmetically accumulating a succession of arithmetic values respectively represented by successive digital input signals to produce successive digital output signals respectively indicative of successive accumulated values comprising:
first one's complement circuitry adapted to one's-complement each successive accumulated value; adder circuitry adapted to successively add each successive arithmetic value to concurrent outputs of the first one's complement circuitry; and second one's complement circuitry adapted to one's-complement outputs of the adder circuitry to produce a next successive accumulated value.
- 48. The circuitry defined in claim 47 further comprising:
sign extension circuitry adapted to sign-extend each successive arithmetic value.
- 49. The circuitry defined in claim 47 further comprising:
alternative circuitry adapted to selectively cause the first and second one's complement circuitry to pass values without one's complementing them.
- 50. The circuitry defined in claim 49 further comprising:
programmable circuitry adapted to control whether the alternative circuitry is operative.
- 51. The circuitry defined in claim 49 further comprising:
control circuitry adapted to apply a time-varying signal to the alternative circuitry so that the alternative circuitry is operative only at certain times.
Parent Case Info
[0001] This application claims the benefit of U.S. provisional patent application No. 60/233,389, filed Sep. 18, 2000, which is hereby incorporated by reference herein in its entirety.
Provisional Applications (1)
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Number |
Date |
Country |
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60233389 |
Sep 2000 |
US |