Patent Application
20090235040
Many electronic devices often include a programmable memory component to store information about the device such as device identification (ID) and device configurations. Some conventional programmable memory components may store information in memory elements and use circuit latches to provide the stored information when the memory elements are read. In some of these programmable memory components, each memory element may have its own circuit latch. A conventional programmable memory component with a large number of memory elements and circuit latches may have a greater size or a lower storage density for a given area.
As shown in
Device 100 may include additional components 102, which may include a pixel array for use in sensing light for image processing, an array of memory cells for use as a main storage component of device 100, or both pixel array and memory cells. For example, when device 100 includes an image sensor device, additional components 102 may include a complementary metal-oxide-semiconductor (CMOS) pixel array or a charge-coupled device (CCD) pixel array. In another example, when device 100 includes a memory device, additional components 102 may include DRAM cells, SRAM cells, flash memory cells, phase change memory cells, or other types of memory cells.
Device 100 may also include a voltage generator 103 to receive a supply voltage Vsupply and generate different voltages for use in device 100, such as a voltage Vw and a voltage Vr used by programmable memory 101. Device 100 may include an input/output (I/O) circuit 104 to transfer data and information (represented by signals DATA) between device 100 and other devices external to device 100. Device 100 may include a controller 105 to control operations of device 100, such as write and read operations.
Device 100 may receive a write command in form of signals (e.g., write signals) on lines 106 to perform a write operation to selectively write information into storage units 111. Device 100 may receive a read command in form of signals (e.g., read signals) on lines 106 to perform a read operation to selectively read information from storage units 111. Controller 105 may include a decoder circuit 107 to decode signals (e.g., address signals) on lines 106 to allow device 100 to determine which one or more of storage units 111 are to be selected during a write or read operation. Controller 105 may provide control signals such as R/W, HVX, RSELX, CSELX, EQ, EN*, and EN to programmable memory 101, which may use these control signals during a write or read operation of device 100. The functions of these signals may be similar to or identical to the signals described below with reference to
Device 100 of
Device 100 may include the devices (e.g., device 200 and 300) described below with reference to
As shown in
Device 200 may receive a write command to perform a write operation to selectively write information into storage units 211, 212, 213, 221, 222, 223, 231, 232, and 233. Device 200 may write information in parallel (concurrently) or sequentially (one at a time) into any number of selected storage units or all of storage units 211, 212, 213, 221, 222, 223, 231, 232, and 233. Device 200 may receive a read command to perform a read operation to selectively read information from these storage units. Device 200 may read information in parallel or sequentially from selected storage units of storage units in the same row or in different rows. Device 200 may read information sequentially (not in parallel) from selected storage units of storage units in the same column.
A signal R/W may include different signal levels based on the write and read commands to indicate which one of the write and read operations device 200 performs. For example, the R/W signal may have a high signal level when device 200 performs a write operation and a low signal level when device 200 performs a read operation.
Programmable memory 201 may include a voltage selector 275, which may respond to the R/W signal to selectively provide a voltage Vw and a voltage Vr to line 270 as a voltage Vbus, depending on which one of the write and read operations device 200 performs. For example, voltage Vbus may correspond to voltage Vw during a write operation and to voltage Vr during a read operation. Voltage Vw may have a value greater than the value of voltage Vr. In some cases, voltage Vw may have a value of approximately three to five times the value of voltage Vr. For example, voltage Vw may have a value of approximately seven to ten volts and voltage Vr may have a value of approximately two to three volts. Since voltage Vw may have a value higher than that of voltage Vr, and since voltage Vbus may correspond to either voltage Vw (e.g., during a write operation) or voltage Vr (e.g., during a read operation), voltage Vbus may have a value that is relatively higher during a write operation than its value during a read operation. The relatively higher value of voltage Vbus during a write operation may be used to write information into storage units 211, 212, 213, 221, 222, 223, 231, 232, and 233.
Programmable memory 201 may include comparator circuits 281, 282, and 283 to generate output signals DOUT1, DOUT2, and DOUT3, respectively. The DOUT1 signal may have a value to represent the value of information read from storage unit 211, 212, or 213, depending on which storage unit among storage units 211, 212, and 213 is selected. The value of the DOUT1 signal may depend on a result of a comparison between a current I1 on line 271 and a current Iref on line 274. The DOUT2 signal may have a value to represent the value of information read from storage unit 221, 222, or 223, depending on which storage unit among storage units 221, 222, and 223 is selected. The value of the DOUT2 signal may depend on a result of a comparison between a current I2 on line 272 and current Iref on line 274. The DOUT3 signal may have a value to represent the value of information read from storage unit 231, 232, or 233, depending on which storage unit among storage units 231, 232, and 233 is selected. The value of the DOUT3 signal may depend on a result of a comparison between a current I3 on line 273 and current Iref on line 274. Comparator circuits 281, 282, and 283 may generate the DOUT1, DOUT2, and DOUT3 signals in parallel when storage units from different columns (one storage unit from a different column) are read in parallel. For example, comparator circuits 281, 282, and 283 may generate the DOUT1, DOUT2, and DOUT3 signals in parallel to represent information that is read in parallel from storage units 211, 221, and 231.
Programmable memory 201 may include a reference generator 276 to generate current Iref, which may have a value that is substantially stable over operating voltage and temperature of device 200. Reference generator 276 may include a bandgap current reference generator to generate current Iref. Device 200 may set current Iref at a value (e.g., a fixed value) so that comparator circuits 281, 282, and 283 may provide corresponding signals DOUT1, DOUT2, and DOUT3 with values based on values of currents 11, 12, and 13, respectively.
Each of currents 11, 12, and 13 may have a value based on information read from a selected storage unit in columns 251, 252, and 253, respectively. As shown in
Programmable memory 201 may include circuits 291, 292, and 293 to control lines 271, 272, and 273, respectively, during write and read operations. During a write operation, circuit 291 may couple line 271 to a node 299 when information is written into one or more of storage units 211, 212, and 213. Node 299 may have a voltage equal to, or substantially equal to, 0 volts. For example, node 299 may include a ground potential. During a read operation, circuit 291 may decouple line 271 from node 299 when information is read from one or more of storage units 211, 212, and 213. When it is decoupled from node 299, line 271 may “float,” e.g., be unconnected to a supply node, such as ground, of device 200. Each of circuits 292 and 293 may operate in a similar fashion to the operation of circuit 291. For example, during a write operation, circuit 292 may couple line 272 to node 299 when device 200 selects to write information into one or more of storage units 221, 222, and 223. During a read operation, circuit 292 may decouple line 272 from node 299 when device 200 selects to read information from one or more of storage units 221, 222, and 223. Circuit 293 may couple line 273 to node 299 when device 200 selects to write information into one or more of storage units 231, 232, and 233. Circuit 293 may decouple line 273 from node 299 when device 200 selects to read information from one or more of storage units 231, 232, and 233.
Device 200 may use signals HV1, RSEL1, HV2, RSEL2, HV3, and RSEL3 to selectively turn on transistors 262 and 263 of storage units 211, 212, 213, 221, 222, 223, 231, 232, and 233 to select one or more of these storage units. Device 200 may use signals CSEL1, CSEL2, and CSEL3 to allow circuits 291, 292, and 293, respectively, to either couple corresponding lines 271, 272, and 273 to node 299 or decouple corresponding lines 271, 272, and 273 from node 299. Device 200 may include a controller (omitted from
For example, to select storage unit 211, device 200 may use signals HV1 and RSEL1 to turn on transistors 262 and 263 in row 241. In this example, device 200 may use signal CSEL1 to allow circuit 291 to either couple line 271 (being associated with the selected storage unit 211 in this example) to node 299 if device 200 selects to write information into storage unit 211 or decouple line 271 from node 299 if device 200 selects to read information from storage unit 211. In another example, to select storage unit 222, device 200 may use signals HV2 and RSEL2 to turn on transistors 262 and 263 in row 242. In this example, device 200 may use signal CSEL2 to allow circuit 292 to either couple line 272 (being associated with the selected storage unit 222 in this example) to node 299 if device 200 selects to write information into storage unit 222 or decouple line 271 from node 299 if device 200 selects to read information from storage unit 222.
Device 200 may use signals HV1, RSEL1, HV2, RSEL2, HV3, RSEL3, CSEL1, CSEL2, and CSEL3 to select multiple storage units 211, 212, 213, 221, 222, 223, 231, 232, and 233 to write information in parallel into the multiple selected storage units, or to read information in parallel from the multiple selected storage units from multiple columns in parallel. Device 200 may write information in parallel into multiple selected storage units in different columns (one storage unit from a different column) or in the same column. The multiple selected storage units may come from the same row or from different rows. Device 200 may also write information in parallel into multiple entire columns. Device 200 may also write information sequentially into one entire column and then write information into the next entire column. Device 200 may read information in parallel from selected storage units from columns (one storage unit from a different column). The multiple selected storage units may come from the same row or from different rows. Device 200 may also read information sequentially from one entire row to the next entire row. Writing information into or reading information from storage units 211, 212, 213, 221, 222, 223, 231, 232, and 233 in parallel may reduce write or read time, improve device performance, or both.
Each of storage units 211, 212, 213, 221, 222, 223, 231, 232, and 233 may include different states to represent different values (e.g., binary values 0 and 1) of information to be stored therein. Each of these storage units may change from one state to another state (among the different states), depending on which value of the information is to be stored therein. Device 200 may perform a write operation to cause one or more selected storage unit of storage units 211, 212, 213, 221, 222, 223, 231, 232, and 233 to change from one state to another state. For example, as described above, during a write operation, device 200 may apply voltage Vbus with a value corresponding to the value of voltage Vw and use circuits 291, 292, and 293 to couple one or more of lines 271, 272, and 273 to node 299. The voltage difference between lines 270 and node 299 may cause the selected storage unit (or storage units) to change from one state to another state. Device 200 may allow a selected storage unit to remain at its state (e.g., the state before a write operation) if the value of the information to be stored in the selected storage unit corresponds to the state that the selected storage unit may already have. For example, if a selected storage unit has an open state and the value of the information to be stored into the selected storage unit also corresponds to the open state, then the controller of device 200 may direct device 200 to skip performing the write operation. Thus, in this example, device 200 does not perform the write operation.
Each memory element 261 of storage units 211, 212, 213, 221, 222, 223, 231, 232, and 233 may include programmable memory elements such as antifuse, fuse, or other types of memory elements.
Device 300 may use signals HVX, RSEL1, RSEL2, and RSEL3 to selectively turn on transistors 362 and 363 to select one or more of storage units 311, 312, and 313 during a write or read operation. Device 300 may include a circuit 390 having a transistor 395, which may respond a signal CSELX to couple line 371 to node 399 during the write operation or decouple line 371 from node 399 during the read operation. In a write operation, voltage Vbus may have a value that is higher than its value during a read operation. Transistor 362 may have a structure to withstand the relatively high value of voltage Vbus during a write operation to protect transistor 363 from damage.
Voltage Vbus may correspond to voltage Vbus of
Each of storage units 311, 312, and 313 may include different states based on the state of antifuse 361. An antifuse, such as antifuse 361, usually has two different states: a state when the antifuse is open (or “unfused”) and a state when the antifuse is closed (or “fused”). The antifuse normally has an open state to prevent conduction of current through it. The antifuse may allow conduction of current through it when it has a closed state. The antifuse often has a non-conductive material (e.g., an oxide of silicon or nitrogen) placed between its conductive terminals to electrically isolate the conductive terminals to allow the antifuse to normally (e.g., initially) have an open state. A write operation, such as the write operation described above, may change the state of the antifuse from the open state to the closed state by applying a high voltage between conductive terminals of the antifuse to modify the structure of the antifuse and create a conductive path through the non-conductive material to electrically connect (e.g., short-circuit) the conductive terminals.
In
In a write operation, device 300 may select one or more of storage units 311, 312, and 312 by turning on transistors 362 and 363 of the selected storage unit. Device 300 may turn off transistors 362 and 363 of the unselected storage unit (or storage units). For example, if device 300 selects to change the state of antifuse 361 of storage unit 311, device 300 may use signals HVX and RSEL1 to turn on transistors 362 and 363 of storage unit 311, and use signals RSEL2 and RSEL3 to turn off (or keep off) transistors 362 and 363 of storage units 312 and 313. Then, device 300 may apply a relatively higher value for voltage Vbus (e.g., the value of Vw of
In a read operation, device 300 may select one of storage units 311, 312, and 313 to read information from the selected storage unit by turning on transistors 362 and 363 of the selected storage unit. Device 300 may turn off transistors 362 and 363 of the unselected storage unit (or storage units). For example, if device 300 selects to read storage unit 311, device 300 may use signals HVX and RSEL1 to turn on transistors 362 and 363 of storage unit 311, and use signals RSEL2 and RSEL3 to turn off (or keep off) transistors 362 and 363 of storage units 312 and 313. Then, device 300 may apply a relatively lower value for voltage Vbus (e.g., the value of Vr of
Current sensing circuit 380 may receive current Ix during a read operation and compare it with current Iref to generate signal DOUTx. Current sensing circuit 380 may include nodes 375 and 376, nodes 372 and 373, and transistors 330, 331, 332, 333, 334, 335, 336, 337, 338, and 339 coupled in ways shown in
As shown in
The DOUTx signal may have one value (e.g., a value corresponding to binary value 1) when the value of current Ix is less than the value of current Iref (e.g., when antifuse 361 of a selected storage unit has an open state). The DOUTx signal may have another value (e.g., a value corresponding to binary value 0) when the value of current Ix is greater than the value of current Iref (e.g., when antifuse 361 of a selected storage unit has a closed state).
As show in
The following description refers to both
As shown in
In the write operation, the EQ and EN signals have signal value 402, and the EN* signal has signal value 401 to deactivate current sensing circuit 380. In the read operation, these EQ, EN*, EN signals may change their signal values (e.g., signal values opposite from those during the write operation) to activate current sensing circuit 380. For example, during the read operation, the EQ signal has signal value 402 before time T3 to turn on transistors 335 and 336 to electrically couple nodes 372, 373, 375, and 376 to each other. Then, after the CSELX signal may change from signal value 402 to signal value 401 at time T3, the EQ signal may change from signal value 402 to signal value 401 after a time delay 451 from time T3 to turn off transistors 335 and 336 to electrically decouple nodes 372, 373, 375, and 376 from each other in preparation for the DOUTx signal to be generated. After nodes 372, 373, 375, and 376 are electrically decoupled from each other, the EN* and EN signals may change to signal values 402 and 401, respectively. As shown in
Device 300 may include a signal generator, such as the signal generator of
As shown in
Processor 610 may include a general-purpose processor or an application specific integrated circuit (ASIC). Processor 610 may comprise a single core processor or a multiple-core processor. Processor 610 may execute one or more programming commands to process information. The information may include output information provided by other components of system 600, such as by image sensor device 620 or memory device 625.
Image sensor device 620 may include a CMOS image sensor having a CMOS pixel array. Image sensor device 620 may include a CCD image sensor having a CCD pixel array. Image sensor device 620 may include one or more embodiments described above with reference to
Memory device 625 of
Display 652 may include an analog display or a digital display. Display 652 may receive information from other components. For example, display 652 may receive information that is processed by one or more of image sensor device 620, memory device 625, graphics controller 640, and processor 610 to display information such as text or images.
The illustrations of the apparatus such as devices 100, 200, and 300 and signal generator 505 and a system such as system 600 are intended to provide a general understanding of the structure of various embodiments, and not a complete description of all the elements and features of apparatus and systems that might make use of the structures described herein.
Any of the components described above can be implemented in a number of ways, including simulation via software. Thus, apparatus (e.g., devices 100, 200, and 300 and signal generator 505) and systems (e.g., a portion of system 600 or the entire system 600) described above may all be characterized as “modules” (or “module”) herein. Such modules may include hardware circuitry, single and/or multi-processor circuits, memory circuits, software program modules and objects and/or firmware, and combinations thereof, as desired by the architect of the apparatus (e.g., devices 100, 200, and 300 and signal generator 505) and systems (e.g., system 600), and as appropriate for particular implementations of various embodiments. For example, such modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and distribution simulation package, a capacitance-inductance simulation package, a power/heat dissipation simulation package, a signal transmission-reception simulation package, and/or a combination of software and hardware used to operate or simulate the operation of various potential embodiments.
The apparatus and systems (e.g., devices 100, 200, and 300 and signal generator 505 and system 600) of various embodiments may include or be included in electronic circuitry used in high-speed computers, communication and signal processing circuitry, single or multi-processor modules, single or multiple embedded processors, multi-core processors, data switches, and application-specific modules including multilayer, multi-chip modules. Such apparatus and systems may further be included as sub-components within a variety of electronic systems, such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others.
One or more embodiments described herein include apparatus, systems, and methods having storage units coupled in parallel between a first line and a second line, and a comparator circuit coupled to the second line. The first line may be configured to provide different voltages. The comparator circuit may be configured to compare a first current on the second line with a second current to provide an output signal. Other embodiments, including additional apparatus, systems, and methods are described above with reference to
The above description and the drawings illustrate some embodiments of the invention to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other changes. In the drawings, like features or like numerals describe substantially similar features throughout the several views. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of others. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. Therefore, the scope of various embodiments of the invention is checked by the appended claims, along with the full range of equivalents to which such claims are entitled.
The Abstract is provided to comply with 37 C.F.R. §1.72(b) requiring an abstract that will allow the reader to quickly ascertain the nature and gist of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
