Patent Application
20050247554
The inventions relate generally to sputtering. In particular, the invention relates to the sputter deposition of material in the formation of semiconductor integrated circuits.
Semiconductor integrated circuits such as complementary metal oxide silicon (CMOS) devices may include a silicide layer to provide low sheet resistance on gate, source or drain regions. A silicide is a compound formed in a reaction between a metal and silicon or polysilicon. In addition to CMOS, silicide can be a useful component of a variety of other semiconductor devices, particularly where a low sheet resistance or low contact resistance is desired.
Various metals may be deposited on silicon or polysilicon to react with the underlying silicon to form the silicide. Titanium is commonly reacted with silicon to form titanium silicide, TiSi2. It has also been proposed to use cobalt and nickel to form silicides.
The reaction between the metal layer 10 and the polysilicon gate 16 or the silicon region 20 is often facilitated by the application of heat, either during the deposition of the metal layer 20 or after the metal deposition.
In many applications, it is often preferred that the metal layer 10 be formed in an extremely thin film such as 50 A (angstroms), for example. Such thin films can reduce or minimize the consumption of silicon in the silicide formation process and thus facilitate maintaining the integrity of the shallow junctions in the source and drain regions. However, such thin films are often difficult to achieve with a desired degree of uniformity over nonplanar structures such as those shown in
As integrated circuits become more densely packed, the spacing between adjacent vertical structures is shrinking. In addition, the relative height of the vertical structures is growing increasingly tall. As a consequence, the spaces between adjacent gate structures can in effect become deep “holes” 40 as shown in
Semiconductor integrated circuits also utilize metal layers to interconnect various devices. These circuits can include multiple levels of metal layers or “metallizations” to provide electrical connections between large numbers of active semiconductor devices. Advanced integrated circuits, particularly those for microprocessors, may include five or more metallization levels.
A typical metallization level is illustrated in the cross-sectional view of
A via hole is etched into the upper-level dielectric layer 114 typically using, in the case of silicate dielectrics, a fluorine-based plasma etching process. A preferred technique for metallization, called dual damascene, forms the hole in the dielectric layer 114 into two connected portions, the first being narrow vias through the bottom portion of the dielectric and the second being wider trenches in the surface portion which interconnect the vias.
There are yet other shapes for “holes” including lines and trenches. Also, in dual damascene and similar interconnect structures, as described below, the holes may have a complex shape. In some applications, the hole may not extend through the dielectric layer. The following discussions will often refer to vias and gate spacing holes, but in most circumstances the discussion applies equally well to other types of holes with only a few modifications well known in the art.
A liner layer 116 may be deposited onto the bottom and sides of the hole and above the dielectric layer 114. The liner 116 can perform several functions. It can act as an adhesion layer between the dielectric and the metal since metal films tend to peel from oxides. It can also act as a barrier against inter-diffusion between the oxide-based dielectric and the metal. It may also act as a seed and nucleation layer to promote the uniform adhesion and growth and possibly low-temperature reflow for the deposition of metal filling the hole and to nucleate the even growth of a separate seed layer. One or more liner layers may be deposited, in which one layer may function primarily as a barrier layer and others may function primarily as adhesion, seed or nucleation layers. An interconnect layer 118 of a conductive metal may be deposited over the liner layer 116 to fill the hole and to cover the top of the dielectric layer 114.
Lining or otherwise depositing metal into via holes and similar high aspect-ratio structures such as the gate spacing holes 40 described above, have presented a continuing challenge as their aspect ratios continue to increase. An aspect ratio as used herein is defined as the ratio of the depth of the hole to narrowest width of the hole. In advanced integrated circuits, the via holes may have widths as low as 0.18 μm or even less. The thickness of the dielectric layer 114 is usually at least 0.7 μm, and sometimes twice this, so that the aspect ratio of the hole may be 4:1 or greater. For example, aspect ratios of 6:1 and greater are being proposed.
The deposition of a metal layer by conventional physical vapor deposition (PVD), also called sputtering, is relatively fast. A DC magnetron sputtering reactor has a target which is composed of the metal to be sputter deposited and which is powered by a DC electrical source. The magnetron is scanned about the back of the target and projects its magnetic field into the portion of the reactor adjacent the target to increase the plasma density. The target is typically negatively biased to attract the ions generated in the plasma to sputter the target.
The rate at which material is sputtered from the target may be controlled by controlling the power of the source biasing the target. Because a relatively thin metal deposition is often desired for silicide formation, a low sputtering rate is often desired to facilitate controlling the thickness of the deposition. Consequently, the power level of the target biasing source may be set relatively low to assist in achieving the desired thin layer deposition.
However, conventional DC sputtering (which will be referred to as PVD in contrast to other types of sputtering to be introduced) predominantly sputters neutral atoms. The typical ion densities in PVD are often less than 109 cm−3. PVD also tends to sputter atoms into a wide angular distribution, typically having a cosine dependence about the target normal. Such a wide distribution can be disadvantageous for filling a deep and narrow gate spacing hole 40 such as that illustrated in
A recently developed technology of self-ionized plasma (SIP) sputtering allows plasma sputtering reactors to be only slightly modified but to nonetheless achieve efficient lining of metals into high aspect-ratio holes in a low-pressure, low-temperature process. This technology has been described by Fu et al. in U.S. Pat. No. 6,290,825 and by Chiang et al. in U.S. patent application Ser. No. 09/414,614, filed Oct. 8, 1999, both incorporated herein by reference in their entireties. For example, at a sufficiently high plasma density adjacent a target, a sufficiently high density of target metal ions can develop that ionizes additional metal sputtered from the target. As noted above, such a plasma is referred to as a self-ionizing plasma (SIP). The sputtered metal ions may be accelerated across the plasma sheath and toward a biased wafer, thus increasing the directionality of the sputter flux and decreasing scattering of metal particles by the argon. As a result, bottom coverage in deep and narrow holes may be improved. However, to achieve a sufficiently high rate of ionization, the power of the biasing applied to the target may be raised to a level which increases the sputtering rate above that desired to achieve a thin metal layer. SIP sputtering including sustained self-sputtering (SSS), is also described by Fu et al. in U.S. patent application Ser. No. 08/854,008, filed May 8, 1997 and by Fu in U.S. Pat. No. 6,183,614 B1, Ser. No. 09/373,097, filed Aug. 12, 1999.
Ionizing plasmas may also be generated by capacitive coupling. In such chambers, RF energy may be capacitively coupled into the chamber through parallel electrodes such as the wafer pedestal and the target. However, again, the power applied to the target may cause the sputtering rate to rise beyond desirable levels for thin film deposition.
One embodiment of the present inventions is directed to sputter depositing a metal layer by biasing a sputter target with pulsed power in which the power applied to the target alternates between low and high levels. The high levels are, in one embodiment, sufficiently high to maintain a plasma for ionizing deposition material. The low levels are, in one embodiment, sufficiently low such that the power applied to the target during the high and low levels is, on average, low enough to facilitate deposition of thin layers if desired.
In the illustrated embodiment, the power applied to bias the target is modulated in a plurality of alternating first and second intervals wherein in each of the first intervals, the power level is at a first level sufficiently high to attract ions to sputter the target. In each of the second intervals, the power is applied at a second level higher than the first level and sufficiently high not only to sputter the target but also to maintain a plasma adjacent the target capable of ionizing target material sputtered from said target. Thus, the target is continuously sputtered once deposition onto the wafer is initiated. In the illustrated embodiment the durations of the first intervals of lower power application can be selected to be longer than the durations of the second intervals of higher power application to reduce further the average of the power applied to the target.
Because the power applied during the first intervals is lower than the power applied during the second intervals which alternate with the first intervals, the sputtering rate of the target can be substantially reduced during the first intervals as compared to that of the second intervals. As a consequence, it is believed that the average sputtering rate can be sufficiently low to facilitate deposition of thin layers of metal.
On the other hand, because the power applied during the second intervals is higher than the power applied during the first intervals which alternate with the second intervals, the rate at which target material sputtered from the target is ionized prior to deposition can be significantly increased during the second intervals as compared to that of the first intervals. As a consequence, it is believed that the average ionization rate can be sufficiently high to provide good bottom coverage of deep and narrow holes in CMOS and other structures.
In the illustrated embodiment, a generally planar target coupled with an unbalanced magnetron generate a self-ionizing plasma, particularly when biased at sufficiently high levels of biasing power in the second intervals in which the higher power level is applied to the target. It is appreciated that other types of sputtering targets and magnetrons may be used. For example, hollow cathode targets may be used as well as targets which generate an ionizing plasma by capacitively coupling energy from the target and the workpiece holder into the plasma.
There are additional aspects to the present inventions as discussed below. It should therefore be understood that the preceding is merely a brief summary of some embodiments and aspects of the present inventions. Additional embodiments and aspects of the present inventions are referenced below. It should further be understood that numerous changes to the disclosed embodiments can be made without departing from the spirit or scope of the inventions. The preceding summary therefore is not meant to limit the scope of the inventions. Rather, the scope of the inventions is to be determined only by the appended claims and their equivalents.
A reactor which is believed capable of providing, for example, both a low average sputtering rate and a sufficiently high deposition material ionization rate for good bottom coverage, is indicated generally at 140 in
The reactor 140 includes a vacuum chamber 142, usually of metal and electrically grounded, sealed through a target isolator 144 to a PVD target 146 having at least a surface portion composed of the material to be sputter deposited on a wafer 148. A magnetron 150 coupled to the target 146 generates a plasma adjacent to the target for sputtering the target and ionizing the sputtered deposition material.
The wafer also referred to as a substrate or workpiece, may be different sizes including 150, 200, 300 and 450 mm. In addition to silicon, the wafer may be composed of glass or other materials. A pedestal electrode 152 has a support surface which supports the wafer and biases the wafer 148 to attract ionized deposition material. A wafer clamp 160 holds the wafer 148 on the pedestal electrode 152. Resistive heaters, refrigerant channels, and a thermal transfer gas cavity in the pedestal 152 can be provided to allow the temperature of the pedestal to be controlled to temperatures of less than −40° C., thereby allowing the wafer temperature to be similarly controlled.
The reactor 140 also biases the target 146. In one aspect of the illustrated embodiments, the power applied to bias the target is modulated in a plurality of alternating first and second intervals wherein in each of the first intervals, the power level is at a first level sufficiently high to attract ions to sputter the target but at a relatively low sputtering rate if desired. In each of the second intervals, the power is applied at a second level higher than the first level and sufficiently high not only to sputter the target but also to maintain a plasma adjacent the target capable of ionizing target material sputtered from said target. The overall sputtering rate will be an average of the sputtering rates in the alternating intervals. As a consequence, the average sputtering rate can be sufficiently low to facilitate thin film deposition and the ionization rate can be sufficiently high to provide good bottom coverage in high aspect ratio holes. In the illustrated embodiment the durations of the first intervals of lower power application can be selected to be longer than the durations of the second intervals of higher power application to reduce further the average of the power applied to the target.
A darkspace shield 164 and a chamber shield 166 separated by a second dielectric shield isolator 168 are held within the chamber 142 to protect the chamber wall 142 from the sputtered material. In one embodiment, the darkspace shield 164 is permitted to float electrically and the chamber shield 166 is electrically grounded. However, in some embodiments, either or both shields may be grounded, floating or biased to the same or different nonground levels. The chamber shield 166 can also act as an anode grounding plane in opposition to the cathode target 146 and the RF pedestal electrode 152, thereby capacitively supporting a plasma. If the darkspace shield is permitted to float electrically, some electrons can deposit on the darkspace shield 164 such that a negative charge builds up there. It is believed that the negative potential could not only repel further electrons from being deposited, but also confine the electrons in the main plasma area, thus reducing the electron loss, sustaining low-pressure sputtering, and increasing the plasma density, if desired. The plasma darkspace shield 164 is generally cylindrically-shaped. The plasma chamber shield 166 is generally bowl-shaped and includes a generally cylindrically shaped, vertically oriented wall 170. It is appreciated that the shields may have other shapes as well.
Superimposed on the DC component is the plurality of pulses 204, each of which alternates between a “pulse low” interval in which the power minimum Pmin as represented by the DC component 206 is applied to the target, and a “pulse high” interval in which a power maximum as represented by Pmax is applied to the target. During each “pulse low” interval, the power applied to the target is relatively low. As a consequence, the plasma density adjacent the target, the target sputtering rate and the deposition material ionization rate are all relatively low during each pulse low interval. In the illustrated embodiment, it is preferred that the minimum power Pmin of each pulse low interval remain nonzero such that at least the sputtering rate remains nonzero during the pulse low intervals. It is believed that such an arrangement facilitates plasma stability and uniformity of results from wafer to wafer.
During each “pulse high” interval, power Pmax applied to the target is higher. As a consequence, the plasma density adjacent the target, the target sputtering rate and the deposition material ionization rate are higher during each pulse high interval. In the illustrated embodiment, the power level Pmax of each pulse high interval is sufficiently high to maintain a self ionizing plasma (SIP) to ionize a significant portion of the material being sputtered from the target during each pulse high period. As a consequence, it is believed that bottom coverage of deep aspect ratio holes may be achieved yet maintaining a sufficiently low average sputtering rate to facilitate thin film depositions. One example of an expected improved coverage is depicted in
The power level applied during the pulse high intervals will vary, depending upon the particular application. For example, for deposition of cobalt or nickel, it is believed that a power level Pmax in the range of 15-25 K watts would be suitable during the pulse high intervals. For deposition of titanium, tantalum or their nitrides, a range of 20-30 K watts is believed to be suitable. For deposition of copper, a range of 30-80 K watts is believed to be suitable.
Although the sputtering rate of the target may rise substantially during each pulse high interval, it is appreciated that the average power Pavg applied to the target is lower than the maximum power Pmax. Consequently, the average sputtering rate will similarly be lower than the sputtering rate during the pulse high intervals alone. For thin film applications, it is believed that a suitably low average sputtering rate may be achieved by appropriate selections of the high and low power levels, Pmax and Pmin, and the durations of the respective pulse low and pulse high intervals. For many such applications, it is believed that providing pulse low intervals longer in duration than pulse high intervals may provide suitable results.
In the illustrated embodiment, deposition of a thin layer may be accomplished in 30 seconds for example. During this 30 second deposition period, the power supply to the target may be pulsed at a frequency of 10 Hz, for example. At this frequency, there would be 10 cycles of alternating pulse high and pulse low intervals during each second of deposition. If so, each cycle of one pulse high interval and one pulse low interval would have a duration of 0.1 seconds. Thus, during a 30 second deposition, the power to the target would be pulsed in 300 cycles. The pulse frequency may vary, depending upon the application. It is believed that a pulse frequency in the range of 1-100 Hz or more preferably 5-20 Hz may be appropriate for a number of applications. Also, the duration of the layer deposition may vary as well. At present, for depositions lasting 10-50 seconds, 10-500 cycles of high and low pulses during the deposition is believed to be appropriate.
Within each cycle, it is generally preferred that the duration of the pulse low interval be longer than that of the pulse high interval in each cycle. The ratio of the duration of the pulse high interval to the duration of the cycle (the duty cycle) may range from ½ to ⅛, for example. Values for the parameters including Pmax, Pmin, and the interval durations may be determined empirically. These parameters may be affected by the particular design goals of the application including repeatability of results, the thickness of the deposited layer and the uniformity of the deposited layer. In the illustrated embodiment, an average power Pavg in the range of 15-30 kW for material such as Ti is believed to be suitable.
In the illustrated embodiment, the values Pmax, Pmin, and the pulse high and pulse low interval durations are depicted as being relatively constant from interval to interval. It is appreciated that these values may vary from interval to interval, and within each interval, depending upon the particular application. Moreover, the voltage or current output of the source 200 may be modulated as appropriate.
A source 210 applies RF power to the pedestal electrode 152 to bias the wafer 148 to attract deposition material ions during SIP sputter deposition. In addition, the source 210 may be configured to apply RF power to the pedestal electrode 152 to couple supplemental energy to the plasma. During SIP deposition, the pedestal 152 and hence the wafer 148 may be left electrically floating, but a negative DC self-bias may nonetheless develop on it. Alternatively, the pedestal 152 may be negatively biased by a source at a negative voltage of −30 VDC, for example, to negatively bias the wafer 148 to attract the ionized deposition material to the substrate.
If the source 210 biasing the wafer through the pedestal is an RF power supply, the supply may operate at a frequency of 13.56 MHz, for example. Other frequencies are suitable such as 60 MHz, depending upon the particular application. The pedestal 152 may be supplied with RF power in a range of 10 watts to 5 kW, for example, a more preferred range being 150 to 300 W for a 200 mm wafer in SIP deposition.
The above-mentioned power and voltage levels and frequencies may vary of course, depending upon the particular application. A computer-based controller 224 may be programmed to control the power levels, voltages, currents and frequencies of the various sources in accordance with the particular application.
Retuming to the large view of
The shields 164, 166 are typically composed of stainless steel, and their inner sides may be bead-blasted or otherwise roughened to promote adhesion of the material sputter deposited on them. At some point during prolonged sputtering, however, the deposited material builds up to a thickness that is likely to flake off, producing deleterious particles. Before this point is reached, the shields 164, 166 should be cleaned or replaced. However, the more expensive isolators 144, 168 do not need to be replaced in most maintenance cycles. Thus, the maintenance cycle is determined by flaking of the shields.
As mentioned, the darkspace shield 164, if floating can accumulate some electron charge and build up a negative potential. Thus biased, it repels further electron loss to the darkspace shield 164 and confines the plasma nearer the target 146. Ding et al. have disclosed a similar effect with a somewhat similar structure in U.S. Pat. No. 5,736,021. In selecting an appropriate darkspace shield, it is noted that the darkspace shield 164 electrically shields the chamber shield 166 from the target 146 so that it should not extend too far away from the target 146. If it is too long, it is believed it can become more difficult to strike the plasma; but, if it is too short, it is believed that electron loss can increase such that sustaining the plasma at lower pressure is more difficult and the plasma density may fall. In the illustrated embodiment, the shield 164 has an axial length of 7.6 cm but may range from 6-10 cm in a preferred embodiment.
Referring again to
To provide efficient sputtering, the magnetron 150 is positioned in back of the target 146. It has opposed magnets 324a, 324b connected and supported by a magnetic yoke 336. The magnets create a magnetic field adjacent the magnetron 150 within the chamber 142. The magnetic field traps electrons and, for charge neutrality, the ion density also increases to form a high-density plasma region 338. The magnetron 150 is usually rotated about the center axis 340 of the target 146 by a motor-driven shaft 342 to achieve full coverage in sputtering of the target 146. To achieve a high-density plasma 338 of sufficient ionization density to allow self-ionization, the power density delivered to the area adjacent the magnetron 150 is preferably made high during the pulse high intervals. It is believed that this may be achieved by increasing the power level delivered from the power supply 200 during the pulse high intervals and by reducing the area of magnetron 150, for example, in the shape of a triangle or a racetrack. A 60-degree triangular magnetron, which is rotated with its tip approximately coincident with the target center 340, covers only about ⅙ of the target at any time. Coverage of ¼ is the preferred maximum in a commercial reactor capable of SIP sputtering.
To decrease the electron loss, the inner magnetic pole represented by the inner magnet 324b and magnetic pole face should have no significant apertures and be surrounded by a continuous outer magnetic pole represented by the outer magnets 324a and pole face. Furthermore, to guide the ionized sputter particles to the wafer 148, the outer pole should produce a much higher magnetic flux than the inner pole. The extending magnetic field lines trap electrons and thus extend the plasma closer to the wafer 148. The ratio of magnetic fluxes should be at least 150% and preferably greater than 200%. Two embodiments of Fu's triangular magnetron have 25 outer magnets and 6 or 10 inner magnets of the same strength but opposite polarity.
When the argon is admitted into the chamber, the DC voltage difference between the target 146 and the chamber shield 166 ignites the argon into a plasma, and the positively charged argon ions are attracted to the negatively charged target 146. The ions strike the target 146 at a substantial energy and cause target atoms or atomic clusters to be sputtered from the target 146. Some of the target particles strike the wafer 148 and are thereby deposited on it, thereby forming a film of the target material. In reactive sputtering of a metallic nitride, nitrogen is additionally admitted into the chamber from a source 343, and it reacts with the sputtered metallic atoms to form a metallic nitride on the wafer 148.
In operation, a gate valve operatively coupled to the exhaust outlet 322 is fully opened in order to achieve the desired vacuum level of about 1×10−8 Torr in the deposition chamber 142 prior to introduction of the process gas(es) into the chamber. To commence processing within the sputtering chamber 142, argon or other process gasses are flowed into the sputtering chamber 142 via a gas inlet 360. After the gas stabilizes at a pressure of about 0.1-40 milliTorr (preferably 1-5 milliTorr), power is applied to the target 146 via the power supply 200. The gas mixture continues to flow into the sputtering chamber 142 via the gas inlet 360 and is pumped therefrom via the pump 320 to maintain gas pressure in the chamber. The power applied to the target 146 causes the gas to form an SIP plasma and to generate ions such as argon ions which are attracted to and strike the target 146, causing target material (e.g., cobalt or nickel) to be ejected therefrom. The ejected target material travels to and deposits on the wafer 148 supported by the pedestal 152. In accordance with the SIP process, the plasma created by the unbalanced magnetron ionizes a portion of the sputtered target material. By adjusting the RF power signal applied to the substrate support pedestal 152, a negative bias can be created between the substrate support pedestal 152 and the plasma. The negative bias between the substrate support pedestal 152 and the plasma causes target material ions and argon ions to accelerate toward the pedestal 152 and any wafer supported thereon. Accordingly, both neutral and ionized target material may be deposited on the wafer, providing good sidewall and upper sidewall coverage in accordance with SIP sputtering. In addition, particularly if sufficient RF power is optionally applied to the pedestal the wafer may be sputter-etched by the argon ions at the same time the material from the target 146 deposits on the wafer (i.e., simultaneous deposition/sputter-etching).
In one embodiment, the chamber 142 may be capable of self-ionized sputtering including sustained self-sputtering (SSS). In this case, after the plasma has been ignited, the supply of argon may be cut off in the case of SSS, and the metal ions may have sufficiently high density to resputter the target with a yield of greater than unity. Alternatively, some argon may continue to be supplied, but at a reduced flow rate and chamber pressure and perhaps with insufficient target power density to support pure sustained self-sputtering but nonetheless with a significant but reduced fraction of self-sputtering. It is believed that if the argon pressure is increased to significantly above 5 milliTorr, the argon will remove energy from the metal ions, thus decreasing the self-sputtering. The wafer bias attracts the ionized fraction of the metal particle deep into the hole.
To achieve deeper hole coating with a partially neutral flux, it may be desirable to increase the distance between the target 146 and the wafer 148, that is, to operate in a long-throw mode. In previously practiced long-throw, the target-to-substrate spacing is typically greater than half the substrate diameter, or greater than 100% wafer diameter, or at least 80% of the substrate diameter, or at least 90% of the substrate diameter, or at least 140% of the substrate diameter. The throws mentioned in the examples of the present embodiment are referenced to 200 mm wafers. For many applications, it is believed that a target to wafer spacing of 50 to 1000 mm will be appropriate. Long-throw in conventional sputtering reduces the sputtering deposition rate, but ionized sputter particles typically do not suffer a large decrease.
Many of the features of the apparatus and process of the inventions can be applied to sputtering not involving long throw. Although it is believed that the inventions are particularly useful at the present time for silicide layer formation, the different aspects of the invention may be applied to sputtering other materials and for other purposes.
It will, of course, be understood that modifications of the present invention, in its various aspects, will be apparent to those skilled in the art, some being apparent only after study, others being matters of routine mechanical and process design. Other embodiments are also possible, their specific designs depending upon the particular application. As such, the scope of the invention should not be limited by the particular embodiments herein described but should be defined only by the appended claims and equivalents thereof.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10322230 | Dec 2002 | US |
| Child | 11064689 | Feb 2005 | US |
