Patent Application
20230062092
Embodiments disclosed herein pertain to recessed access devices and to methods of forming recessed access devices.
A recessed access device is a field effect transistor having its gate construction buried within a trench formed in semiconductive material. The gate construction includes a gate insulator which lines the trench and conductive gate material within the trench laterally inward of the gate insulator. A source/drain region is formed in outermost regions of the semiconductive material on each of opposing sides of the trench. When the two source/drain regions are at different voltages and a suitable voltage is applied to the conductive gate material, current (Ion) flows through the semiconductive material between the source/drain regions along the trench sidewalls and around the base of the trench (i.e., a conductive channel forms through which current flows between the two source/drain regions). Recessed access devices are typically devoid of non-volatile charge-storage devices (yet may be fabricated to include such), and regardless may be used in memory circuitry, for example DRAM circuitry. It is desirable to attain high device on-current (Ion) and low device off-current (e.g., leakage current Ioff) in recessed access devices.
Embodiments of the invention encompass recessed access devices, for example as might be in DRAM constructions, and methods of forming recessed access devices. First example embodiments are initially described with reference to
Example base substrate 11 comprises semiconductor material 12 (e.g., appropriately and variously doped monocrystalline silicon and/or other semiconductive material) comprising a pair of recessed access devices 116.
A pair of source/drain regions 24, 26 are in upper portions of semiconductor material 12 on opposing lateral sides of trench 19. Each of source/drain regions 24, 26 likely comprises at least a part thereof having a conductivity-increasing dopant therein that is of maximum concentration of such conductivity-increasing dopant within the respective source/drain region 24, 26, for example to render such part to be conductive (e.g., having a maximum dopant concentration of at least 1019 atoms/cm3). Accordingly, all or only a part of each source/drain region 24, 26 may have such maximum concentration of conductivity-increasing dopant (indicated by stippling). Source/drain regions 24 and/or 26 may include other doped regions (not shown), for example halo regions, LDD regions, etc.
In the depicted example, one of the source/drain regions (e.g., region 26) of the pair of source/drain regions is laterally between conductive gates 18 and is shared by immediately-adjacent recessed access devices 116. Others of the source/drain regions (e.g., regions 24) of individual of the pairs of source/drain regions are not shared by immediately-adjacent recessed access devices 116. A digitline 130 is directly electrically coupled to the one shared source/drain region 26. A pair of capacitors 118 individually are directly electrically coupled to one of the other source/drain regions 24.
Example recessed access devices 116 comprise a channel region 27 that is in the semiconductor material 12 below the pair of source/drain regions 24, 26 and extends along sidewalls 25 and around a bottom 28 of trench 19. Channel region 27 may be suitably doped with a conductivity-increasing dopant likely of the opposite conductivity-type of the dopant in source/drain regions 24, 26, and for example that is at a maximum concentration in the channel of no greater than 1×1016 atoms/cm3. When suitable voltage is applied to conductive gate 18, a conductive channel forms (e.g., along a channel current-flow line/path 29) within channel region 27 proximate gate insulator 20 such that current can flow between pair of source/drain regions 24 and 26.
In one embodiment, gate insulator 20 comprises a low-k material 30 (in some embodiments referred to as low-k gate-insulator material) and a high-k material 32 (in some embodiments referred to as high-k gate-insulator material). Low-k material 30 is characterized by its dielectric constant k being no greater than 4.0 (e.g., no less than 0.5). In one embodiment, low-k material comprises at least one of SiO2 and SiaObNc, and in one such embodiment where the at least one of the SiO2 and SiaObNc is carbon-doped (e.g., from 0.01 to 10.0 atomic percent).
In one embodiment, high-k material 32 is both (a) and (b), where:
In one embodiment, “x” is 0.999 to 0.96 and “y” is 0.001 to 0.04. In one embodiment, “M” comprises Al. In one embodiment, “M” comprises at least one of La, Lu, Yb, Er, Dy, Gd, Pr, Y, Hf, Zr, Mg, Sr, and Ti. In one embodiment, “M” is only one metal from Group 2, Group 3, Group 4, Group 5, and the lanthanide series of the periodic table, and in one such embodiment “M” is from the lanthanide series. Alternately, “M” is more than one metal from Group 2, Group 3, Group 4, Group 5, and the lanthanide series of the periodic table.
In one embodiment, low-k material 30 has its dielectric constant k at 3.0 to 4.0 and high-k material 32 has its dielectric constant k at 10.0 to 40.0. In one embodiment, low-k material 30 is devoid of SixMyO (no detectable SixMyO therein). In another embodiment, low-k material 30 comprises SixMyO, for example as described in example embodiments below. In one embodiment, high-k material 32 has its top 33 above top 31 of conductive gate 18. In one embodiment, low-k material 30 has its top 35 below top 31 of conductive gate 18.
Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments.
High-k material 32 may be homogenous or non-homogenous (as may be low-k material 20).
In one embodiment, the high-k material is both aside the low-k material laterally-inward thereof and above the low-k material. One such example embodiment construction 8b comprising a pair of recessed access devices 116b is shown in
An alternate example embodiment construction 8c comprising a pair of recessed access devices 116c is shown in
The embodiments of
An alternate example embodiment construction 8f comprising a pair of recessed access devices 116f is shown in
A possible, although not required, advantage of some embodiments of the invention over some constructions of the prior art is reduction of a phenomenon known as gate-induced-drain-leakage (GIDL) at an LDD junction when such a junction is present. Such reduced GIDL may enable use of an all-metal-material gate 18 as opposed to conductive polysilicon-over-metal material of some prior art gate constructions which may thereby increase conductivity (reduce resistance) of gate 18.
Embodiments of the invention encompass methods of forming a recessed access device. Embodiments of the invention encompass a recessed access device independent of method of manufacture. Nevertheless, such recessed access device may have any of the attributes as described herein in method embodiments. Likewise, the described method embodiments may incorporate, form, and/or have any of the attributes described with respect to structure embodiments.
An example embodiment of a method of forming a recessed access device in accordance with the invention is first described with reference to
A lining is formed in the trench laterally-inward of the low-k gate-insulator material, with the lining comprising at least one of elemental-form M, alloy-form M, and a metal oxide (regardless of whether stoichiometric), where M or the metal of the metal oxide is one or more of Al, metal(s) from Group 2, Group 3, Group 4, Group 5, and the lanthanide series of the periodic table. In one embodiment, the lining comprises at least one of elemental-form M and alloy-form M, in one embodiment comprises the metal oxide, and in one embodiment comprises at least one of elemental-form M and alloy-form M and comprises the metal oxide.
In one embodiment, the lining is directly against some and only some of the low-k gate-insulator material that is in the trench. For example, and by way of example only,
Referring to
Referring to
Referring to
Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.
Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.
The above processing(s) or construction(s) may be considered as being relative to an array of components formed as or within a single stack or single deck of such components above or as part of an underlying base substrate (albeit, the single stack/deck may have multiple tiers). Control and/or other peripheral circuitry for operating or accessing such components within an array may also be formed anywhere as part of the finished construction, and in some embodiments may be under the array (e.g., CMOS under-array). Regardless, one or more additional such stack(s)/deck(s) may be provided or fabricated above and/or below that shown in the figures or described above. Further, the array(s) of components may be the same or different relative one another in different stacks/decks and different stacks/decks may be of the same thickness or of different thicknesses relative one another. Intervening structure may be provided between immediately-vertically-adjacent stacks/decks (e.g., additional circuitry and/or dielectric layers). Also, different stacks/decks may be electrically coupled relative one another. The multiple stacks/decks may be fabricated separately and sequentially (e.g., one atop another), or two or more stacks/decks may be fabricated at essentially the same time.
The assemblies and structures discussed above may be used in integrated circuits/circuitry and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.
In this document unless otherwise indicated, “elevational”, “higher”, “upper”, “lower”, “top”, “atop”, “bottom”, “above”, “below”, “under”, “beneath”, “up”, and “down” are generally with reference to the vertical direction. “Horizontal” refers to a general direction (i.e., within 10 degrees) along a primary substrate surface and may be relative to which the substrate is processed during fabrication, and vertical is a direction generally orthogonal thereto. Reference to “exactly horizontal” is the direction along the primary substrate surface (i.e., no degrees there-from) and may be relative to which the substrate is processed during fabrication. Further, “vertical” and “horizontal” as used herein are generally perpendicular directions relative one another and independent of orientation of the substrate in three-dimensional space. Additionally, “elevationally-extending” and “extend(ing) elevationally” refer to a direction that is angled away by at least 45° from exactly horizontal. Further, “extend(ing) elevationally”, “elevationally-extending”, “extend(ing) horizontally”, “horizontally-extending” and the like with respect to a field effect transistor are with reference to orientation of the transistor's channel length along which current flows in operation between the source/drain regions. For bipolar junction transistors, “extend(ing) elevationally” “elevationally-extending”, “extend(ing) horizontally”, “horizontally-extending” and the like, are with reference to orientation of the base length along which current flows in operation between the emitter and collector. In some embodiments, any component, feature, and/or region that extends elevationally extends vertically or within 10° of vertical.
Further, “directly above”, “directly below”, and “directly under” require at least some lateral overlap (i.e., horizontally) of two stated regions/materials/components relative one another. Also, use of “above” not preceded by “directly” only requires that some portion of the stated region/material/component that is above the other be elevationally outward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components). Analogously, use of “below” and “under” not preceded by “directly” only requires that some portion of the stated region/material/component that is below/under the other be elevationally inward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components).
Any of the materials, regions, and structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. Where one or more example composition(s) is/are provided for any material, that material may comprise, consist essentially of, or consist of such one or more composition(s). Further, unless otherwise stated, each material may be formed using any suitable existing or future-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples.
Additionally, “thickness” by itself (no preceding directional adjective) is defined as the mean straight-line distance through a given material or region perpendicularly from a closest surface of an immediately-adjacent material of different composition or of an immediately-adjacent region. Additionally, the various materials or regions described herein may be of substantially constant thickness or of variable thicknesses. If of variable thickness, thickness refers to average thickness unless otherwise indicated, and such material or region will have some minimum thickness and some maximum thickness due to the thickness being variable. As used herein, “different composition” only requires those portions of two stated materials or regions that may be directly against one another to be chemically and/or physically different, for example if such materials or regions are not homogenous. If the two stated materials or regions are not directly against one another, “different composition” only requires that those portions of the two stated materials or regions that are closest to one another be chemically and/or physically different if such materials or regions are not homogenous. In this document, a material, region, or structure is “directly against” another when there is at least some physical touching contact of the stated materials, regions, or structures relative one another. In contrast, “over”, “on”, “adjacent”, “along”, and “against” not preceded by “directly” encompass “directly against” as well as construction where intervening material(s), region(s), or structure(s) result(s) in no physical touching contact of the stated materials, regions, or structures relative one another.
Herein, regions-materials-components are “electrically coupled” relative one another if in normal operation electric current is capable of continuously flowing from one to the other and does so predominately by movement of subatomic positive and/or negative charges when such are sufficiently generated. Another electronic component may be between and electrically coupled to the regions-materials-components. In contrast, when regions-materials-components are referred to as being “directly electrically coupled”, no intervening electronic component (e.g., no diode, transistor, resistor, transducer, switch, fuse, etc.) is between the directly electrically coupled regions-materials-components.
Any use of “row” and “column” in this document is for convenience in distinguishing one series or orientation of features from another series or orientation of features and along which components have been or may be formed. “Row” and “column” are used synonymously with respect to any series of regions, components, and/or features independent of function. Regardless, the rows may be straight and/or curved and/or parallel and/or not parallel relative one another, as may be the columns. Further, the rows and columns may intersect relative one another at 90° or at one or more other angles (i.e., other than the straight angle).
The composition of any of the conductive/conductor/conducting materials herein may be metal material and/or conductively-doped semiconductive/semiconductor/semiconducting material. “Metal material” is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compound(s).
Herein, any use of “selective” as to etch, etching, removing, removal, depositing, forming, and/or formation is such an act of one stated material relative to another stated material(s) so acted upon at a rate of at least 2:1 by volume. Further, any use of selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material relative to another stated material or materials at a rate of at least 2:1 by volume for at least the first 75 Angstroms of depositing, growing, or forming.
Unless otherwise indicated, use of “or” herein encompasses either and both.
In some embodiments, a recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator extends along sidewalls and around a bottom of the conductive gate between the conductive gate and the semiconductor material. A pair of source/drain regions are in upper portions of the semiconductor material on opposing lateral sides of the trench. A channel region in the semiconductor material below the pair of source/drain regions extends along sidewalls and around a bottom of the trench. The gate insulator comprises a low-k material and a high-k material. The low-k material is characterized by its dielectric constant k being no greater than 4.0. The high-k material is both (a) and (b), where:
In some embodiments, a recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator extends along sidewalls and around a bottom of the conductive gate between the conductive gate and the semiconductor material. A pair of source/drain regions are in upper portions of the semiconductor material on opposing lateral sides of the trench. A channel region in the semiconductor material below the pair of source/drain regions extends along sidewalls and around a bottom of the trench. The gate insulator comprises a high-k material. The high-k material is all of (a), (b), and (c), where:
In some embodiments, a method of forming a recessed access device comprises forming a trench in semiconductor material. Silicon-containing low-k gate-insulator material is formed over sidewalls and a bottom of the trench. The silicon-containing low-k gate-insulator material is characterized by its dielectric constant k being no greater than 4.0. A lining is formed in the trench laterally-inward of the low-k gate-insulator material. The lining comprises at least one of elemental-form M, alloy-form M, and a metal oxide where M or the metal of the metal oxide is one or more of Al, metal(s) from Group 2, Group 3, Group 4, Group 5, and the lanthanide series of the periodic table. Material of the lining is reacted with the low-k gate-insulator material to form high-k gate-insulator material comprising SixMyO, where “x” is 0.999 to 0.6 and “y” is 0.001 to 0.4. The high-k gate-insulator material is characterized by its dielectric constant k being greater than 4.0. A conductive gate is formed in the trench over sidewalls of the high-k gate-insulator material. A pair of source/drain regions are formed in upper portions of the semiconductor material on opposing lateral sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions and extends along the trench sidewalls and around the trench bottom.
In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.
