The present invention relates generally to integrated circuits and, more particularly, to resistive memory devices.
Resistive based memory devices (ReRAMs), such as magnetic random access memory (MRAM), phase changeable random access memory (PRAM), resistance random access memory (RRAM), etc. can store data by programming the resistance of cells included therein. For example, an MRAM can store a logical data value of “zero” by programming a data cell to have a relatively low resistance or can store a logical data value of “one” by programming the data cell to have a relatively high resistance as shown in
As further shown in
When the data is read from the data cell, the programmed value can be determined by essentially comparing the programmed resistance to a reference resistance. The programmed resistance and reference resistance can actually be provided by respective currents (i.e., currents that correspond to the logical data value stored in the cell as well as the reference). Accordingly, when the data cell is read, circuitry in the MRAM can determine the level of resistance provided by the data cell being read, based on the current, to output the logical data value stored therein. MRAMs are further discussed in, for example, Durlam et al. “A low power 1 Mbit MRAM based on 1T1MTJ bit cell integrated with Copper Interconnects” 2002 Symposium on VLSI Circuits Digest of Technical Papers 158-161 (2002).
MRAMs are also discussed in, for example, Debrosse et al. “A High-Speed 128-kb MRAM Core for Future Universal Memory Applications” IEEE Journal of Solid-State Circuits 39(4):678-683 (2004).
One conventional way of determining the logical data values stored in an MRAM is discussed, for example, in U.S. Pat. No. 6,982,908 to Cho. The approach discussed in Cho uses reference cells that are programmed to store both a logical data value of zero and a logical data value of one. These reference cells are placed in parallel with one another so that a current provided by the combination (i.e., the reference current) should ideally have a value that is the midpoint between a current corresponding to a logical data value of one and a current corresponding to a logical data value of zero, as shown, for example, in
One of the drawbacks associated with this type of approach is that the actual current generated by reading the data cell (and the reference cell) can vary based on a bias voltage provided thereto, as shown in
According to
Embodiments according to the invention can provide resistive memory devices including selected reference memory cells. Pursuant to these embodiments, a Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element could be termed a second element without departing from the teachings of the present invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As described hereinbelow in greater detail, embodiments according to the invention can provide for at least three ReRAM reference cells coupled in parallel with one another and configured to provide a reference current to respective ReRAM sense amplifier circuits. For example, circuits according to some embodiments of the invention can provide a relatively large number of reference cells where half are programmed with a logical data value of zero and half are programmed with a logical data value of one so that the parallel combination can provide a reference current that approximates a midpoint between reference currents associated with the logical data values of zero. Furthermore, the reference current may be less subject to process variation as the greater number of reference cells may provide a more accurate representation of a true midpoint between the data values.
In some embodiments according to the invention, when a read operation is performed to a first block of memory, reference cells in a second block of memory are used to provide a reference current to the sense amplifier used to read the data from the first block of memory. In still other embodiments according to the invention, either of the inputs of the sense amplifier circuits can be used to provide the reference current. In particular, the inputs of the sense amplifier circuits may be coupled to reference block select transistors that are configured to couple together the inputs of the sense amplifier circuits that are to be provided with the reference current.
Furthermore, the input of the sense amplifier circuit that is to be coupled to the other inputs can be responsive to the block of memory to which the read operation is directed. Accordingly, a read to a first block of memory can result in data being provided to a first set of inputs of the sense amplifier circuits whereas the remaining inputs of the sense amplifier circuits are coupled to reference cells in a second block of memory.
In still other embodiments according to the invention, reference cells from different blocks can be coupled together in response to a read operation to a memory block that is outside those blocks that are coupled together. In other words, a read to a particular block of memory can result in reference cells from blocks other than that to which the read is directed being coupled together.
In still further embodiments according to the invention, a current reference circuit can include a number of reference cells that are configured to provide respective reference currents upon activation to a sense amplifier. The amounts of current provided by the reference cells can have an unequally weighted distribution of resistance values. In other words, in some embodiments according to the invention, the number of reference cells used to store logical data values of one may be unequal to the number of reference cells used to store a data value of zero. Accordingly, the reference circuit may be configured to compensate for a particular distribution of values provided by data cells that may be caused by particular process parameters.
In still other embodiments according to the invention, the current reference circuit may be configured so that all the reference cells store equal data values to provide substantially equal reference currents to the sense amplifier circuits coupled thereto.
It will be understood that the data cells MC are configured to store logical data values based on resistive properties, such as those provided in magnetic random access memories, phase changeable random access memories, etc. Accordingly, logical data values, such as one and zero, can be stored in the data cells MC as different resistances so that upon a read operation the logical data values can be determined based on the current which flows to/from the data cells MC when the proper biasing is applied to the wordlines and bitlines coupled thereto.
It will be further understood that although the discussion herein discusses the storage and retrieval of single bit data in/from the data cells MC, the data cells may actually represent multi-bit storage cells. In a multi-bit arrangement, at least two bits of data are stored per memory cell. For example, in a 2-bit memory cell configuration, the status of information stored in each memory cell maybe “00”, “01”, “10” or “11”. Furthermore, each memory cell may be programmed to have a threshold voltage determined as one of four different values. Accordingly, such a multi-bit memory device can store two bits in the same area as a one-bit memory device while using the number of memory cells corresponding to half the number of memory cells required in the one-bit memory device for that amount of information. Therefore, the chip size is correspondingly reduced for storage of a given amount of information, as compared to the one-bit memory device. As the number of bits stored per memory cell increases, the capacity of the multi-bit memory device increases correspondingly as compared to that of the one-bit memory device. Multi-bit storage cells are described further in, for example, U.S. Pat. No. 6,118,696, entitled Multi-bit memory cell array of a non-volatile semiconductor memory device and method for driving the same, the entirety of which is incorporate herein by reference.
As further shown in
As further shown in
In operation, a row of data cells MC in the memory block MCB can be accessed by biasing the appropriate combination of wordlines MWL1-m and bitlines MLB1-n. For example, to access the first row of data cells MC in the memory block MCB, the wordline MWL1 can be activated and a bias voltage applied to each of the bitlines MBL1-n to access the logical data values stored in the first row of data cells MC. Accordingly, currents IM1-n can be provided responsive to activation of the appropriate row of data cells MC during a read operation. Each of the currents IM1-n provided in response to the read can be proportional to the resistance provided by the respective data cell MC to which the input is connected during the read operation.
During the read operation, the reference current circuit RCB can be activated by biasing of the reference word line RWL and the reference bit lines RBL1-n to provide substantially equal reference currents Iref sourced from each of the respective inputs to the sense amplifier circuits SU1-n, The reference currents Iref are divided among the at least three reference cells coupled in parallel with one another, which are shown in
In response, each of the sense amplifier circuits SU1-SUn compares the voltage levels provided to the inputs of the sense amplifier SA1-n that are proportional to the reference current and the current IM1-n that is sourced by the respective sense amplifier circuit SU1-n. In particular, each input of the sense amplifiers SA1-SAn is coupled to respective constant current sources IS1 and IS2 that can be accessed through operation of a pair of control transistors TC1 and TC2 that operate responsive to an output of a pair of comparators CMP1 and CMP2. The comparators CMP1 and CMP2 each compare the voltage developed by the respective current Iref and IM1-n to a bias voltage Vb to provide operation of the control transistors TC1 and TC2.
The comparators CMP1 and CMP2 compare the voltage at the input (either the input coupled to the reference cells or the input connected to the data cells) to the bias voltage Vb and if the input voltage is less than the bias voltage Vb, the output of the comparitor increases so that a drain current in the control transistor TC1 or TC2 supplied by the constant current source IS1 or IS2 is increased thereby raising the voltage level presented at the input. If, on the other hand, the voltage developed at the input from the data cells MC is greater than the bias voltage Vb, the output of the comparator CMP1 or CMP2 decreases so that the drain current of the control transistor TC1 or TC2 decreases to reduce the voltage present at the input of the sense amplifier circuit SU1-n. It will be understood that although the operation of the circuits included in the sense amplifier circuit SU1-SUn are described above with reference to inputs coupled to the data cells MC, the operations of the circuits coupled to the reference cells can be analogous.
According to
Because an increased number of reference cells RC1-n can be provided in the reference current circuit RCB, the distribution range of the current Iref can be narrower, thereby enabling an improvement in the operating margin of the sense amplifier circuits SU1-n, which may further allow a more accurate determination of the data that is stored in the data cells MC.
As further shown in
As further shown in
In operation, as discussed above in reference to
It will be understood that the control signal ØR1 designates a read to the first half block HBK1 so that the remaining inputs to the sense amplifier circuits SU-SUn are coupled to reference cells in the second half block at HBK2. In particular, the reference wordline provided by the second row decoder 13B along with the bitlines BSL1-n (for both MBLK1 and MBLKi in HBK2) are used to activate the reference cells included therein. Accordingly,
In operation, the sense amplifier circuits included in the sense amplifier block SAB can be provided with data from the data cells from one of the half blocks HBK1′/HBK2′ while being coupled to reference cells included in the other half block HBK1′/HBK2′, which is illustrated in equivalent simplified
Moreover, as shown above in reference to
As described herein, embodiments according to the invention can provide for at least three ReRAM reference cells coupled in parallel with one another and configured to provide a reference current to respective ReRAM sense amplifier circuits. For example, circuits according to some embodiments of the invention can provide a relatively large number of reference cells where half are programmed with a logical data value of zero and half are programmed with a logical data value of one so that the parallel combination can provide a reference current that approximates a midpoint between reference currents associated with the logical data values of zero. Furthermore, the reference current may be less subject to process variation as the greater number of reference cells may provide a more accurate representation of a true midpoint between the data values.
In some embodiments according to the invention, when a read operation is performed to a first block of memory, reference cells in a second block of memory are used to provide a reference current to the sense amplifier used to read the data from the first block of memory. In still other embodiments according to the invention, either of the inputs of the sense amplifier circuits can be used to provide the reference current. In particular, the inputs of the sense amplifier circuits may be coupled to reference block select transistors that are configured to couple together the inputs of the sense amplifier circuits that are to be provided with the reference current.
Furthermore, the input of the sense amplifier circuit that is to be coupled to the other inputs can be responsive to the block of memory to which the read operation is directed. Accordingly, a read to a first block of memory can result in data being provided to a first set of inputs of the sense amplifier circuits whereas the remaining inputs of the sense amplifier circuits are coupled to reference cells in a second block of memory.
In still other embodiments according to the invention, reference cells from different blocks can be coupled together in response to a read operation to a memory block that is outside those blocks that are coupled together. In other words, a read to a particular block of memory can result in reference cells from blocks other than that to which the read is directed being coupled together.
In still further embodiments according to the invention, a current reference circuit can include a number of reference cells that are configured to provide respective reference currents upon activation to a sense amplifier. The amounts of current provided by the reference cells can have an unequally weighted distribution of resistance values. In other words, in some embodiments according to the invention, the number of reference cells used to store logical data values of one may be unequal to the number of reference cells used to store a data value of zero. Accordingly, the reference circuit may be configured to compensate for a particular distribution of values provided by data cells that may be caused by particular process parameters.
In still other embodiments according to the invention, the current reference circuit may be configured so that all the reference cells store equal data values to provide substantially equal reference currents to the sense amplifier circuits coupled thereto.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.
Number | Date | Country | Kind |
---|---|---|---|
2005-0124033 | Dec 2005 | KR | national |
The present application is a Divisional Application of U.S. patent application Ser. No. 12/358,936, filed in the United States Patent Office on Jan. 23, 2009, now U.S. Pat. No. 8,023,311 which is a Divisional Application of U.S. patent application Ser. No. 11/527,271, filed in the United States Patent Office on Sep. 26, 2006, now U.S. Pat. No. 7,495,984 and claims priority to Korean Patent Application No. 2005-0124033, filed in the Korean Intellectual Property Office on Dec. 15, 2005, the disclosures of which are incorporated herein by reference.
Number | Name | Date | Kind |
---|---|---|---|
5432731 | Kirsch et al. | Jul 1995 | A |
5753946 | Naiki et al. | May 1998 | A |
5999439 | Seyyedy | Dec 1999 | A |
6246622 | Sugibayashi | Jun 2001 | B1 |
6269040 | Reohr et al. | Jul 2001 | B1 |
6317375 | Perner | Nov 2001 | B1 |
6317376 | Tran et al. | Nov 2001 | B1 |
6426907 | Hoenigschmid | Jul 2002 | B1 |
6490217 | DeBrosse et al. | Dec 2002 | B1 |
6504751 | Poechmueller | Jan 2003 | B2 |
6678189 | Tran | Jan 2004 | B2 |
6714443 | Ooishi | Mar 2004 | B2 |
6738285 | Tanizaki et al. | May 2004 | B2 |
6757191 | Ooishi et al. | Jun 2004 | B2 |
6778426 | Hosotani | Aug 2004 | B2 |
6795340 | Sakimura et al. | Sep 2004 | B2 |
6826079 | Tran | Nov 2004 | B2 |
6839269 | Iwata et al. | Jan 2005 | B2 |
6856537 | Tanizaki et al. | Feb 2005 | B2 |
6870759 | Tsang | Mar 2005 | B2 |
6876575 | Hidaka | Apr 2005 | B2 |
6982908 | Cho | Jan 2006 | B2 |
6990015 | Honda et al. | Jan 2006 | B2 |
7027342 | Inoue | Apr 2006 | B2 |
7072207 | Ooishi | Jul 2006 | B2 |
7116595 | Hidaka | Oct 2006 | B2 |
7116598 | Shimizu et al. | Oct 2006 | B2 |
7233537 | Tanizaki et al. | Jun 2007 | B2 |
7272064 | Ooishi | Sep 2007 | B2 |
7286378 | Nazarian | Oct 2007 | B2 |
7313043 | Gogl et al. | Dec 2007 | B2 |
8189363 | Tsuchida et al. | May 2012 | B2 |
20030235071 | Okazawa | Dec 2003 | A1 |
20040233709 | Tsuchida et al. | Nov 2004 | A1 |
20050036376 | Iwata et al. | Feb 2005 | A1 |
20050105329 | Nazarian | May 2005 | A1 |
20050128793 | Ho et al. | Jun 2005 | A1 |
20060062066 | Garni | Mar 2006 | A1 |
20090323405 | Jung et al. | Dec 2009 | A1 |
20100046274 | Tsuchida et al. | Feb 2010 | A1 |
20100054020 | Ueda | Mar 2010 | A1 |
20100195415 | Seko | Aug 2010 | A1 |
20100271861 | Kitagawa | Oct 2010 | A1 |
20110080775 | Bae et al. | Apr 2011 | A1 |
20110310661 | Taylor et al. | Dec 2011 | A1 |
20120087183 | Chang | Apr 2012 | A1 |
Number | Date | Country |
---|---|---|
103 04 453 | Aug 2003 | DE |
02-110895 | Apr 1990 | JP |
09097496 | Apr 1997 | JP |
2002-140888 | May 2002 | JP |
2002-343077 | Nov 2002 | JP |
2003-196973 | Jul 2003 | JP |
2003-257175 | Sep 2003 | JP |
2003-257177 | Sep 2003 | JP |
2003-288779 | Oct 2003 | JP |
2003-297072 | Oct 2003 | JP |
2004-005797 | Jan 2004 | JP |
2004-23062 | Jan 2004 | JP |
2005-018916 | Jan 2005 | JP |
10-2002-0003296 | Jan 2002 | KR |
10-0449067 | Jan 2002 | KR |
10-2003-0097697 | Dec 2003 | KR |
10-2005-0004160 | Jan 2005 | KR |
Number | Date | Country | |
---|---|---|---|
20110310657 A1 | Dec 2011 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 12358936 | Jan 2009 | US |
Child | 13219582 | US | |
Parent | 11527271 | Sep 2006 | US |
Child | 12358936 | US |