BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a graphical depiction of different resistance levels provided by cells storing logical data values of zero or logical data values of one.
FIG. 2 is a circuit of a conventional MRAM including two reference cells.
FIG. 3 is a graph that illustrates variation in resistances associated with reference cells as a function of voltage biasing provided thereto.
FIG. 4 is a circuit schematic of a conventional sense amplifier circuit used to compare currents provided by data cells and reference cells.
FIG. 5 is a graphical illustration of currents provided by data cells storing logical data values of one and zero as well as reference currents provided by reference cells that are approximately midway between the current levels provided by the data cells.
FIG. 6 is a circuit schematic that illustrates sense amplifier circuits coupled to data cells and current reference cells according to some embodiments of the invention.
FIG. 7 is a simplified equivalent circuit that represents sense amplifier circuits coupled to reference cells/data cells using access transistors according to some embodiments of the invention.
FIG. 8 is an equivalent circuit showing a “crosspoint” configuration where the resistive elements represent the data cells and reference cells according to some embodiments of the invention.
FIG. 9 is a schematic representation of a sense amplifier circuit selectively coupled to reference cells in different memory blocks according to some embodiments of the invention.
FIG. 10 is a simplified schematic illustration of sense amplifier circuits including control transistors coupled to inputs thereof according to some embodiments of the invention.
FIG. 11 is a schematic illustration of memory blocks including data cells and reference cells according to some embodiments of the invention.
FIG. 12 is a simplified equivalent circuit of memory blocks including data cells and reference cells shown in FIG. 11 according to some embodiments of the invention.
FIG. 13 is a schematic illustration of a resistive random access memory device wherein the data cells and reference cells are shown in a “crosspoint” configuration according to some embodiments of the invention.
FIG. 14 is a simplified equivalent circuit showing the sense amplifier circuits SA0-15 in FIG. 13 according to some embodiments of the invention.
FIG. 15 is a schematic illustration of memory blocks 0-7 and memory blocks 8-15 coupled to inputs of sense amplifier circuits SA0-7 according to some embodiments of the invention.
FIG. 16 is a simplified equivalent circuit of memory blocks 0-7 and memory blocks 8-15 coupled to inputs of sense amplifier circuits SA0-7 shown in FIG. 16.
FIG. 17 is a schematic illustration of variations in the range of distribution of currents associated with logical data values stored in data cells/reference cells.
FIG. 18 is a schematic illustration that shows a relatively narrow distribution range for currents generated by data cells storing a logical data value of one and the current generated by memory cells storing logical data values of zero can occur over a relatively wide range.
FIG. 19 is a schematic illustration of a reference current circuit RCB′ including three reference cells RS1-RS3 coupled to four sense amplifier circuits SU1-4 each providing a reference current Iref′ to the reference current circuit RCB′ according to some embodiments of the invention.
FIG. 20 is a schematic that illustrates reference cells coupled to sense amplifier circuits SU1-SU4 in some embodiments according to the invention.