Resistive memory devices including selected reference memory cells

Abstract

A Resistance based Random Access Memory (ReRAM) can include a current reference circuit including at least three ReRAM reference cells coupled in parallel with one another and configured to provide a reference current to respective ReRAM sense amplifier circuits.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a graphical depiction of different resistance levels provided by cells storing logical data values of zero or logical data values of one.

FIG. 2 is a circuit of a conventional MRAM including two reference cells.

FIG. 3 is a graph that illustrates variation in resistances associated with reference cells as a function of voltage biasing provided thereto.

FIG. 4 is a circuit schematic of a conventional sense amplifier circuit used to compare currents provided by data cells and reference cells.

FIG. 5 is a graphical illustration of currents provided by data cells storing logical data values of one and zero as well as reference currents provided by reference cells that are approximately midway between the current levels provided by the data cells.

FIG. 6 is a circuit schematic that illustrates sense amplifier circuits coupled to data cells and current reference cells according to some embodiments of the invention.

FIG. 7 is a simplified equivalent circuit that represents sense amplifier circuits coupled to reference cells/data cells using access transistors according to some embodiments of the invention.

FIG. 8 is an equivalent circuit showing a “crosspoint” configuration where the resistive elements represent the data cells and reference cells according to some embodiments of the invention.

FIG. 9 is a schematic representation of a sense amplifier circuit selectively coupled to reference cells in different memory blocks according to some embodiments of the invention.

FIG. 10 is a simplified schematic illustration of sense amplifier circuits including control transistors coupled to inputs thereof according to some embodiments of the invention.

FIG. 11 is a schematic illustration of memory blocks including data cells and reference cells according to some embodiments of the invention.

FIG. 12 is a simplified equivalent circuit of memory blocks including data cells and reference cells shown in FIG. 11 according to some embodiments of the invention.

FIG. 13 is a schematic illustration of a resistive random access memory device wherein the data cells and reference cells are shown in a “crosspoint” configuration according to some embodiments of the invention.

FIG. 14 is a simplified equivalent circuit showing the sense amplifier circuits SA0-15 in FIG. 13 according to some embodiments of the invention.

FIG. 15 is a schematic illustration of memory blocks 0-7 and memory blocks 8-15 coupled to inputs of sense amplifier circuits SA0-7 according to some embodiments of the invention.

FIG. 16 is a simplified equivalent circuit of memory blocks 0-7 and memory blocks 8-15 coupled to inputs of sense amplifier circuits SA0-7 shown in FIG. 16.

FIG. 17 is a schematic illustration of variations in the range of distribution of currents associated with logical data values stored in data cells/reference cells.

FIG. 18 is a schematic illustration that shows a relatively narrow distribution range for currents generated by data cells storing a logical data value of one and the current generated by memory cells storing logical data values of zero can occur over a relatively wide range.

FIG. 19 is a schematic illustration of a reference current circuit RCB′ including three reference cells RS1-RS3 coupled to four sense amplifier circuits SU1-4 each providing a reference current I_ref′ to the reference current circuit RCB′ according to some embodiments of the invention.

FIG. 20 is a schematic that illustrates reference cells coupled to sense amplifier circuits SU1-SU4 in some embodiments according to the invention.

Claims

1. A Resistance based Random Access Memory (ReRAM) comprising: a current reference circuit including at least three ReRAM reference cells coupled in parallel with one another and configured to provide a reference current to respective ReRAM sense amplifier circuits.

2. A ReRAM according to claim 1 further comprising: at least three bit lines, each coupled to a respective one of the reference cells, the at least three bit lines configured to be activated during a read operation in the ReRAM.

3. A ReRAM according to claim 1 further comprising: a word line coupled to the at least three reference cells, and configured to be activated during a read operation in the ReRAM.

4. A ReRAM according to claim 1 further comprising: at least three bit lines, each coupled to one of the reference cells, the at least three bit lines configured to be activated during a read operation in the ReRAM;at least three access transistors, each coupled to one of the reference cells; anda reference word line coupled to gates of the access transistors and configured to be activated during the read operation.

5. A ReRAM according to claim 1 further comprising: at least three bit lines, each coupled to one of the reference cells, the at least three bit lines configured to be activated during a read operation in the ReRAM; anda reference word line coupled to each of the reference cells and configured to be activated during the read operation.

6. A ReRAM according to claim 1 further comprising: a sense amplifier circuit including first and second inputs, wherein the first input is coupled to a bit line of a data cell in the ReRAM and the second input is coupled to the current reference circuit.

7. A ReRAM according to claim 6 wherein the reference current flows from the second input to the at least reference cells.

8. A ReRAM according to claim 7 further comprising: first and second control transistors coupled inline with the bit line of the data cell and the first input and coupled inline with the reference cells and the second input, respectively; andfirst and second comparator circuits coupled to gates of the first and second control transistors, wherein the first and second comparator circuits are configured to increase/decrease voltage levels at the gates of the first and second control transistors to drive voltages at the first or second inputs to a bias voltage level.

9. A ReRAM according to claim 1 wherein the ReRAM comprises a PRAM or an MRAM.

10. A ReRAM according to claim 1 wherein each ReRAM reference cell is configured to provide a respective resistance value representative of a data value stored in the ReRAM.

11. A ReRAM according to claim 1 wherein the ReRAM further comprises ReRAM data cells configured to store multi-bit data.

12. A ReRAM according to claim 1 further comprising: a sense amplifier circuit including first and second inputs, wherein the first input is coupled to a first bit line of a data/reference cell in the ReRAM and the second input is coupled to a second bit line of a data/reference cell.

13. A ReRAM according to claim 12 wherein the sense amplifier circuit comprises a first sense amplifier circuit, the ReRAM further comprising: a second sense amplifier circuit including first and second inputs; anda reference block select transistor coupled between the first input of the first sense amplifier circuit and the first input of the second sense amplifier circuit, wherein the reference block select transistor is configured to coupled the first inputs of the first and second sense amplifier circuits to the reference cells responsive to a read operation to a block of the ReRAM other than a block including the reference cells.

14. A ReRAM according to claim 1 further comprising: a plurality of sense amplifier circuits each have first inputs coupled to a plurality of control transistors, the control transistors configured to couple the first inputs to reference cells in a block of the ReRAM other than a block to which a read operation is performed.

15. A ReRAM according to claim 1 further comprising: a plurality of sense amplifier circuits each have first inputs coupled to a plurality of control transistors, the control transistors configured to couple the first inputs to reference cells in different blocks of the ReRAM other than a block to which a read operation is performed.

16. A Resistance based Random Access Memory (ReRAM) comprising: a sense amplifier circuit including a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.

17. A ReRAM according to claim 16 further comprising: a second input of the sense amplifier circuit coupled to a reference cell in the second block responsive to a read operation to a first block.

18. A ReRAM according to claim 17 wherein the first and second blocks comprise arrays of data cells each coupled to a respective bit line and to a respective word line of the ReRAM.

19. A ReRAM according to claim 17 wherein the first and second blocks comprise arrays of data cells each coupled to respective bit lines and to respective access transistors, wherein the access transistors are coupled to respective data cells.

20. A ReRAM according to claim 19 wherein each of the data cells is configured for access responsive to activation of a respective access transistor using a respective word line and activation of a respective bit line couple to the respective access transistor.

21. A ReRAM according to claim 18 wherein each of the data cells is configured for access responsive to activation of a respective word line coupled to the respective access transistor and activation of a respective bit line coupled to the respective access transistor.

22. A ReRAM according to claim 17 wherein the sense amplifier circuit comprises a first sense amplifier circuit, the ReRAM further comprising: a second sense amplifier circuit including first and second inputs; anda reference block select transistor coupled between the first input of the first sense amplifier circuit and the first input of the second sense amplifier circuit, wherein the reference block select transistor is configured to coupled the first inputs of the first and second sense amplifier circuits to the reference cells responsive to a read operation to a block of the ReRAM other than a block including the reference cells.

23. A Resistance based Random Access Memory (ReRAM) comprising: a plurality of sense amplifier circuits configured to receive data from data cells from a plurality of different blocks in the ReRAM and to receive reference voltages from reference cells from the different blocks; anda plurality of reference block select transistors coupled to inputs of the plurality of the sense amplifier circuits and configured to couple the inputs to reference cells included in the plurality of different blocks responsive to a read operation to a block of the ReRAM other than the remaining ones.

24. A Resistance based Random Access Memory (ReRAM) comprising: a current reference circuit including reference cells configured to provide respective reference currents upon activation to sense amplifier circuits coupled thereto in amounts provided by an unequally weighted distribution of resistance values among the reference cells.

25. A ReRAM according to claim 24 wherein the resistance values are weighted toward a resistance value having a narrower range of values among data cells in the ReRAM.

26. A ReRAM according claim 24 wherein the ReRAM comprises a PRAM or an OxRAM, or a polymer RAM.

27. A ReRAM according to claim 24 wherein the unequally weighted distribution of resistance values is based only on one of the resistance values used to store data in the ReRAM.

28. A ReRAM according to claim 27 wherein the only one of the resistance values comprises the resistance value having a narrower range of values.

29. A ReRAM according to claim 24 wherein the current reference circuit comprises: a number of first reference cells configured to store a first resistance value; anda second number of second cells configured to store a second resistance value, wherein the first and second numbers are unequal.

30. A ReRAM according to claim 29 wherein the number of first reference cells is greater than the number of second reference cells if the range of the first resistance values is narrower than the range of the second resistance values.

31. A Resistance based Random Access Memory (ReRAM) comprising: a current reference circuit including reference cells all configured to store equal data values to provide respective substantially equal reference currents.

32. A ReRAM according to claim 31 wherein the equal data values correspond to a resistance value having-a narrower range of values in the ReRAM.

33. A ReRAM according to claim 32 wherein the resistance value comprises a relatively low resistance.

34. A ReRAM according to claim 32 wherein the resistance value comprises a relatively high resistance.

35. A ReRAM according to claim 31 further comprising: a single reference word line coupled to each of the reference cells and configured to activate the reference cells to provide the reference currents responsive to a read operation in the ReRAM; andseparate bit lines for each of the reference cells.

36. A ReRAM according to claim 31, wherein the current reference circuit comprises a first current reference circuit including first reference cells, the ReRAM further comprising: a second current reference circuit, coupled in parallel with the first current reference circuit, the second current reference circuit including second reference cells all configured to store equal data values to provide respective substantially equal reference currents, wherein the equal data values stored in the first and second current reference circuit are substantially equal.

37. A ReRAM according to claim 36 further comprising: first and second reference word lines coupled to the first and second current reference circuits respectively and configured to activate the reference circuits to provide the reference currents responsive to a read operation in the ReRAM.