Patent Application
20210013405
The disclosed embodiments relate generally to resistive switching nonvolatile random access memory (ReRAM) devices, and more particularly, to structures and methods of forming multiple conductive elements in ReRAM devices.
Nonvolatile memory elements are used in systems when “persistent” storage is required. For example, nonvolatile memory elements are used to persistently store data in computer environments. Digital cameras use nonvolatile memory elements to store image data and digital music players use nonvolatile memory elements to store audio data. Nonvolatile memory is often formed using electrically-erasable programmable read only memory (EEPROM) technology. An EEPROM device typically includes floating gate transistors that can be programmed or erased by application of program and erase voltages, respectively.
As device dimensions shrink, it becomes more challenging to fabricate traditional nonvolatile memory devices due to scaling issues. This has led to the investigation of alternative memory technologies, including ReRAM devices.
A ReRAM device uses reversible resistance switching between two different resistance states, a low resistance state and a high resistance state. The device is switched between the two different resistance states through the application of suitable switching voltages. The applied voltage causes the formation and breaking of conducting filaments across an insulating metal-oxide based dielectric layer that results in the low and high resistance states, respectively.
Over time, it becomes increasingly more difficult to switch the device from a high resistance state to a low resistance state or from a low resistance state to a high resistance state, i.e., set or reset, respectively. The number of repeated set and reset cycles that the device is able to reliably undergo determines the device lifetime. Naturally, it is desirable for the device to be able to undergo a large number of set and reset cycles.
In addition, a large variability is observed in the voltages required to switch the device for the set and reset voltages, respectively. A tight distribution in the set and reset voltages or switching voltages is desirable.
Hence, there is a need for a ReRAM structure that can meet the design criteria for advanced memory devices.
To achieve the foregoing and other aspects of the present disclosure, structures and a method of fabricating resistive memory devices with multiple conductive elements are presented.
According to an aspect of this disclosure, a resistive memory device is provided, which includes a first electrode having a first work function and a second electrode having a second work function, wherein the first work function is different from the second work function. A dielectric layer is disposed between the first and second electrodes. A set of nanocrystal structures is distributed in the dielectric layer and a conductive layer is disposed in the dielectric layer.
According to another aspect of this disclosure, a resistive memory device is provided, which includes a first electrode and a second electrode. A dielectric layer is disposed between the first and second electrodes. At least one set of nanocrystal structures is horizontally distributed in the dielectric layer. A conductive layer is horizontally disposed in the dielectric layer.
In yet another aspect of this disclosure, a method of fabricating a resistive memory device is provided, which includes depositing a layer of metal having a first work function to form a first electrode. A first dielectric layer is deposited on the first electrode. A first conductive layer is formed on the dielectric layer. A second dielectric layer is deposited on the first conductive layer. A second conductive layer is formed on the second dielectric layer. A third dielectric layer is deposited on the second conductive layer. A layer of metal having a second work function is deposited over the third dielectric layer to form a second electrode, wherein the first work function is different from the second work function.
Numerous advantages may be derived from the embodiments described below wherein a resistive memory device includes a set of nanocrystal structures distributed in a dielectric layer and a conductive layer disposed in the dielectric layer. The nanocrystal structures lead to a tighter distribution in set and reset voltages as well as the high and low resistance states. Tighter distributions in switching voltages and resistance states are achieved as the nanocrystal structures lead to conductive filament formation at particular locations in the device.
In an aspect of the present disclosure, the conductive layer may be a metal layer. In another aspect of the present disclosure, the conductive layer may be a set of nanocrystal structures distributed in a dielectric layer. The conductive layer leads to the formation of shorter filaments, hence allowing more control on the filament formation. The added control over the resistive memory device improves the device lifetime.
In a preferred embodiment, the conductive layer may be a set of nanocrystal structures distributed in a dielectric layer due to the advantages mentioned above. In another embodiment, the conductive layer may be a metal layer due to lower cost of fabrication.
The disclosed embodiments will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawings:
For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and certain descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the device. Additionally, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements in the drawings may be exaggerated relative to other elements to help improve understanding of embodiments of the device. The same reference numerals in different drawings denote the same elements, while similar reference numerals may, but do not necessarily, denote similar elements.
The following detailed description is exemplary in nature and is not intended to limit the device or the application and uses of the device. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the device or the following detailed description.
The dielectric layers 116a, 116b and 116c (collectively referred to as dielectric layer 116) are disposed between the first electrode 102 and the second electrode 106. A set of nanocrystal structures 206 is distributed in a dielectric layer 116c. A conductive layer 208 is disposed between the set of nanocrystal structures 206 and the first electrode 102. In a preferred embodiment, the conductive layer 208 may be a metal layer. A dielectric layer 116a is disposed between the conductive layer 208 and the first electrode 102. A dielectric layer 116b is disposed between the set of nanocrystal structures 206 and the conductive layer 208.
In an aspect of the present disclosure, the set of nanocrystal structures 206 is separated from the second electrode 106 by a distance 216 ranging from 3 to 20 nm. In another aspect of the present disclosure, the set of nanocrystal structures 206 has at least three nanocrystals, a first nanocrystal 206a, a second nanocrystal 206b and a third nanocrystal 206c. The first nanocrystal 206a is separated from the second nanocrystal 206b by the dielectric layer 116. The second nanocrystal 206b is separated from the third nanocrystal 206c by the dielectric layer 116. The separation distance 202 between the first nanocrystal 206a and the second nanocrystal 206b may or may not be equal to the separation distance 212 between the second nanocrystal 206b and the third nanocrystal 206c.
In an embodiment of the disclosure, the first nanocrystal 206a, the second nanocrystal 206b and the third nanocrystal 206c are spherical in shape. In another embodiment, the nanocrystal structures 206 are elliptical in shape. The shape of the nanocrystal structures 206 is representative and not intended to be limiting.
The resistive memory device 110 is fabricated by depositing a layer of metal having a first work function to form a first electrode 102. A dielectric layer 116a is subsequently deposited on the first electrode 102. A conductive layer 208 is formed on the dielectric layer 116a by depositing a layer of metal. A dielectric layer 116b is deposited on the conductive layer 208. A set of nanocrystal structures 206 is formed on the dielectric layer 116b. A dielectric layer 116c is deposited on the set of nanocrystal structures 206. Hence, the set of nanocrystal structures 206 is distributed in the dielectric layer 116c. A layer of metal having a second work function is deposited on the dielectric layer 116c to form the second electrode 106.
The set of nanocrystal structures 206 is formed by depositing a layer of metal on the dielectric layer 116b followed by annealing the layer of metal. In an aspect of the disclosure, the dielectric layer 116c is deposited together with the deposition of the layer of metal. In another aspect of the disclosure, the dielectric layer 116c is deposited after the metal deposition. For example, a layer of metal with a thickness in the range of 2 to 5 nm is deposited on the dielectric layer 116b. The deposited layer of metal is annealed at a temperature high enough to melt the metal layer. Hence, the annealing temperature range varies with the type of metal deposited. After annealing, the melted layer of metal join together to form the nanocrystal structures due to strain.
The first electrode 102 and the second electrode 106 of the resistive memory device 110 are connected to peripheral circuitry such as row and column address decoders. The first electrode 102 of the resistive memory device 110 is connected to a drain of an n-channel metal oxide semiconductor (NMOS) access transistor.
The first electrode 102 and the second electrode 106 comprise aluminum, titanium, tungsten, ruthenium, nickel, copper, silver, iridium, platinum, gold and tantalum. The electrodes may be fabricated by physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD).
The set of nanocrystal structures 206 and the conductive layer 208 comprise aluminum, titanium, tungsten, ruthenium, nickel, copper, silver, iridium, platinum, gold, tantalum, cobalt, terbium, dysprosium, holmium and gadolinium. The nanocrystal structures 206 and the conductive layer 208 may be fabricated by PVD, CVD or ALD. Preferred fabrication methods for the nanocrystal structures are by PVD or CVD.
The dielectric layer 116 comprise a binary oxide of magnesium, silicon, aluminum, chromium, manganese, iron, cobalt, zinc, germanium, titanium, nickel, copper, yttrium, zirconium, niobium, molybdenum, tin, lanthanum, hafnium, tantalum, tungsten, cerium, gadolinium, ytterbium and lutetium. For example, the dielectric layer 116 includes aluminum oxide. The dielectric layer 116 may be fabricated by PVD, CVD or ALD.
The resistive memory device 110 as illustrated in
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The resistive memory device 770 is fabricated by depositing a layer of metal having a first work function to form a first electrode 102. A first dielectric layer 116a is deposited on the first electrode 102. A first set of nanocrystal structures 212 is formed on the first dielectric layer 116a. A second dielectric layer 116b is deposited on the first set of nanocrystal structures 212. A second set of nanocrystal structures 206 is formed on the second dielectric layer 116b. A third dielectric layer 116c is deposited on the second set of nanocrystal structures 206. A layer of metal having a second work function is deposited on the third dielectric layer 116c to form a second electrode 106.
In an aspect of the disclosure, having a conductive layer that is a set of nanocrystal structures rather than a metal layer reduces variability in the switching voltages or set and reset voltages as the conductive filament formation occurs only at particular locations in the device. For example, the conductive filaments are formed between the first electrode 102 and the nanocrystals in the first set of nanocrystal structures 212. In addition, conductive filaments are also formed between the nanocrystals in the first set of nanocrystal structures 212 and the second set of nanocrystal structures 206. Furthermore, conductive filaments are formed between the second set of nanocrystal structures 206 and the second electrode 106.
In another aspect of the disclosure, having a conductive layer that is either a set of nanocrystal structures or a metal layer also improves the device lifetime due to formation of shorter filaments.
As shown in
The resistive memory device 990 is fabricated by depositing a layer of metal having a first work function to form a first electrode 102 and depositing a first dielectric layer 116a on the first electrode 102. A first conductive layer 230 may be a first set of nanocrystal structures that is formed on the first dielectric layer 116a. The first set of nanocrystal structures has at least one nanocrystal. The number of nanocrystals in the first set of nanocrystal structures is varied by controlling the amount of metal deposited to form the nanocrystals. A second dielectric layer 116b is deposited on the first conductive layer 230. A second conductive layer 218 may be a second set of nanocrystal structures that is formed on the second dielectric layer 116b. The second set of nanocrystal structures has at least two nanocrystals. A third dielectric layer 116c is deposited on the second conductive layer 218. A third conductive layer 206 may be a third set of nanocrystal structures that is formed on the third dielectric layer 116c. The third set of nanocrystal structures has at least three nanocrystals and in a representative middle layer.
Subsequently, a fourth dielectric layer 116d is deposited on the third conductive layer 206. A fourth conductive layer 212 may be a fourth set of nanocrystal structures that is formed on the fourth dielectric layer 116d. The fourth set of nanocrystal structures has at least two nanocrystals. A fifth dielectric layer 116e is deposited on the fourth conductive layer 212. A fifth conductive layer 224 may be a fifth set of nanocrystal structures that is formed on the fifth dielectric layer 116e. The fifth set of nanocrystal structures has at least one nanocrystal. A sixth dielectric layer 116f is deposited on the fifth conductive layer 224. Finally, a layer of metal having a second work function is deposited on the sixth dielectric layer 116f to form the second electrode 106.
The number of nanocrystals in the first, second, third, fourth and fifth sets of nanocrystal structures is representative and is not supposed to be limiting. As shown, the number of nanocrystals increases with increasing distance from the first electrode 102 within a first section 256 in the dielectric layer 116 up to the middle layer 116d. Thereafter, the number of nanocrystals decreases with increasing distance from the first electrode 102 within a second section 276 in the dielectric layer 116. The first section 256 and the second section 276 have substantially similar thicknesses. In another aspect of the present disclosure, the second, third and fourth conductive layers, 218, 206 and 212, respectively, may alternatively be metal layers (not shown).
Referring to
The terms “first”, “second”, “third”, and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. The terms “left”, “right”, “front”, “back”, “top”, “bottom”, “over”, “under”, and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. Similarly, if a method is described herein as comprising a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. Furthermore, the terms “comprise”, “include”, “have”, and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or device that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or device. Occurrences of the phrase “in one embodiment” herein do not necessarily all refer to the same embodiment.
While several exemplary embodiments have been presented in the above detailed description of the device, it should be appreciated that number of variations exist. It should further be appreciated that the embodiments are only examples, and are not intended to limit the scope, applicability, dimensions, or configuration of the device in any way. Rather, the above detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the device, it being understood that various changes may be made in the function and arrangement of elements and method of fabrication described in an exemplary embodiment without departing from the scope of this disclosure as set forth in the appended claims.
