Patent Application
20090004851
The present invention relates, most generally, to semiconductor devices and methods for forming the same. In particular, the present invention is directed to the selective electroless deposition of metal materials on exposed silicon surfaces.
In advanced semiconductor device processing, metal silicide films are formed on silicon surfaces to improve device speed and contact resistance for contact made to the silicon surface. Contact resistance is lowered when an interconnect material contacts a metal silicide film formed on a silicon surface, in comparison to the interconnect material directly contacting the silicon surface.
According to conventional processing technology, metal silicide layers are formed over exposed silicon surfaces on a semiconductor device by depositing a metal film over the entire surface of a semiconductor substrate, including over exposed silicon sections and over other sections such as dielectric sections. After the metal film is formed over the entire substrate surface, a heating operation is carried out to cause reaction between the deposited metal film and the exposed silicon surfaces in areas where the deposited metal film contacts the silicon surfaces. In other areas, such as where the deposited metal film is disposed over a dielectric, no reaction occurs. After the metal silicide layer is formed by reaction between metal from the metal film and silicon from the silicon surface, the un-reacted portions of the deposited metal layer are then removed. The un-reacted portions of the deposited metal layer can be removed using a selective etching process or other suitable processes. After the unwanted and un-reacted metal is removed, a further heating process is often used to obtain the desired phase of the metal silicide. Nickel, Ni, and Cobalt, Co, are metal materials that are commonly used in this application.
A shortcoming of the aforedescribed conventional processing sequence is that the selective etching process or other process used to remove the un-reacted, deposited metal, generates particle contamination that can result in electrical, yield and device performance degradation. It would be therefore desirable to form suitable metal silicide layers in desired locations without generating contaminating particles.
To address these and other needs, and in view of its purposes, the present invention provides, in one aspect, a method for forming a semiconductor device. The method includes providing a semiconductor substrate with a semiconductor device thereon, the semiconductor device having exposed silicon surfaces and exposed dielectric surfaces. The method further includes positioning the semiconductor substrate in an electroless plating solution that includes at least metal ions therein. The method provides for urging the metal ions to selectively deposit only on the exposed silicon surfaces and not on the dielectric surfaces, thereby forming a metal film on the exposed silicon surfaces.
According to another aspect, the invention provides a method for forming a semiconductor device, the method including providing a semiconductor substrate with a semiconductor device thereon, the semiconductor device having exposed silicon surfaces and exposed dielectric surfaces. The semiconductor substrate is positioned in an electroless plating solution that includes at least metal ions and dopant impurity ions therein. The method provides for urging the metal ions to selectively deposit only on the exposed silicon surfaces and not on the dielectric surfaces, thereby forming a metal film on the exposed metal surfaces. The method further provides for heating to form a metal silicide by causing the metal film to react with silicon from the exposed silicon surfaces, the heating also causing the dopant impurity ions to become situated at an interface between the exposed silicon surfaces and the metal silicide.
According to another aspect, the invention provides a method for forming a semiconductor device which includes providing a semiconductor substrate with a semiconductor device thereon, the semiconductor device having at least exposed silicon surfaces. The method provides for positioning the semiconductor substrate in an electroless plating solution that includes at least metal ions and dopant impurity ions therein, controlling conditions of the electroless plating solution to cause formation of a metal layer formed of the metal ions. The metal layer is formed on the silicon surface and the metal layer includes the dopant impurity ions therein. The method further provides for heating to cause reaction between the metal layer and the exposed silicon surfaces to form a metal silicide film and the heating further causes the dopant impurity ions to become institiated at an interface formed between the metal silicide film and the exposed silicon surfaces.
The present invention is best understood from the following detailed description when read in conjunction with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not necessarily to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Like numerals denote like features throughout the specification and drawing.
The process for forming metal silicide layers by selective electroless deposition of metal materials on exposed silicon surfaces of semiconductor devices, is shown in most general form in
The structure shown in
The structure shown in
After the optional pre-clean, a surface activation step (step 102) may be carried out. The surface activation operation is again a wet processing operation and may include exposing the structure shown in
After the surface activation operation, the structure shown in
In addition to the metal ions produced by the dissolution of the metal salt, dopant impurity ions such as B, P and W may also be included in the electroless deposition solution. According to an exemplary embodiment in which n-type dopant impurity boron, B, is the dopant impurity, the boron may be provided in the electroless deposition solution by using the DMAB reducing agent and according to an exemplary embodiment in which a p-type dopant impurity ion is desired, hypophosphite may be used as the reducing agent and as a source of phosphorous, P. Other boron and phosphorus sources may be used in other exemplary embodiments. According to yet another exemplary embodiment, tungstate, WO4, may be used as a tungsten, W, source to provide thermal stability during and after the subsequent silicidation process.
Key parameters are controlled to urge electroless deposition of a metal film selectively upon exposed silicon surfaces but not on dielectric surfaces. Key parameters may include temperature, pH, concentration of the metal ions, and concentration of the reducing agent in the solution. In one exemplary embodiment, the temperature may be advantageously maintained between about 40 to 90° C., the pH maintained between about 4-9 and the metal salt concentration maintained between about 0.05M-5M (mole/L). The reducing agent concentration may advantageously be maintained within a concentration of about 0.01M (mole/L)-1M (mole/L). Various conventional techniques and methods may be used to monitor the key parameters and control the same. In one exemplary embodiment, the pH may be maintained within about 8.5-10 and the deposition temperature between about 70 and 80° C. By controlling the key parameters to produce an electroless deposition solution with a desired combination of parameters, a metal film will form only on exposed silicon surfaces 10, 12 shown in
The parameters of the electroless plating solution are controlled such that a metal film consisting of the metal ions from the electroless plating solution deposit on exposed silicon surfaces such as exposed silicon surfaces 10, 12 shown in
After the deposition of metal film 20, and prior to any subsequent heating operations, and optional pos-deposition clean (step 106) may be carried out. The post-deposition clean may be carried out using a brush or other similar physical cleaning operation or it may be a clean carried out using a dilute acid clean similar to one of the pre-cleaning dilute acid cleaning operations described above.
The structure in
During either or both of the annealing operations, the dopant impurity ions such as B, P, etc., are driven to interface 28 formed between exposed silicon surfaces 10, 12 and silicide film 26. The presence of boron or phosphorus at interface 28 aids in lowering contact resistance to the metal silicide film 26. When tungsten is used as an impurity ion in metal silicide film 26, it serves to provide enhanced thermal stability and enables formation of the desired silicide phase with a restricted thermal budget.
The structure shown in
The preceding merely illustrates the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and conditional language recited herein are principally intended expressly to be only for pedagogical purposes and to aid the reader in understanding the principles of the invention and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.
This description of the exemplary embodiments is intended to be read in connection with the figures of the accompanying drawing, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal, “vertical,” above,” “below,” “up,” “down,” “tops” and “bottom” as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation.
Although the invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments of the invention, which may be made by those skilled in the art without departing from the scope and range of equivalents of the invention.
