This invention relates to computer system architecture and particularly to new instructions which augment the IBM z/Architecture and can be emulated by other architectures.
Before our invention IBM has created through the work of many highly talented engineers beginning with machines known as the IBM System 360 in the 1960s to the present, a special architecture which, because of its essential nature to a computing system, became known as “the mainframe” whose principles of operation state the architecture of the machine by describing the machine instructions which may be executed upon the “mainframe” implementation of the machine instructions which had been invented by IBM inventors and adopted, because of their significant contribution to improving the state of the computing machine represented by “the mainframe”, as significant contributions by inclusion in IBM's Principles of Operation as stated over the years. The First Edition of the z/Architecture Principles of Operation which was published December, 2000 has become the standard published reference as SA22-7832-00. We determined that further new instructions would assist the art and could be included in a z/Architecture machine and also emulated by others in simpler machines, as described herein.
It is an object of the present invention to provide a CPU-synchronous, problem-state, and sectioning instruction for computing a message authentication code for data in storage of a computer system.
It is a further object of the invention to provide an instruction for computing a message authentication code using a cryptographic key in the computing of the message authentication code.
It is a further object of the invention to provide an instruction for computing a message authentication code using a chaining value for a chaining operation for computing message authentication codes for data in a plurality of storage locations.
These and other objects will be apparent to one skilled in the art from the following detailed description of the invention taken in conjunction with the accompanying drawings in which:
The COMPUTE MESSAGE AUTHENTICATION CODE (KMAC) instruction will be discussed first, and then a preferred computer system, and, in the alternative, a computer system for emulating a computer system haveing a different architecture for executing the instrutcion.
Compute Message Authentication Code (KMAC)
A function specified by the function code in general register 0 is performed. Bits 16-23 of the instruction and the R1 field are ignored.
Bit positions 57-63 of general register 0 contain the function code.
General register 1 contains the logical address of the leftmost byte of the parameter block in storage. In the 24-bit addressing mode, the contents of bit positions 40-63 of general register 1 constitute the address, and the contents of bit positions 0-39 are ignored. In the 31-bit addressing mode, the contents of bit positions 33-63 of general register 1 constitute the address, and the contents of bit positions 0-32 are ignored.
In the 64-bit addressing mode, the contents of bit positions 0-63 of general register 1 constitute the address.
The function codes for COMPUTE MESSAGE AUTHENTICATION CODE are shown in
All other function codes are unassigned. The query function provides the means of indicating the availability of the other functions. The contents of general registers R2 and R2+1 are ignored.
For all other functions, the second operand is processed as specified by the function code using an initial chaining value in the parameter block and the result replaces the chaining value. The operation also uses a cryptographic key in the parameter block. The operation proceeds until the end of the second-operand location is reached or a CPU-determined number of bytes have been processed, whichever occurs first. The result is indicated in the condition code.
The R2 field designates an even-odd pair of general registers and must designate an even numbered register; otherwise, a specification exception is recognized.
The location of the leftmost byte of the second operand is specified by the contents of the R2 general register. The number of bytes in the second-operand location is specified in general register R2+1.
As part of the operation, the address in general register R2 is incremented by the number of bytes processed from the second operand, and the length in general register R2+1 is decremented by the same number. The formation and updating of the address and length is dependent on the addressing mode.
In the 24-bit addressing mode, the contents of bit positions 40-63 of general register R2 constitute the address of second operand, and are ignored; bits 40-63 of the updated address replace the corresponding bits in general register R_, carries out of bit position 40 of the updated address are ignored and, the contents of bit positions 32-39 of general register R_ are set to zeros. In the 31-bit addressing mode, the contents of bit positions 33-63 of general register R_ constitute the address of second operand, and the contents of bit positions 0-32 are ignored; bits 33-63 of the updated address replace the corresponding bits in general register R_, carries out of bit position 33 of the updated address are ignored, and the content of bit position 32 of general register R— is set to zero. In the 64-bit addressing mode, the contents of bit positions 0-63 of general register R— constitute the address of second operand; bits 0-63 of the updated address replace the contents of general register R— and carries out of bit position 0 are ignored.
In both the 24-bit and the 31-bit addressing modes, the contents of bit positions 32-63 of general register R2+1 form a 32-bit unsigned binary integer which specifies the number of bytes in the second operand; and the updated value replaces the contents of bit positions 32-63 of general register R2+1. In the 64-bit addressing mode, the contents of bit position 0-63 of general register R2+1 form a 64-bit unsigned binary integer which specifies the number of bytes in the second operand; and the updated value replaces the contents of general register R2+1.
In the 24-bit or 31-bit addressing mode, the contents of bit positions 0-31 of general registers R2 and R2+1, always remain unchanged.
In the access-register mode, access registers 1 and R2 specify the address spaces containing the parameter block and second operand, respectively.
The result is obtained as if processing starts at the left end of the second operand and proceeds to the right, block by block. The operation is ended when all source bytes in the second operand have been processed (called normal completion), or when a CPU-determined number of blocks that is less than the length of the second operand have been processed (called partial completion). The CPU-determined number of blocks depends on the model, and may be a different number each time the instruction is executed. The CPU-determined number of blocks is usually nonzero. In certain unusual situations, this number may be zero, and condition code 3 may be set with no progress. However, the CPU protects against endless reoccurrence of this no-progress case.
When the chaining-value field overlaps any portion of the second operand, the result in the chaining value field is unpredictable.
Normal completion occurs when the number of bytes in the second operand as specified in general register R+1 have been processed.
When the operation ends due to normal completion, condition code 0 is set and the resulting value in R2+1 is zero. When the operation ends due to partial completion, condition code 3 is set and the resulting value in R2+1 is nonzero.
When the second-operand length is initially zero, the second operand and the parameter block are not accessed, general registers R2 and R2+1 are not changed, and condition code 0 is set.
As observed by other CPUs and channel programs, references to the parameter block and storage operands may be multiple-access references, accesses to these storage locations are not necessarily block-concurrent, and the sequence of these accesses or references is undefined.
Access exceptions may be reported for a larger portion of the second operand than is processed in a single execution of the instruction; however, access exceptions are not recognized for locations beyond the length of the second operand nor for locations more than 4K bytes beyond the current location being processed.
Symbols Used in Function Descriptions
The symbols of
Further description of the data-encryption algorithm may be found in Data Encryption Algorithm, ANSI-X3.92.1981, American National Standard for Information Systems.
KMAC-Query (Function Code 0)
The locations of the operands and addresses used by the instruction are as shown in
A 128-bit status word is stored in the parameter block. Bits 0-127 of this field correspond to function codes 0-127, respectively, of the KMAC instruction. When a bit is one, the corresponding function is installed; otherwise, the function is not installed.
Condition code 0 is set when execution of the KMAC-Query function completes; condition code 3 is not applicable to this function.
KMAC-DEA (Function Code 1)
The locations of the operands and addresses used by the instruction are as shown in
The parameter block used for the KMAC-DEA function has the format shown in
The message authentication code for the 8-byte message blocks (M1, M2, . . . , Mn) in operand 2 is computed using the DEA algorithm with the 64-bit cryptographic key and the 64-bit chaining value in the parameter block.
The message authentication code, also called the output chaining value (OCV), is stored in the chaining-value field of the parameter block. The KMAC-DEA operation is shown in
KMAC-TDEA-128 (Function Code 2)
The locations of the operands and addresses used by the instruction are as shown in
The parameter block used for the KMAC-TDEA-128 function has the format shown in
The message authentication code for the 8-byte message blocks (M1, M2, . . . , Mn) in operand 2 is computed using the TDEA algorithm with the two 64-bit cryptographic keys and the 64-bit chaining value in the parameter block.
The message authentication code, also called the output chaining value (OCV), is stored in the chaining-value field of the parameter block. The KMAC-TDEA-128 operation is shown in
KMAC-TDEA-192 (Function Code 3)
The locations of the operands and addresses used by the instruction are as shown in
The parameter block used for the KMAC-TDEA-192 function has the format shown in
The message authentication code for the 8-byte message blocks (M1, M2, . . . , Mn) in operand 2 is computed using the TDEA algorithm with the three 64-bit cryptographic keys and the 64-bit chaining value in the parameter block.
The message authentication code, also called the output chaining value (OCV), is stored in the chaining-value field of the parameter block. The KMAC-TDEA-192 operation is shown in
Special Conditions for KMAC
A specification exception is recognized and no other action is taken if any of the following occurs:
Resulting Condition Code
Program Exceptions
Programming Notes
The preferred embodiment provides a crypto coprocessor which can be used with the instructions described herein and to execute cipher messages and assist in a variety of chaining message tasks which can be employed for chained and cryptographic use with the appropriate instructions.
The cryptographic control unit provides a cryptographic coprocessor directly attached to a data path common to all internal execution units of the central processing unit on a general purpose microprocessor providing the available hardware (E0 . . . En), or from a combination thereof in the preferred embodiment having multiple execution pipelines) for the central processing unit. When a cryptographic instruction is encountered in the command register (3), the control unit (2) invokes the appropriate algorithm from the available hardware. Operand data is delivered over the same internal microprocessor bus via an input FIFO register (4). When an operation is completed the a flag is set in a status register (6) and the results are available to be read out from the output FIFO register (5).
The illustrated preferred embodiment of our invention is designed to be extensible to include as many hardware engines as required by a particular implementation depending on the performance goals of the system. The data paths to the input and output registers (7) are common among all engines.
The preferred embodiment of the invention cryptographic functions are implemented in execution unit hardware on the CPU and this implementation enables a lower latency for calling and executing encryption operations and increases the efficiency.
This decreased latency greatly enhances the capability of general purpose processes in systems that frequently do many encryption operations, particularly when only small amounts of data are involved. This allows an implementation that can significantly accelerate the processes involved in doing secure online transactions. The most common methods of securing online transactions involve a set of three algorithms. The first algorithm is only used one time in a session, and may be implemented in hardware or software, while the other operations are invoked with every transaction of the session, and the cost in latency of calling external hardware as well as the cost in time to execute the algorithm in software are both eliminated with this invention.
In
As illustrated by
In
More particularly, these architected instructions can be used with a computer architecture with existing instruction formats with a 12 bit unsigned displacement used to form the operand storage address and also one having additional instruction formats that provide a additional displacement bits, preferably 20 bits, which comprise an extended signed displacement used to form the operand storage address. These computer architected instructions comprise computer software, stored in a computer storage medium, for producing the code running of the processor utilizing the computer software, and comprising the instruction code for use by a compiler or emulator/interpreter which is stored in a computer storage medium 501, and wherein the first part of the instruction code comprises an operation code which specified the operation to be performed and a second part which designates the operands for that participate. The long displacement instructions permit additional addresses to be directly addressed with the use of the long displacement facility instruction.
As illustrated by
While the preferred embodiment of the invention has been illustrated and described herein, it is to be understood that the invention is not limited to the precise construction herein disclosed, and the right is reserved to all changes and modifications coming within the scope of the invention as defined in the appended claims.
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