This following pertains generally to the field of charge pumps and more particularly to techniques for improving the efficiency of charge pumps.
Charge pumps use a combination of switches and capacitors to provide a DC output voltage higher or lower than its DC input voltage. To generate the required output, transfer of charge from input to output happens through Capacitors and switches. During one clock half cycle, the charging half cycle, the capacitor couples in parallel to the input so as to charge up to the input voltage. During a second half cycle, the boost half cycle, the charged capacitor's bottom plate is boosted with the input voltage so as to provide an output voltage twice the level of the input voltage. This process is illustrated in
Charge pumps are used in many contexts. For example, they are used as peripheral circuits on flash and other non-volatile memories to generate many of the needed operating voltages, such as sensing, programming or erase voltages, from a lower power supply voltage. A number of charge pump designs, such as conventional Dickson-type pumps, are know in the art. But given the common reliance upon charge pumps, there is an on going need for improvements in pump design and improving their efficiency.
A charge pump has first and second branches connected in parallel between a supply node and an output node. Each of the branches includes multiple stages connected in series, the first of which is connected to the supply node though a respective initial switch. Each of the stages has a stage capacitor, a stage node connected to the corresponding stage capacitor, and a transfer switch, through which the corresponding stage node is connected to the stage node of the subsequent stage in the series, except for the final stage of the series, whose stage node is connected through the corresponding transfer switch to the output node. When the charge pump is enabled, even and odd stages in the series of the first branch are respectively connected to receive first and second clock non-overlapping clock signals and even and odd stages in the series of the second branch are respectively connected to receive the second and first clock signals. The charge pump also includes first and second diodes through which the stage node of a first one of the stages in the series of both of the first and second branches are respectively connected to provide, for both of the first and second branches, the body bias of the transfer switches of the stage subsequent to the first one of the stages.
An integrated circuit includes an array of non-volatile memory cells; read, write, and erase circuitry connected to the array; and a charge pump. The charge pump has first and second branches connected in parallel between a supply node and an output node connectable to supply the read, write, and erase circuitry, wherein each of the branches includes multiple stages connected in series, the first of which is connected to the supply node though a respective initial switch. Each of the stages has a stage capacitor, a stage node connected to the corresponding stage capacitor, and a transfer switch, through which the corresponding stage node is connected to the stage node of the subsequent stage in the series, except for the final stage of the series, whose stage node is connected through the corresponding transfer switch to the output node. When the charge pump is enabled, even and odd stages in the series of the first branch are respectively connected to receive first and second clock non-overlapping clock signals and even and odd stages in the series of the second branch are respectively connected to receive the second and first clock signals. The charge pump also includes first and second diodes. The first and second diodes are connected through the stage node of a first one of the stages in the series of both of the first and second branches are respectively connected, for both of the first and second branches, to bias the body of the transfer switches of the stage subsequent to the first one of the stages.
Various aspects, advantages, features and embodiments are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail.
The techniques presented here are widely applicable to various charge pump designs to reduce overall power consumption for charge pump system and for reducing switching current. As noted in the Background, non-volatile memory systems often are designed for use with relative low voltage power supplies, but need higher voltage levels to perform various read, write and erase operations. For example, with NAND Memory applications, such as for 2D NAND or 3D devices such as of the BiCS type, elements such as bit line drivers and various op-amps use higher (2×-3×) than the given supply voltage. These voltages are generated by the charge pump circuitry on the memory chips that can be the major power consuming circuitry on the circuit. Furthermore these pumps are typically designed to operate at the single clock frequency at which the pump performance meets the worst case load conditions. This will result in high switching and high switching current at the lower loads. The techniques presented here can help to minimize the pump switching frequency according to the load current requirement, consequently minimizing the corresponding switching current. Although the following discussion is often given in the context of using a charge pump for a memory circuit, the techniques described are more generally applicable to other circuits where boosted voltage levels are needed.
With respect to the memory section 102, semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.
The memory devices can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.
Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.
The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure.
In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.
The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.
A three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).
As a non-limiting example, a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels. As another non-limiting example, a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements in each column. The columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.
By way of non-limiting example, in a three dimensional NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-z) memory device levels. Alternatively, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.
Typically, in a monolithic three dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory device levels.
Then again, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.
Associated circuitry is typically required for operation of the memory elements and for communication with the memory elements. As non-limiting examples, memory devices may have circuitry used for controlling and driving memory elements to accomplish functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and/or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements.
It will be recognized that the following is not limited to the two dimensional and three dimensional exemplary structures described but cover all relevant memory structures within the spirit and scope as described herein. More detail on such memory devices and systems is given in U.S. patent application Ser. No. 14/528,711 filed on Oct. 30, 2014.
For NAND memory applications, program, erase, and read operations often use high voltages in the range of 10-30V, while the chip supply level may be in the order of 2.3 to 3.6V. These high voltage supplies are generated through charge pump circuits. Typically high voltage charge pump designs uses high voltage devices. These devices have high body bias coefficients, which results in increased threshold voltage (VTH) and degraded device performance at higher voltages. The following presents techniques to reduce the voltage losses that typically arise in the transfer switches used in charge pumps.
In a typical charge pump arrangement, multiple stages connected in series by transfer switches are used to generate higher voltages, with two legs or branches of opposite phase. A number of topologies can be used for the individual stages, including voltage doublers, four-phase, and Dickson type pumps, among other. The following discussion is based on a Dickson type topology, but can also be applied to the transfer switches of other designs, such as voltage doubles, four-phase, and so on
Using a simple 3-stage, 2-phase Dickson charge pump as the exemplary embodiment to consider the situation further,
The timing diagram of the charge pump of
Consequently, a significant portion of the boosted voltage can be lost to the transfer switches, with the problem becoming more pronounced as the number of stages increase. A number of techniques have been introduced to deal with the problem. For example, one set of techniques involves boosting the gate voltages of the inter-stage transfer switches by various means, such as by an auxiliary pump. Other techniques switch the bulk connections of the transfer gates back and forth between the minimum voltage of the device's source and drain. However, these arrangements typically have a number of undesirable features in terms of layout area, efficient, leakage, or some combination of these. To help overcome this issues, the embodiment of
To ensure proper operation of MOSFETs of the transfer switches, the switch body voltage should be less than minimum of source and drain voltage, VBody<mm (VSource VDrain). This can be achieved by sampling the maximum of the previous stage's outputs through the diodes as shown in
In the embodiment of
Looking at the M24 device 407, for example, for the desired behavior the bulk would be min (VSource, VDrain), or min ([3SUP, 4SUP], (4SUP)), which is 3SUP. As 3SUP is max (V32, V23), this level can be generated by using the diode connection through 505 to the V32 node and through the diode 525 to the V23 node. Additionally, the diode drop will be available to make sure the VTH for the diodes is more than 0.
The use of selective body bias is described above in the context of a 3-stage Dickson-type pump architecture, but readily extends to other numbers of stages and other types of multi-stage pumps, as this problem of voltage loss across the transfer switches is also found in these. In
Regulation has not been considered in any detail, as the circuit of
The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the above to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described examples were chosen in order to explain the principals involved and its practical application, to thereby enable others to best utilize the various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.
This application claims priority from, U.S. Provisional Applications Nos. 62/220,479, filed on Sep. 18, 2015, which is hereby incorporated in its entirety by this reference.
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