Patent Grant
10600902
As semiconductor fabrication technology continues to progress, devices such as field effect transistors (FET) continue to get smaller and less expensive. The design and layout for such devices are constrained by technology specific minimum sizes, spacings, alignments and overlaps of the various structures of the device and the fabrication means. During manufacturing a percentage of the devices are defective due to process variations.
A typical power MOSFET device may have thousands or millions of parallel MOSFET cells. The large number of parallel linked cells enable the device to handle high current and have a low on resistance. Generally, the higher the current carrying capability of the device, the high the number of cells there are in the device. When a single cell in the device is defective, such as a gate-to-source or source-to-drain short, the defect typically damages the entire device. Therefore, when one cell is defective, the whole device has to be discarded, reducing the manufacturing yield. The massive parallel cell structure also makes it difficult to screen the devices. In particular, non-catastrophic defects between source-to-gate and drain-to-gate are not easily detectable. The non-catastrophic device may therefore cause reliability issued with the device and/or the electronics in which it is utilized.
Embodiments of the present invention are directed toward self-repairing transistors. In one embodiment, a field effect transistor WET) device includes a plurality of FET cells. A dielectric layer is disposed between the plurality of cells and the source interconnect of the device. A source contact of each cell is coupled to the source interconnect by a corresponding source fuse link.
In another embodiment, an integrated circuit (IC) includes a drain region, a gate region, a plurality of source regions, a plurality of body regions and a plurality of gate insulator regions. The gate region is disposed above the drain region, wherein a first portion of the gate region is formed as a first plurality of substantially parallel elongated structures and a second portion of the gate region is formed as a second plurality of substantially parallel elongated structures that are perpendicular to the first plurality of substantially parallel elongated structures. The plurality of source regions are disposed proximate a periphery of the gate region within each cell defined by the first and second plurality of substantially parallel elongated structures. The plurality of body regions are disposed between the drain region and the source region within each cell. The gate insulator region is disposed between the gate region and the plurality of source regions, between the gate region and the plurality of body regions and between the gate region and the drain region. The (IC) also includes a plurality of source contacts, a source interconnect, and a plurality of source fuse links. The plurality of source contacts are each coupled to a corresponding source region. The source fuse links couple corresponding source contacts to the source interconnect.
In yet another embodiment, a method of fabricating a field effect transistor device includes forming a plurality of field effect transistor cells, wherein each cell includes a source region. The method also includes forming a plurality of source contacts, a plurality of source fuse links and a source interconnect. Each given source contact is coupled to a corresponding source region. Each source fuse link is coupled to a corresponding source contact. The source interconnect is coupled to the plurality of source fuse links.
Embodiments of the present technology are illustrated by way of example and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
Reference will now be made in detail to the embodiments of the present technology, examples of which are illustrated in the accompanying drawings. While the present technology will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, die invention is intended to cover alternatives, modifications and equivalents, which may be included within the scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present technology, numerous specific details are set forth in order to provide a thorough understanding of the present technology. However, it is understood that the present technology may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present technology.
Embodiments of the present invention include self-repairing field effect transistors (FET) and methods of manufacturing the same. In particular, a fuse is added to each individual cell of FET devices having massively parallel cell structures. When a cell is defective, excessive current through the cell will brown up the cell, automatically disabling the defective cell. The fuse may be vertically aligned with the cell and therefore will not substantially increase the surface area of the cell. The FET devices may be MOSFETs, JFETs or the like. Furthermore, the FET devices may have a vertical or planar topology.
It is appreciated that FET devices are substantially symmetrical. In particular, the source and drains of the FET devices may generally be swapped. Therefore, it is to be understood that the use of the term “source” herein is also equivalent to “drain” when the source and drains are interchanged.
Referring to
The MOSFET device may include a plurality of source/body contacts 110, a plurality of source regions 115, a gate region 120, a gate insulator region 125, a plurality of body regions 130, a drain region 135, 140 and a drain interconnect 145. The drain region 135, 140 may optionally include a first drain portion 140 usually referred to as a drift region, and a second drain portion 135 usually referred to as the drain region. The MOSFET device also includes an encapsulation layer 150, a plurality of source fuse links 155, and a source interconnect 160.
The body regions 130, the source regions 115, the gate region 120 and the gate insulator region 125 are disposed above the drain region 135, 140. A first portion of the gate region 120 and the gate insulator region 125 is formed as substantially parallel-elongated structures 121. A second portion of the gate region 120 and the gate insulation region 125 is formed as substantially normal-to-parallel elongated structures 122. The first and second portions of the gate region 120 are all interconnected and form the plurality of cells. The body regions 130 are disposed within the plurality of cells formed by the gate region 120. The gate insulator region 125 surrounds the gate region 120. Thus, the gate region 120 is electrically isolated from the surrounding regions by the gate insulator region 125. The source regions 115 are formed in The plurality of cells, along the periphery of the gate insulator region 125.
In one implementation, the source regions 115 and the drain region 140 are heavily n-doped (+N) semiconductor, such as silicon doped with phosphorous or arsenic. The body regions 130 are p-doped (P) semiconductor, such as silicon doped with boron. The gate region 120 is heavily n-doped semiconductor (N+), such as polysilicon doped with phosphorous. The gate insulator region 125 may be an insulator, such as silicon dioxide.
A source/body contact 110 is coupled to the source region 115 and the body region 130 of each cell. Thus, the source/body contact 110 couples the source region 115 to the body region 130 of each cell. The encapsulation layer is disposed between the gate region 120, the source region 115, the source/body contacts 110, the source fuse links 155, and the source interconnect 160. The source fuse links 155 are disposed between the source/body contacts 110 and the source interconnect 160. The source interconnect 160 couples the plurality of source regions 115 to form a common source of the device. The source fuse links 155 vertically extend from the source/body contacts 115, on top of each individual cell, and therefore do not consume additional lateral surface area in the device 100.
When the potential of the gate region 120, with respect to the source regions 115, is increased above the threshold voltage of the device 100, a conducting channel is induced in the body region 130 along the periphery of the gate insulator region 125. The device 100 will then conduct current between the drain region 140 and the source regions 115. Accordingly, the device 100 is in its on state.
When the potential of the gate region 120 is reduced below the threshold voltage, the channel is no longer induced. As a result, a voltage potential applied between the drain region 140 and the source regions 115 will not cause current to flow there between. Accordingly, the device is in its off state and the junction formed by the body region 130 and the drain region 140 supports the voltage applied across the source and drain.
If the drain region 135, 140 comprises a second portion 135 disposed above a first portion 140, the second portion of the drain region 135 is lightly n-doped (N−) semiconductor, such as silicon doped with phosphorous or arsenic, and the first portion of the drain region 140 is heavily n-doped (N+) semiconductor, such as silicon doped with phosphorous. The lightly n-doped (N−) second portion of the drain region 135 results in a depletion region that extends into both the body regions 130 and the second portion of the drain region 135, thereby reducing the punch through effect. Accordingly, the lightly n-doped (N−) second portion of the drain region 135 acts to increase the breakdown voltage of the closed cell TMOSFET 200.
The channel width of the closed cell TMOSFET 100 is a function of the slim of the width of the source regions 115. Accordingly, the closed cell TMOSFET 100 has a relatively low channel resistance (e.g., drain-to-source on resistance Rds-on). The low channel resistance reduces power dissipated in the closed cell TMOSFET 100. Similarly, the gate-to-drain capacitance of the closed cell TMOSFET 120 is a function of the area of overlap between the bottom of the gate region 120 and the drain region 140.
In one implementation, the encapsulant 150 may be a dielectric, such as but not limited to BPSG. The source/body contacts 110 may be made of a high melting point metal, such as but not limited to tantalum, titanium, tungsten, titanium nitride, tantalum nitride, and/or titanium silicide. The source fuse link 155 may be made of a low melting point metal, such as but not limited to copper, aluminum, bismuth, indium and/or tin. The source interconnect 160 may be made of a high or low melting point metal or a combination thereof.
In one implementation, the source fuse links 155 may be substantially solid. When a relatively high current flows through the source of a given cell, heat will be concentrated in the corresponding source fuse link. The heat melts the metal of the given fuse link and causes localized melting of the surrounding encapsulant 150. The localized melting of the surrounding encapsulant forms a void into which the low melting point metal of the source fuse link will flow, thereby creating a break in the source fuse link. When a break in the source fuse link develops the fuse is “blown” and the high current path through the cell is broken.
In another implementation, the source fuse links 155 may each contain a cavity, as illustrated in
Each fuse link 255 is constructed to be blown before the corresponding cell damages other cells. A typical MOSFET cell carries about 0.1 mA in direct current mode (DC mode) and 0.5 mA in pulse mode. When a given cell is defective and there is a high current path (e.g. short) between the gate-to-source, gate-to-drain or source-to-drain the in rush current in the give cell will get progressively larger, typically reaching 10-100 mA. The fuse links are constructed to be blown before the corresponding cell reaches this high current level, preventing damage to the rest of the cells in the device. Accordingly, the defective cell is disabled and the rest of the cells remain functional. The device is thus self-repairing with little or no performance degradation.
Referring now to
In an exemplary implementation, for a FET device having a source fuse link, it is assumed that no heat is lost to the surroundings, that the head capacity is constant between room temperature and the melting point. The volume space of the void in the source fuse link 300 is substantially equal to the aluminum volume of the source fuse link 310. The melt energy is assumed to be the sum of heat needed to raise the temperature and the enthalpy of fusion. The number of parallel cells in the exemplary device may be approximate 1,000,000 cells. The chip is assumed to operate at a room temperature of 295 K.
The individual cell fuse link area resistance may be calculated according to equation 1, as follows.
r=ρ*L*4/[π*(D2−d2)] (1)
The chip resistance due to the added aluminum fuse may be calculated according to equation 2, as follows:
R=r/N (2)
wherein N is the number of parallel cells. The energy required to melt one cell fuse may be calculated according to equation 3, as follows:
E=Volume*d*(Cp*ΔT+ΔHfusion)/AW (4)
wherein AW is the atomic weight, d is the density, Cp is the molar heat capacity, and ΔHfusion is the enthalpy of fusion. Accordingly, the time required to melt the source fuse link for a cell may be calculated according to equation 4, as follows:
Referring now to
Referring now to
Referring now to
Referring now to
At 610, the gate trench mask 706 is removed utilizing an appropriate resist stripper or a resist ashing process. Referring now to
Referring now to
Referring now to
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Referring now to
In another embodiment, the source fuse link trenches may have a larger aspect ratio. The source fuse link trenches are filled with a metal using a process such as sputtering. A photo-resist layer is deposited and patterned to define a source fuse link cavity in the metal deposited in the source fuse link trenches. A selective etching process is used to remove the exposed portion of the metal in the source fuse link trenches 748. The source interconnect metal layer is then deposited on the surface of the wafer.
At 656, the source interconnect metal layer 754 is patterned to form a source interconnect that is electrically coupled to the source contacts by the source fuse links. At 658, fabrication continues with various other processes. The various processes typically include etching, deposition, doping, cleaning, annealing, passivation, cleaving and/or the like.
Referring now to
The gate region 815 is disposed proximate the portion of the drain region 830, 835 that extends up between the body regions 825, proximate the portion of the body regions 825 between the source regions 805 and the drain region 830, 835, and proximate a portion of the source regions 810. The gate insulator region 820 surrounds the gate region 815, thereby separating the gate region 815 from the body regions 825, the source regions 810 and the drain region 830, 835. The drain region 830, 835 may include a first drain portion 830, usually referred to as a drift region, proximate the body regions 825 and a second drain portion 835, usually referred to as the drain region, separated from the body regions 825 by the drift region.
The source/body contacts 805 are each coupled to respective ones of the body regions 825 and source regions 810. Thus, the source/body contact 805 couples the source region 810 to the body region 825 of each cell. The encapsulation layer 845 is disposed between the source/body contacts 805 and the source interconnect 855. The source fuse links 850 extend through the encapsulation layer 845 between the source/body contacts 805 and the source interconnect 855. The source fuse links 850 vertically extend from the source/body contacts 805, on top of each individual cell, and therefore do not consume additional lateral surface area in the device 800.
When the potential of the gate region 815 is increased above the threshold voltage of the device 800, a conducting channel is induced in the portion of the body region 825 between the source regions 810 and the drain region 830, 835. The device 800 will then conduct current between the drain region 830, 835 and the source regions 810. Accordingly, the device 800 is in its on state. When the potential of the gate region 815 is reduced below the threshold voltage, the channel is no longer induced. As a result, a voltage potential applied between the drain region 830, 835 and the source regions 810 will not cause current to flow there between. Accordingly, the device is in its off state and the junction formed by the body region 825 and the drain region 830, 835 supports the voltage applied across the source and drain.
Each source fuse link 850 is constructed to be blown by a failure mode level of current. Accordingly, a defective cell is disabled and the rest of the cells remain functional. The device 800 is thus self-repairing with little or no performance degradation. In one implementation, the source fuse links 850 may be substantially solid. In another implementation, the source fuse links 850 may each contain a cavity that extends at least a portion of the length of each source fuse link.
Referring now to
Embodiments of the present invention can be used to disabled one or more cells in a FET device with gate-to-source, gate-to-drain, and/or source-to-drain short. The fuse link may be constructed for both planar and vertical FET devices. The fuse link may be vertically constructed without consuming additional silicon area. Accordingly, embodiments advantageously implement a self-repairing field effect transistor (FET) device.
The foregoing descriptions of specific embodiments of the present technology have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the present technology and its practical application, to thereby enable others skilled in the art to best utilize the present technology and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.
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