Patent Application
20220352226
The technology according to the present disclosure (present technology) relates to a semiconductor apparatus and a semiconductor apparatus manufacturing method.
In the past, there has been a known method of increasing the vertical density of elements such as transistors by stacking plural substrates each of which has elements formed therein (see PTL 1). This method has a feature that not only one planar surface is used, but the number of elements increases as the number of planar surfaces to be used increases to two or to three by stacking them one on another. In a case where this method is used for elements for which area sizes are limited, the elements can be increased, and a complicated circuit can be configured in small area sizes.
Pixel sizes in image sensors are fixed, and the area size of elements formed for each pixel is limited to a pixel size. Accordingly, the sizes of elements cannot be changed freely, and furthermore there is a limitation in terms of increase of the number of elements for the purpose of forming a complicated circuit. Accordingly, a method that increases area sizes of elements by forming a stacked structure of plural substrates is a very beneficial method for devices like image sensors in which area sizes of elements are restricted.
JP 2014-99582A
There is a possibility that in a stacked structure of plural substrates, noise and heat such as electromagnetic waves, infrared rays or surges are propagated to each other between elements formed in upper and lower substrates, and characteristics of the elements deteriorate.
An object of the present technology is to provide a semiconductor apparatus and a semiconductor apparatus manufacturing method that make it possible to suppress propagation of noise and heat between elements formed in upper and lower substrates in a stacked structure of plural substrates, and suppress deterioration of characteristics of the elements.
According to the gist of a semiconductor apparatus according to one aspect of the present technology, the semiconductor apparatus includes: a first substrate that includes a first element layer including a first active element, a first wiring layer arranged on the first element layer, and a shield layer including an electrically conductive material arranged on the first wiring layer; and a second substrate that includes a second element layer including a second active element arranged on the shield layer, and a second wiring layer arranged on the second element layer, in which the first substrate and the second substrate are stacked one on another.
According to the gist of a semiconductor apparatus manufacturing method according to another aspect of the present technology, the semiconductor apparatus manufacturing method includes: forming a first wiring layer on a first element layer including a first active element; forming a first substrate including the first element layer, the first wiring layer, and a shield layer, by forming the shield layer including an electrically conductive material on the first wiring layer; preparing a second substrate in which a second element layer including a second active element is formed; forming the second element layer on the shield layer by pasting, on a shield layer side of the first substrate, a second element layer side of the second substrate; and forming a second wiring layer on the second element layer.
According to the gist of a semiconductor apparatus according to another aspect of the present technology, the semiconductor apparatus includes: a first substrate that includes a first element layer including a first active element, and a first wiring layer arranged on the first element layer; and a second substrate that includes a second element layer including a second active element, and a second wiring layer arranged on the second element layer, in which the first substrate and the second substrate are stacked one on another, and the semiconductor apparatus further includes, between the first substrate and the second substrate, an electromagnetic shield layer including an electrically conductive material.
According to the gist of a semiconductor apparatus manufacturing method according to another aspect of the present technology, the semiconductor apparatus manufacturing method includes: forming a first substrate including a first element layer and a first wiring layer, by forming the first wiring layer on the first element layer including a first active element; preparing a second substrate; forming an electromagnetic shield layer including an electrically conductive material on the first substrate or the second substrate; pasting together the first substrate and the second substrate with the electromagnetic shield layer being interposed therebetween; forming, on the second substrate, a second element layer including a second active element; and forming a second wiring layer on the second element layer.
According to the gist of a semiconductor apparatus according to another aspect of the present technology, the semiconductor apparatus includes: a first substrate that includes a first element layer including a first active element, a first wiring layer arranged on the first element layer, and a photoelectric converting section arranged under the first element layer; and a second substrate that includes a second element layer including a second active element, and a second wiring layer arranged on the second element layer, in which the first substrate and the second substrate are stacked one on another, and the semiconductor apparatus further includes, between the second active element and the photoelectric converting section, a light attenuation section including a material whose refractive index is higher than a refractive index of surrounding materials.
According to the gist of a semiconductor apparatus manufacturing method according to another aspect of the present technology, the semiconductor apparatus manufacturing method includes: forming a first substrate including a first element layer, a first wiring layer, and a photoelectric converting section, by forming the first wiring layer on the first element layer including a first active element and forming the photoelectric converting section under the first element layer; preparing a second substrate; forming, in the second substrate, a light attenuation section including a material whose refractive index is higher than a refractive index of surrounding materials; pasting together the first substrate and a light attenuation section side of the second substrate; forming, on the second substrate, a second element layer including a second active element; and forming a second wiring layer on the second element layer.
According to the gist of a semiconductor apparatus according to another aspect of the present technology, the semiconductor apparatus includes: a first substrate that includes a first element layer including a first active element, a first wiring layer arranged on the first element layer, and a photoelectric converting section arranged under the first element layer; a second substrate that includes a second element layer including a second active element, and a second wiring layer arranged on the second element layer; and a reflection preventing section that includes a material whose refractive index is lower than a refractive index of a semiconductor material included in the second substrate, in which the first substrate and the second substrate are stacked one on another, and the reflection preventing section is arranged at least between the second active element and the photoelectric converting section.
According to the gist of a semiconductor apparatus manufacturing method according to another aspect of the present technology, the semiconductor apparatus manufacturing method includes: forming a first substrate including a first element layer, a first wiring layer, and a photoelectric converting section, by forming the first wiring layer on the first element layer including a first active element and forming the photoelectric converting section under the first element layer; preparing a second substrate; forming, in the second substrate, a reflection preventing section including a material whose refractive index is lower than a refractive index of a semiconductor material included in the second substrate; pasting together the first substrate and a reflection preventing section side of the second substrate; forming, on the second substrate, a second element layer including a second active element; and forming a second wiring layer on the second element layer.
Hereinafter, first to seventh embodiments of the present technology are explained with reference to the figures. In the descriptions of the figures that are referred to in the following explanation, identical or similar portions are given identical or similar reference characters. It should be noted however that the figures are schematic figures, and the relation between thicknesses and planar dimensions, the ratio of the thicknesses of layers and the like are different from actual ones. Accordingly, specific thicknesses and dimensions should be determined by taking the following explanation into consideration. In addition, certainly, dimensions depicted in different figures may have different relation and ratios from each other. Note that advantages described in the present specification are presented merely for illustrative purposes, the advantages of the present disclosure are not limited to them, and there may be other advantages.
The first substrate 10 has a semiconductor substrate 11 having plural sensor pixels 12 that perform photoelectric conversion. The plural sensor pixels 12 are provided in a matrix in a pixel region 13 of the first substrate 10. The second substrate 20 has a semiconductor substrate 21 having, for each set of four sensor pixels 12, one read circuit 22 that outputs pixel signals based on electric charge output from the sensor pixels 12. The semiconductor substrate 21 corresponds to a specific example of a “second semiconductor substrate” of the present technology. The second substrate 20 has plural pixel driving lines 23 extending in the row direction and plural vertical signal lines 24 extending in the column direction. The third substrate 30 has a semiconductor substrate 31 having a logic circuit 32 that processes pixel signals. The semiconductor substrate 31 corresponds to a specific example of a “third semiconductor substrate” of the present technology. For example, the logic circuit 32 has a vertical driving circuit 33, a column signal processing circuit 34, a horizontal driving circuit 35 and a system control circuit 36. The logic circuit 32 (specifically, the horizontal driving circuit 35) outputs an output voltage Vout of each sensor pixel 12 to the outside. For example, the logic circuit 32 has an impurity diffusion region contacting source electrodes and drain electrodes, and the front surface of the impurity diffusion region may have low resistance regions including a silicide such as CoSi2 or NiSi formed by using the salicide (Self Aligned Silicide) process.
For example, the vertical driving circuit 33 sequentially selects each row of the plural sensor pixels 12. For example, on a pixel signal output from each sensor pixel 12 in a row selected by the vertical driving circuit 33, the column signal processing circuit 34 performs a correlated double sampling (Correlated Double Sampling: CDS) process. For example, by performing the CDS process, the column signal processing circuit 34 extracts the signal level of a pixel signal, and retains pixel data according to a received light amount of each sensor pixel 12. For example, the horizontal driving circuit 35 sequentially outputs pixel data retained at the column signal processing circuit 34 to the outside. For example, the system control circuit 36 controls driving of each block (the vertical driving circuit 33, the column signal processing circuit 34 and the horizontal driving circuit 35) in the logic circuit 32.
The sensor pixels 12 have mutually the same constituent elements. In order to make distinctions between constituent elements of the sensor pixels 12, identification numbers (1, 2, 3 and 4) are given at the ends of reference characters of the constituent elements of the sensor pixels 12 in
For example, each sensor pixel 12 has a photodiode PD, a transfer transistor TR electrically connected with the photodiode PD and a floating diffusion FD that temporarily retains electric charge output from the photodiode PD via the transfer transistor TR. The photodiode PD corresponds to a specific example of a “photoelectric converting element” of the present technology. The photodiode PD performs photoelectric conversion, and generates electric charge according to a received light amount. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to a pixel driving line 23. For example, the transfer transistor TR is a CMOS (Complementary Metal Oxide Semiconductor) transistor.
The floating diffusions FD of the sensor pixels 12 sharing the one read circuit 22 are electrically connected with each other, and are electrically connected to an input terminal of the common read circuit 22. For example, the read circuit 22 has a reset transistor RST, a selection transistor SEL and an amplification transistor AMP. Note that the selection transistor SEL may be omitted as necessary. The source (the input terminal of the read circuit 22) of the reset transistor RST is electrically connected to the floating diffusions FD, and the drain of the reset transistor RST is electrically connected to a power line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically connected to a pixel driving line 23 (see
When the transfer transistor TR is turned on, the transfer transistor TR transfers electric charge of the photodiode PD to the floating diffusion FD. For example, as depicted in
The source (the output terminal of the read circuit 22) of the amplification transistor AMP is electrically connected to the vertical signal line 24, an FD transfer transistor FDG is provided between the source of the reset transistor RST and the gate of the amplification transistor AMP, and the gate of the amplification transistor AMP is electrically connected to the source of the FD transfer transistor FDG.
The FD transfer transistor FDG is used when conversion efficiency is to be switched. Typically, pixel signals are small at the time of imaging at a dark location. On the basis of Q=CV, when electric charge-voltage conversion is performed, if the capacitance (FD capacitance C) of the floating diffusion FD is large, V at the time of conversion into a voltage with the amplification transistor AMP inevitably becomes small. On the other hand, pixel signals become large at a bright location, and so if the FD capacitance C is not large, the floating diffusion FD cannot fully receive the electric charge of the photodiode PD. Further, it is necessary for the FD capacitance C to have become large in order to prevent V at the time of conversion into a voltage at the amplification transistor AMP from becoming too large (in other words, in order for V to become small). Taking these into consideration, when the FD transfer transistor FDG is turned on, there is an increase of the gate capacitance by an amount corresponding to the FD transfer transistor FDG, and so the overall FD capacitance C becomes large. On the other hand, when the FD transfer transistor FDG is turned off, the overall FD capacitance C becomes small. In such a manner, it is possible to make the FD capacitance C variable, and switch the conversion efficiency by turning on and off the FD transfer transistor FDG.
The first substrate 10 includes an insulation layer 46 stacked on the semiconductor substrate 11. The insulation layer 46 corresponds to a specific example of a “first insulation layer” of the present technology. The first substrate 10 has the insulation layer 46 as a part of an interlayer dielectric film 51. The insulation layer 46 is provided at the gap between the semiconductor substrate 11 and the semiconductor substrate 21 mentioned below. The semiconductor substrate 11 includes a silicon substrate. For example, at and near a part of its front surface, the semiconductor substrate 11 has a p well layer 42, and in another region (a region deeper than the p well layer 42), the semiconductor substrate 11 has a PD 41 whose conductivity type is different from that of the p well layer 42. The p well layer 42 includes a p-type semiconductor region. The PD 41 includes a semiconductor region whose conductivity type (specifically, n type) is different from that of the p well layer 42. In the p well layer 42, the semiconductor substrate 11 has a floating diffusion FD as a semiconductor region whose conductivity type (specifically, n type) is different from that of the p well layer 42.
For each sensor pixel 12, the first substrate 10 has a photodiode PD, a transfer transistor TR and a floating diffusion FD. At a portion on the front surface side (a side opposite to the light-incidence surface side, the second substrate 20 side) of the semiconductor substrate 11, the first substrate 10 includes transfer transistors TR and floating diffusions FD. The first substrate 10 has element separating sections 43 that separate sensor pixels 12 from each other. Each element separating section 43 is formed as a section extending in the normal direction of the semiconductor substrate 11 (a direction perpendicular to the front surface of the semiconductor substrate 11). The element separating section 43 is provided between two sensor pixels 12 that are adjacent to each other. The element separating section 43 electrically separates, from each other, the sensor pixels 12 that are adjacent to each other. For example, the element separating section 43 includes silicon oxide. For example, the element separating section 43 penetrates the semiconductor substrate 11. For example, the first substrate 10 further has p well layers 44 that are in contact with surfaces which are side surfaces of the element separating sections 43, and that are on the photodiode PD sides. Each p well layer 44 includes a semiconductor region whose conductivity type (specifically, p type) is different from that of the photodiodes PD. For example, the first substrate 10 further has fixed electric charge films 45 that are in contact with the backside of the semiconductor substrate 11. The fixed electric charge film 45 is charged negatively in order to suppress generation of dark currents caused by the interface state on the light-reception surface side of the semiconductor substrate 11. For example, each fixed electric charge film 45 includes an insulating film having negative fixed electric charge. For example, examples of a material of such an insulating film include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide and tantalum oxide. An electrical field induced by the fixed electric charge film 45 forms a hole accumulation layer at the interface on the light-reception surface side of the semiconductor substrate 11. This hole accumulation layer suppresses generation of electrons from the interface. The color filter 40 is provided on the backside of the semiconductor substrate 11. For example, the color filter 40 is provided in contact with the fixed electric charge film 45, and is provided at a position facing the sensor pixel 12 with the fixed electric charge film 45 being interposed therebetween. For example, the light-reception lens 50 is provided in contact with the color filter 40, and is provided at a position facing the sensor pixel 12 with the color filter 40 and the fixed electric charge film 45 being interposed therebetween.
The second substrate 20 includes an insulation layer 52 stacked on the semiconductor substrate 21. The insulation layer 52 corresponds to a specific example of a “third insulation layer” of the present technology. The second substrate 20 has the insulation layer 52 as a part of the interlayer dielectric film 51. The insulation layer 52 is provided at the gap between the semiconductor substrate 21 and the semiconductor substrate 31. The semiconductor substrate 21 includes a silicon substrate. The second substrate 20 has one read circuit 22 for each set of four sensor pixels 12. The second substrate 20 includes the read circuit 22 provided at a portion on the front surface side (third substrate 30 side) of the semiconductor substrate 21. The second substrate 20 is pasted onto the first substrate 10 with the backside of the semiconductor substrate 21 facing the front surface side of the semiconductor substrate 11. That is, the second substrate 20 is pasted onto the first substrate 10 face-to-back. In the layer where there is the semiconductor substrate 21, the second substrate 20 further has an insulation layer 53 penetrating the semiconductor substrate 21. The insulation layer 53 corresponds to a specific example of a “second insulation layer” of the present technology. The second substrate 20 has the insulation layer 53 as a part of the interlayer dielectric film 51. The insulation layer 53 is provided to cover the side surface of a through-wire 54 mentioned below.
The stack including the first substrate 10 and the second substrate 20 has the interlayer dielectric film 51 and the through-wire 54 provided in the interlayer dielectric film 51. The through-wire 54 corresponds to a specific example of a “first through-wire” of the present technology. The stack described above has one through-wire 54 for each sensor pixel 12. The through-wire 54 extends in the normal direction of the semiconductor substrate 21, and is provided to penetrate a location which is in the interlayer dielectric film 51 and includes the insulation layer 53. The first substrate 10 and the second substrate 20 are electrically connected with each other by the through-wire 54. Specifically, the through-wire 54 is electrically connected to the floating diffusion FD and a connection wire 55 mentioned below.
The stack including the first substrate 10 and the second substrate 20 further has through-wires 47 and 48 (see
For example, in the insulation layer 52, the second substrate 20 has plural connecting sections 59 that are electrically connected with the read circuit 22 and the semiconductor substrate 21. For example, the second substrate 20 further has a wiring layer 56 on the insulation layer 52. For example, the wiring layer 56 has an insulation layer 57, and plural pixel driving lines 23 and plural vertical signal lines 24 that are provided in the insulation layer 57. For example, in the insulation layer 57, the wiring layer 56 further has one of the plural connection wires 55 for each set of four sensor pixels 12. The connection wire 55 electrically connects, with each other, through-wires 54 that are electrically connected to floating diffusions FD included in four sensor pixels 12 sharing the read circuit 22. Here, the total number of the through-wires 54 and 48 is larger than the total number of sensor pixels 12 included in the first substrate 10, and is twice as large as the total number of the sensor pixels 12 included in the first substrate 10. In addition, the total number of the through-wires 54, 48 and 47 is larger than the total number of sensor pixels 12 included in the first substrate 10, and is three times as large as the total number of the sensor pixels 12 included in the first substrate 10.
For example, in the insulation layer 57, the wiring layer 56 further has plural pad electrodes 58. For example, each pad electrode 58 includes a metal such as Cu (copper) or Al (aluminum). Each pad electrode 58 is exposed at the front surface of the wiring layer 56. Each pad electrode 58 is used for electrically connecting the second substrate 20 and the third substrate 30, and pasting together the second substrate 20 and the third substrate 30. For example, each of the plural pad electrodes 58 is provided for one of pixel driving lines 23 and vertical signal lines 24. Here, the total number of the pad electrodes 58 (or the total number of junctions between the pad electrodes 58 and pad electrodes 64 (mentioned below)) is smaller than the total number of sensor pixels 12 included in the first substrate 10.
For example, the third substrate 30 includes an interlayer dielectric film 61 stacked on the semiconductor substrate 31. Note that, as mentioned below, the third substrate 30 is pasted together with the second substrate 20 on surfaces on their front surface sides, and so when the configuration in the third substrate 30 is explained, its upward/downward direction is the reverse direction of the upward/downward direction of figures. The semiconductor substrate 31 includes a silicon substrate. The third substrate 30 includes the logic circuit 32 provided at a portion on the front surface side of the semiconductor substrate 31. For example, the third substrate 30 further has a wiring layer 62 on the interlayer dielectric film 61. For example, the wiring layer 62 has an insulation layer 63, and plural pad electrodes 64 provided in the insulation layer 63. The plural pad electrodes 64 are electrically connected with the logic circuit 32. For example, each pad electrode 64 includes Cu (copper). Each pad electrode 64 is exposed at the front surface of the wiring layer 62. Each pad electrode 64 is used for electrically connecting the second substrate 20 and the third substrate 30, and pasting together the second substrate 20 and the third substrate 30. In addition, there does not necessarily have to be plural pad electrodes 64, but even one pad electrode 64 can form an electrical connection with the logic circuit 32. The second substrate 20 and the third substrate 30 are electrically connected with each other by junctions between the pad electrodes 58 and 64. That is, the gate (transfer gate TG) of the transfer transistor TR is electrically connected to the logic circuit 32 via the through-wire 54 and the pad electrodes 58 and 64. The third substrate 30 is pasted onto the second substrate 20 with the front surface of the semiconductor substrate 31 facing the front surface side of the semiconductor substrate 21. That is, the third substrate 30 is pasted onto the second substrate 20 face-to-face.
In the past, miniaturization of the area size per pixel of an image pickup apparatus with a two-dimensional structure has been realized by introduction of miniaturization processes and enhancement of implementation density. In recent years, in order to realize further size reduction of image pickup apparatuses and miniaturization of the area size per pixel, image pickup apparatuses with three-dimensional structures have been developed. For example, in an image pickup apparatus with a three-dimensional structure, a semiconductor substrate having plural sensor pixels and a semiconductor substrate having a signal processing circuit that processes signals obtained by the sensor pixels are stacked one on another. Thereby, it is possible to further increase the degree of integration of sensor pixels, further increase the size of a signal processing circuit, and so on with chip sizes equivalent to conventional chip sizes.
Meanwhile, in a case where three layers of semiconductor chips are stacked one on another in an image pickup apparatus with a three-dimensional structure, it is not possible to paste together all the semiconductor substrates on surfaces on their front surface sides (face-to-face). In a case where three layers of semiconductor substrates are stacked one on another aimlessly, there is a possibility that a structure that electrically connects the semiconductor substrates with each other inevitably increases the chip sizes, inhibits miniaturization of the area size per pixel, and so on.
On the other hand, in the present embodiment, sensor pixels 12 and read circuits 22 are formed in different substrates (the first substrate 10 and the second substrate 20). Thereby, as compared with a case where sensor pixels 12 and read circuits 22 are formed in the same substrate, the area sizes of the sensor pixels 12 and the read circuits 22 can be expanded. As a result, it is possible to enhance photoelectric conversion efficiency, reduce transistor noise, and so on. In addition, the first substrate 10 having sensor pixels 12 and the second substrate 20 having read circuits 22 are electrically connected to each other by through-wires 54 provided in the interlayer dielectric film 51. Thereby, as compared with a case where the first substrate 10 and the second substrate 20 are electrically connected with each other by junctions between pad electrodes or through-wires (e.g., TSVs (Thorough Si Vias)) that penetrate the semiconductor substrates, it is possible to further reduce the chip sizes. In addition, further miniaturization of the area size per pixel enables a higher resolution. In addition, in a case where chip sizes similar to conventional chip sizes are adopted, the formation region of sensor pixels 12 can be expanded. In addition, in the present embodiment, read circuits 22 and logic circuits 32 are formed in different substrates (the second substrate 20 and the third substrate 30). Thereby, as compared with a case where read circuits 22 and logic circuits 32 are formed in the same substrate, the area sizes of the read circuits 22 and the logic circuits 32 can be expanded. In addition, because the area sizes of read circuits 22 and logic circuits 32 are not constrained by element separating sections 43, noise characteristics can be enhanced. In addition, in the present embodiment, the second substrate 20 and the third substrate 30 are electrically connected with each other by junctions between the pad electrodes 58 and 64. Here, because read circuits 22 are formed in the second substrate 20, and logic circuits 32 are formed in the third substrate 30, as compared with a structure for electrically connecting the first substrate 10 and the second substrate 20 with each other, a structure for electrically connecting the second substrate 20 and the third substrate 30 with each other can be formed with a layout which is free in terms of arrangement, the number of contacts for connection and the like. Accordingly, junctions between pad electrodes 58 and 64 can be used for electrical connection between the second substrate 20 and the third substrate 30. In such a manner, in the present embodiment, electrical connection between substrates are formed according to the degree of integration of the substrates. Thereby, a structure that electrically connects substrates will not inevitably necessitate an increase of the chip sizes, inhibit miniaturization of the area size per pixel, and so on. As a result, it is possible to provide the image pickup apparatus 1 having a triple-layer structure that will not inhibit miniaturization of the area size per pixel with chip sizes equivalent to conventional chip sizes.
In addition, in the present embodiment, sensor pixels 12 having photodiodes PD, transfer transistors TR and floating diffusions FD are formed in the first substrate 10, and read circuits 22 having reset transistors RST, amplification transistors AMP and selection transistors SEL are formed in the second substrate 20. Thereby, as compared with a case where sensor pixels 12 and read circuits 22 are formed in the same substrate, the area sizes of the sensor pixels 12 and the read circuits 22 can be expanded. As a result, even in a case where junctions between pad electrodes 58 and 64 are used for electrical connection between the second substrate 20 and the third substrate 30, the chip sizes will not increase, miniaturization of the area size per pixel will not be inhibited, and so on. As a result, it is possible to provide the image pickup apparatus 1 having a triple-layer structure that will not inhibit miniaturization of the area size per pixel with chip sizes equivalent to conventional chip sizes. Specifically, because fewer transistors are provided in the first substrate 10, particularly the area sizes of photodiodes PD of sensor pixels 12 can be expanded. Thereby, the saturation signal charge amount in photoelectric conversion can be increased, and the photoelectric conversion efficiency can be enhanced. In the second substrate 20, the degree of freedom of the layout of transistors in read circuits 22 can be ensured. In addition, because the area sizes of transistors can be expanded, particularly by expanding the area sizes of amplification transistors AMP, noise that influences pixel signals can be reduced. Even in a case where junctions between pad electrodes 58 and 64 are used for electrical connection between the second substrate 20 and the third substrate 30, the chip sizes will not increase, miniaturization of the area size per pixel will not be inhibited, and so on. As a result, it is possible to provide the image pickup apparatus 1 having a triple-layer structure that will not inhibit miniaturization of the area size per pixel with chip sizes equivalent to conventional chip sizes.
In addition, in the present embodiment, the second substrate 20 is pasted onto the first substrate 10 with the backside of the semiconductor substrate 21 facing the front surface side of the semiconductor substrate 11, and the third substrate 30 is pasted onto the second substrate 20 with the front surface side of the semiconductor substrate 31 facing the front surface side of the semiconductor substrate 21. Thereby, by using through-wires 54 for electrical connection between the first substrate 10 and the second substrate 20, and using junctions between pad electrodes 58 and 64 for electrical connection between the second substrate 20 and the third substrate 30, it is possible to provide the image pickup apparatus 1 having a triple-layer structure that will not inhibit miniaturization of the area size per pixel, with chip sizes equivalent to conventional chip sizes.
In addition, in the present embodiment, the cross-sectional area size of a through-wire 54 is smaller than the cross-sectional area size of a location of a junction between pad electrodes 58 and 64. Thereby, it is possible to provide the image pickup apparatus 1 having a triple-layer structure that will not inhibit miniaturization of the area size per pixel with chip sizes equivalent to conventional chip sizes.
In addition, the logic circuit 32 of the present embodiment has an impurity diffusion region contacting source electrodes and drain electrodes, and the front surface of the impurity diffusion region has low resistance regions including a silicide such as CoSi2 or NiSi formed by using the salicide (Self Aligned Silicide) process. The low resistance regions including a silicide include a compound of a metal and a material of a semiconductor substrate. Here, the logic circuits 32 are provided in the third substrate 30. Accordingly, the logic circuits 32 can be formed by a process different from processes for forming sensor pixels 12 and read circuits 22. As a result, when sensor pixels 12 and read circuits 22 are formed, a high-temperature process such as thermal oxidation can be used. In addition, a silicide, which is a less heat-resistant material, can also be used for logic circuits 32. Accordingly, in a case where low resistance regions including a silicide are provided on the front surface of the impurity diffusion region contacting the source electrodes and the drain electrodes of logic circuits 32, the contact resistance can be lowered; as a result, the speed of calculation at the logic circuits 32 can be increased.
In addition, in the present embodiment, the first substrate 10 is provided with element separating sections 43 that separate sensor pixels 12 from each other. However, in the present embodiment, sensor pixels 12 having photodiodes PD, transfer transistors TR and floating diffusions FD are formed in the first substrate 10, and read circuits 22 having reset transistors RST, amplification transistors AMP and selection transistors SEL are formed in the second substrate 20. Thereby, even in a case where the sizes of areas surrounded by element separating sections 43 become smaller due to miniaturization of the area size per pixel, the area sizes of sensor pixels 12 and read circuits 22 can be expanded. As a result, even in a case where element separating sections 43 are used, the chip sizes will not increase, miniaturization of the area size per pixel will not be inhibited, and so on. Accordingly, it is possible to provide the image pickup apparatus 1 having a triple-layer structure that will not inhibit miniaturization of the area size per pixel with chip sizes equivalent to conventional chip sizes.
In addition, in the present embodiment, element separating sections 43 penetrate the semiconductor substrate 11. Thereby, even in a case where the distances between sensor pixels 12 become shorter due to miniaturization of the area size per pixel, signal crosstalk between adjacent sensor pixels 12 can be suppressed, and resolution deterioration on a reproduced image and image quality deterioration due to color mixing can be suppressed.
In addition, in the present embodiment, the stack including the first substrate 10 and the second substrate 20 has three through-wires 54, 47 and 48 for each sensor pixel 12. Each through-wire 54 is electrically connected to the gate (transfer gate TG) of a transfer transistor TR, each through-wire 47 is electrically connected to a p well layer 42 of the semiconductor substrate 11, and each through-wire 48 is electrically connected to a floating diffusion FD. That is, the number of through-wires 54, 47 and 48 is larger than the number of sensor pixels 12 included in the first substrate 10. However, in the present embodiment, through-wires 54 with small cross-sectional area sizes are used for electrical connection between the first substrate 10 and the second substrate 20. Thereby, the chip sizes can be reduced further, and also the area size per pixel in the first substrate 10 can be miniaturized further. As a result, it is possible to provide the image pickup apparatus 1 having a triple-layer structure that will not inhibit miniaturization of the area size per pixel with chip sizes equivalent to conventional chip sizes.
Hereinafter, modification examples of the image pickup apparatus 1 according to the embodiment described above are explained. Note that in the following modification examples, configurations which are the same as those in the embodiment described above are given identical reference characters.
As depicted in
The insulation layer 53 includes plural blocks extending in first direction V1. The semiconductor substrate 21 includes plural island-like blocks 21A that extend in first direction V1, and are arranged next to each other in second direction V2 orthogonal to first direction V1 with insulation layers 53 being interposed therebetween. For example, each block 21A is provided with reset transistors RST, amplification transistors AMP and selection transistors SEL. For example, each read circuit 22 shared by four sensor pixels 12 is not arranged to directly face the four sensor pixels 12, but is arranged by being displaced in second direction V2.
In
In
In the present modification example, for example, each read circuit 22 shared by four sensor pixels 12 is not arranged to directly face the four sensor pixels 12, but is arranged by being displaced in second direction V2 from a position directly facing the four sensor pixels 12. In a case where such arrangement is adopted, wires 25 can be made short, or wires 25 can be omitted, and the source of an amplification transistor AMP and the drain of a selection transistor SEL can be formed by a common impurity region. As a result, it is possible to reduce the sizes of read circuits 22, to increase the sizes of other locations in the read circuits 22, and so on.
In the present modification example, the semiconductor substrate 21 includes plural island-like blocks 21A arranged next to each other in first direction V1 and second direction V2 with insulation layers 53 being interposed therebetween. For example, each block 21A is provided with one set of a reset transistor RST, an amplification transistor AMP and a selection transistor SEL. In a case where such arrangement is adopted, crosstalk between read circuits 22 that are adjacent to each other can be suppressed by insulation layers 53, and resolution deterioration on a reproduced image and image quality deterioration due to color mixing can be suppressed.
In the present modification example, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and each floating diffusion FD is shared by four sensor pixels 12. Accordingly, in the present modification example, one through-wire 54 is provided for each set of four sensor pixels 12.
In plural sensor pixels 12 arranged in a matrix, four sensor pixels 12 corresponding to a region obtained by displacing a unit region corresponding to four sensor pixels 12 sharing one floating diffusion FD in first direction V1 by an amount corresponding to one sensor pixel 12 are referred to as four sensor pixels 12A for convenience. At this time, in the present modification example, each through-wire 47 is shared by a set of four sensor pixels 12A in the first substrate 10. Accordingly, in the present modification example, one through-wire 47 is provided for each set of four sensor pixels 12A.
In the present modification example, the first substrate 10 has element separating sections 43 that separate photodiodes PD and transfer transistors TR for each sensor pixel 12. As seen in the normal direction of the semiconductor substrate 11, the element separating sections 43 do not completely surround sensor pixels 12, and have gaps (regions where the element separating sections 43 are not formed) near floating diffusions FD (through-wires 54) and near through-wires 47. Then, the gaps allow sharing of one through-wire 54 by four sensor pixels 12 and sharing of one through-wire 47 by four sensor pixels 12A. In the present modification example, the second substrate 20 has a read circuit 22 for each set of four sensor pixels 12 sharing a floating diffusion FD.
As depicted in
In this system configuration, on the basis of a master clock MCK, the system control circuit 36 generates clock signals, control signals and the like that function as reference signals for operation of the vertical driving circuit 33, the column signal processing circuit 34, the reference voltage supply section 38, the horizontal driving circuit 35 and the like, and give them to the vertical driving circuit 33, the column signal processing circuit 34, the reference voltage supply section 38, the horizontal driving circuit 35 and the like.
In addition, the vertical driving circuit 33 is formed in the first substrate 10 along with the sensor pixels 12 in the pixel region 13, and is further formed also in the second substrate 20 where read circuits 22 are formed. The column signal processing circuit 34, the reference voltage supply section 38, the horizontal driving circuit 35, the horizontal output line 37 and the system control circuit 36 are formed in the third substrate 30.
As the sensor pixels 12, although not depicted in the figure here, for example, ones with a configuration having, in addition to photodiodes PD, transfer transistors TR that transfer electric charge obtained by photoelectric conversion at the photodiodes PD to floating diffusions FD can be used. In addition, as read circuits 22, although not depicted in the figure here, for example, ones each with a three-transistor configuration having a reset transistor RST that controls the potential of a floating diffusion FD, an amplification transistor AMP that outputs a signal according to the potential of the floating diffusion FD and a selection transistor SEL for performing pixel selection can be used.
In the pixel region 13, sensor pixels 12 are arranged two-dimensionally. In this pixel arrangement including m rows and n columns, a pixel driving line 23 is placed for each row, and a vertical signal line 24 is placed for each column. One end of each of the plural pixel driving lines 23 is connected to each output terminal of the vertical driving circuit 33 corresponding to one row. The vertical driving circuit 33 includes a shift register or the like, and controls row addressing and row scanning of the pixel region 13 via the plural pixel driving lines 23.
For example, the column signal processing circuit 34 has ADCs (analog-digital conversion circuits) 34-1 to 34-m each provided for one pixel column in the pixel region 13, that is, for one vertical signal line 24, converts analog signals output from each column of sensor pixels 12 in the pixel region 13 into digital signals, and outputs the digital signals.
For example, the reference voltage supply section 38 has a DAC (digital-analog conversion circuit) 38A as means for generating a reference voltage Vref with what is generally called a ramp (RAMP) waveform whose level changes gradually over time. Note that means for generating the reference voltage Vref with a ramp waveform is not limited to the DAC 38A.
Under the control of a control signal CS1 given from the system control circuit 36, the DAC 38A generates the reference voltage Vref with a ramp waveform on the basis of a clock CK given from the system control circuit 36, and supplies the reference voltage Vref to the ADCs 34-1 to 34-m of a column processing section 15.
Note that each of the ADCs 34-1 to 34-m is configured to be able to selectively perform AD conversion operation corresponding to each operation mode of a normal frame rate mode in a progressive scanning format in which information of all sensor pixels 12 is read out, and a high frame rate mode in which light-exposure time of sensor pixels 12 is set to 1/N, and the frame rate is made N times high, for example, twice high, as compared with that at the time of the normal frame rate mode. This switching of the operation mode is executed under the control of control signals CS2 and CS3 given from the system control circuit 36. In addition, from an external system controller (not depicted), the system control circuit 36 is given instruction information for switching the operation mode between the normal frame rate mode and the high frame rate mode.
The ADCs 34-1 to 34-m all have the same configuration, and here the ADC 34-m is explained as an example. The ADC 34-m has a comparator 34A, an up/down counter (denoted as a U/DCNT in the
The comparator 34A compares a signal voltage Vx of a vertical signal line 24 according to a signal output from each sensor pixel 12 in the n-th column in the pixel region 13, and the reference voltage Vref with a ramp waveform supplied from the reference voltage supply section 38. For example, when the reference voltage Vref is higher than the signal voltage Vx, output Vco is at the “H” level, and when the reference voltage Vref is equal to or lower than the signal voltage Vx, output Vco is at the “L” level.
The up/down counter 34B is an asynchronous counter. Under the control of the control signal CS2 given from the system control circuit 36, the up/down counter 34B is given the clock CK from the system control circuit 36 simultaneously with a DAC 18A, and counts down (DOWN) or counts up (UP) in synchronization with the clock CK to thereby measure a comparison period from the start of the comparison operation at the comparator 34A to the end of the comparison operation.
Specifically, in the normal frame rate mode, in operation of reading out signals from one sensor pixel 12, down-counting is performed at the time of the first read operation to thereby measure comparison time at the time of the first read operation, and up-counting is performed at the time of the second read operation to thereby measure comparison time at the time of the second read operation.
On the other hand, in the high frame rate mode, a count result of a sensor pixel 12 in a row is retained as is. Subsequently, about a sensor pixel 12 in the next row, down-counting from the previous count result is performed at the time of the first read operation to thereby measure comparison time at the time of the first read operation, and up-counting is performed at the time of the second read operation to thereby measure comparison time at the time of the second read operation.
Under the control of the control signal CS3 given from the system control circuit 36, the transfer switch 34C in the normal frame rate mode is turned on (closed) at a time point when counting operation of the up/down counter 34B about a sensor pixel 12 in a row has been completed, and transfers the count result of the up/down counter 34B to the memory apparatus 34D.
On the other hand, for example, in the high frame rate mode in which N=2, the transfer switch 34C remains turned off (opened) at a time point when counting operation of the up/down counter 34B about a sensor pixel 12 in a row has been completed. Subsequently, the transfer switch 34C is turned on at a time point when counting operation of the up/down counter 34B about a sensor pixel 12 in the next row has been completed, and transfers, to the memory apparatus 34D, the count result about the two vertical pixels of the up/down counter 34B.
In such a manner, analog signals supplied from each column of sensor pixels 12 in the pixel region 13 through a vertical signal line 24 are converted into N-bit digital signals by operation of each of comparators 34A and up/down counters 34B in the ADCs 34-1 to 34-m, and the digital signals are stored on memory apparatuses 34D.
The horizontal driving circuit 35 includes a shift register or the like, and controls column addressing and column scanning of the ADCs 34-1 to 34-m in the column signal processing circuit 34. Under the control of the horizontal driving circuit 35, an AD-converted N-bit digital signal that is obtained at each of the ADCs 34-1 to 34-m is sequentially read out to the horizontal output line 37, and is output as image pickup data through the horizontal output line 37.
Note that although not depicted particularly because they are not directly related to the present technology, circuits that perform various types of signal processing on image pickup data output through the horizontal output line 37 and the like can also be provided, in addition to the constituent elements described above.
In the image pickup apparatus 1 having the column parallel ADCs mounted thereon according to the present modification example with the configuration described above, a count result of the up/down counter 34B can be transferred selectively to the memory apparatus 34D via the transfer switch 34C, and so it is possible to independently control counting operation of the up/down counter 34B and operation of reading the count result of the up/down counter 34B out to the horizontal output line 37.
In the embodiment described above and modification examples thereof, conductivity types may be reverse. For example, in the description of the embodiment described above and modification examples thereof, p type may be read as meaning n type, and n type may be read as meaning p type. Even in a case where such arrangement is adopted, advantages similar to those of the embodiment described above and modification examples thereof can be attained.
For example, the image pickup system 2 is electronic equipment such as an image pickup apparatus such as a digital still camera or a video camera, or a mobile terminal apparatus such as a smartphone or a tablet-type terminal. For example, the image pickup system 2 includes the image pickup apparatus 1 according to the embodiment described above and modification examples thereof, a DSP circuit 141, a frame memory 142, a display section 143, a storage section 144, an operation section 145 and a power supply section 146. In the image pickup system 2, the image pickup apparatus 1 according to the embodiment described above and modification examples thereof, the DSP circuit 141, the frame memory 142, the display section 143, the storage section 144, the operation section 145 and the power supply section 146 are connected with each other via a bus line 147.
The image pickup apparatus 1 according to the embodiment described above and modification examples thereof outputs image data according to an incident light. The DSP circuit 141 is a signal processing circuit that processes signals (image data) output from the image pickup apparatus 1 according to the embodiment described above and modification examples thereof. The frame memory 142 temporarily retains framewise image data processed by the DSP circuit 141. For example, the display section 143 includes a panel-type display apparatus such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays moving images or still images picked up by the image pickup apparatus 1 according to the embodiment described above and modification examples thereof. The storage section 144 records image data of moving images or still images picked up by the image pickup apparatus 1 according to the embodiment described above and modification examples thereof on a recording medium such as a semiconductor memory or a hard disk. According to operation by a user, the operation section 145 gives an operation command for various types of functions that the image pickup system 2 has. As appropriate, the power supply section 146 supplies the image pickup apparatus 1 according to the embodiment described above and modification examples thereof, the DSP circuit 141, the frame memory 142, the display section 143, the storage section 144 and the operation section 145 with various types of power supplies to be operation power supplies of those supply targets.
Next, an image pickup procedure at the image pickup system 2 is explained.
The image pickup apparatus 1 outputs image data obtained by the image pickup to the DSP circuit 141. Here, the image data means data corresponding to all pixels of pixel signals generated on the basis of electric charge temporarily retained in floating diffusions FD. On the basis of the image data input from the image pickup apparatus 1, the DSP circuit 141 performs predetermined signal processing (e.g., a noise reduction process, etc.) (Step S104). The DSP circuit 141 makes the frame memory 142 retain the image data on which the predetermined signal processing has been performed, and the frame memory 142 causes the image data to be stored on the storage section 144 (Step S105). In such a manner, image pickup at the image pickup system 2 is performed.
In the present application example, the image pickup apparatus 1 according to the embodiment described above and modification examples thereof is applied to the image pickup system 2. Thereby, the image pickup apparatus 1 with a smaller size or higher resolution can be realized, and so the image pickup system 2 with a smaller size or higher resolution can be provided.
As more specific configuration of a semiconductor apparatus according to the first embodiment of the present technology, a backside illumination CMOS image sensor (solid-state image pickup apparatus) is illustrated. As depicted in
The pixel region 1001 has plural pixels (unit cells) 1002 arrayed in a two-dimensional matrix. Each of the plural pixels 1002 has a photoelectric converting section and plural pixel transistors (cell circuits). As the plural pixel transistors, for example, four transistors which are a transfer transistor, a reset transistor, a selection transistor and an amplification transistor can be adopted.
For example, the vertical driving circuit 1003 includes a shift register. The vertical driving circuit 1003 sequentially selects pixel driving wires 1008a, supplies the selected pixel driving wires 1008a with pulses for driving the pixels 1002, and drives each row of the pixels 1002. That is, the vertical driving circuit 1003 selectively scans each row of the pixels 1002 in the pixel region 1001 sequentially vertically, and supplies, through vertical signal lines 1008b, the column signal processing circuits 1004 with output signals (pixel signals) from the pixels based on signal charge generated by photoelectric converting sections of the pixels 1002.
For example, each column signal processing circuit 1004 is arranged for one column of pixels 1002, and performs signal processing such as noise removal on signals output from one row of pixels 1002 for each pixel column. For example, the column signal processing circuit 1004 performs signal processing such as correlated double sampling (CDS) for removing fixed pattern noise unique to pixels, or analog/digital (AD) conversion.
For example, the horizontal driving circuit 1005 includes a shift register. The horizontal driving circuit 1005 sequentially outputs horizontal scanning pulses to the column signal processing circuits 1004, sequentially selects the column signal processing circuits 1004, and causes the selected column signal processing circuits 1004 to output, to a horizontal signal line 1009, pixel signals on which the signal processing has been performed. The output circuit 1006 performs signal processing on a pixel signal supplied sequentially from each of the column signal processing circuits 1004 through the horizontal signal line 1009, and outputs the pixel signal.
On the basis of vertical synchronizing signals, horizontal synchronization signals and master clock signals, the control circuit 1007 generates clock signals and control signals to function as reference signals for operation of the vertical driving circuit 1003, the column signal processing circuits 1004, the horizontal driving circuit 1005 and the like. Then, the control circuit 1007 outputs the generated clock signals and control signals to the vertical driving circuit 1003, the column signal processing circuits 1004, the horizontal driving circuit 1005 and the like.
The semiconductor apparatus according to the first embodiment of the present technology has a three-dimensional structure formed by stacking the configuration depicted in
The first substrate 1101 includes a photoelectric converting section formation region 1101a in which photoelectric converting sections that perform photoelectric conversion of incident light are formed. In addition to the photoelectric converting sections, at least some of pixel transistors such as transfer transistors that control photoelectrically converted signal charge may be formed in the photoelectric converting section formation region 1101a.
The second substrate 1102 includes a pixel transistor formation region 1102a in which at least some of pixel transistors that control photoelectrically converted signal charge are formed. For example, at least some of pixel transistors such as reset transistors, selection transistors or amplification transistors may be formed in the pixel transistor formation region 1102a. Note that, for example, only amplification transistors in pixel transistors may be provided in the second substrate 1102, and either of or both reset transistors and selection transistors may be provided in the third substrate 1103.
The third substrate 1103 includes a logic circuit formation region 1103a in which logic circuits to execute signal processing are formed. For example, as the logic circuits, the logic circuit formation region 1103a may include at least some of the vertical driving circuit 1003, the column signal processing circuits 1004, the horizontal driving circuit 1005, the output circuit 1006 and the control circuit 1007 depicted in
Note that although
As depicted in
At the time of operation of the semiconductor apparatus according to the first embodiment, signal charge generated by the photodiode PD is accumulated in the electric charge accumulation region FD via the transfer transistor T1, and the signal charge accumulated in the electric charge accumulation region FD is read out and applied to the gate of the amplification transistor T3. The gate of the selection transistor 14 is given a horizontal line selection control signal from a vertical shift register. By making the selection control signal a high (H) level signal, the selection transistor T4 becomes conductive, and a current corresponding to the potential of the electric charge accumulation region FD amplified at the amplification transistor T3 flows to the vertical signal line VSL. In addition, by making a reset control signal to be applied to the gate of the reset transistor T2 a high (H) level signal, the reset transistor T2 becomes conductive, and signal charge accumulated in the electric charge accumulation region FD is reset.
The first substrate 1101 includes: a sensor layer 1010; a first element layer 1020 that is arranged on the sensor layer 1010, and includes a first active element 1021; a first wiring layer 1030 arranged on the first element layer 1020; and a shield layer (shield layer) 1040 arranged on the first wiring layer 1030. The second substrate 1102 includes: a second element layer 1050 that is arranged on the shield layer 1040 via an interlayer dielectric film 1042, and includes second active elements 1052, 1053, 1054 and 1055; and a second wiring layer 1060 arranged on the second element layer 1050. The third substrate 1103 includes: a third wiring layer 1070 arranged on the second wiring layer 1060; and a third element layer 1080 that is arranged on the third wiring layer 1070, and includes third active elements 1082 and 1083.
The sensor layer 1010 has plural photoelectric converting sections 1011a, 1011b and 1011c formed in a semiconductor substrate (Si substrate) 1011 including silicon (Si) or the like. Each of the photoelectric converting sections 1011a, 1011b and 1011c includes a photodiode. The photodiode includes a pn junction between a p-type well region (not depicted) formed in the Si substrate 1011 and an n-type electric charge generation region (not depicted).
The adjacent photoelectric converting sections 1011a, 1011b and 1011c are element-separated by element separating sections 1012. For example, the element separating sections 1012 are formed like a grid when seen from below in
A flattening film 1091, a color filter 1092, a microlens 1093, wires (not depicted) and the like are arranged on the backside of the sensor layer 1010. The flattening film 1091 flattens the backsides of the photoelectric converting sections 1011a, 1011b and 1011c. The microlens 1093 condenses incident light entering the photoelectric converting sections 1011a, 1011b and 1011c. The color filter 1092 color-separates incident light entering the photoelectric converting sections 1011a, 1011b and 1011c.
For example, the first element layer 1020 is included in a first cell circuit that independently takes out electric signals generated by photoelectric conversion of the incident light by the plural photoelectric converting sections 1011a, 1011b and 1011c. The first element layer 1020 includes the first active element 1021 that is formed on the front surface of the Si substrate 1011, and that is included in the first cell circuit. For example, the first active element 1021 can include the transfer transistor T1 depicted in
For convenience,
The first wiring layer 1030 is electrically connected with the first element layer 1020. The first wiring layer 1030 has wires 1031, 1032, 1033 and 1034 embedded in an interlayer dielectric film 1035. As a material of the wires 1031, 1032, 1033 and 1034, for example, a metal such as copper (Cu) can be used, and, as a material of the interlayer dielectric film 1035, a silicon oxide film (SiO2 film) or the like can be used.
The shield layer 1040 has a function as a thermal, optical and electromagnetic shield between the first element layer 1020 arranged below the shield layer 1040 and the second element layer 1050 arranged above the shield layer 1040. The shield layer 1040 may have a function of blocking transmission of infrared rays, and may have a function of forming capacitance to prevent surges.
As a material of the shield layer 1040, for example, a material including an electrically conductive material such as a metal such as copper (Cu), aluminum (Al), gold (Au), silver (Ag) or tungsten (W), or an alloy of any of these can be used. In addition, if necessary, a ferromagnetic material such as ferrite can be used as a material of the shield layer 1040. A material of the shield layer 1040 may be another electrically conductive material as long as it can function as a thermal, optical and electromagnetic shield.
For example, the thickness of the shield layer 1040 is approximately equal to or larger than 300 nm but equal to or smaller than 500 nm, but may be smaller than 300 nm or may be larger than 500 nm. Although not depicted in the figure, the shield layer 1040 is connected to a ground potential via the Si substrate 1011. While
For example, the second element layer 1050 is included in a second cell circuit connected to the first element layer 1020, corresponding to each of plural pixels 1002. The second element layer 1050 has the second active elements 1052, 1053, 1054 and 1055 that are formed in a semiconductor substrate (Si substrate) 1051 including Si, and are included in the second cell circuit. For example, each of the second active elements 1052, 1053, 1054 and 1055 can include at least any of the reset transistor T2, the amplification transistor T3 and the selection transistor T4 depicted in
The second wiring layer 1060 is electrically connected with the second element layer 1050. The second wiring layer 1060 has wires 1061, 1062, 1063 and 1064 embedded in an interlayer dielectric film 1065. As a material of the wires 1061, 1062, 1063 and 1064, for example, a metal such as copper (Cu) can be used, and, as a material of the interlayer dielectric film 1065, a silicon oxide film (SiO2 film) or the like can be used.
The wire 1061 which is at the lowermost layer of the second wiring layer 1060 is connected with the upper end of the connection wire 1066. The connection wire 1066 extends vertically to penetrate the second element layer 1050, the shield layer 1040 and the first wiring layer 1030. The connection wire 1066 is provided to penetrate the opening 1041a of the shield layer 1040. The lower end of the connection wire 1066 is connected to a contact section (not depicted) that is included in the first element layer 1020, and that is provided at an upper section of the Si substrate 1011. For example, the connection wire 1066 may electrically connect the gate electrode of an amplification transistor including the second active element 1053 electrically connected via the wire 1061, and an electric charge accumulation region that is included in the first element layer 1020, and that is formed at an upper section of the Si substrate 1011.
In addition, the wire 1062 which is at the lowermost layer of the second wiring layer 1060 is connected with the upper end of the connection wire 1067. The connection wire 1067 extends vertically to penetrate the second element layer 1050 and the shield layer 1040. The connection wire 1067 is provided to penetrate the opening 1041b of the shield layer 1040. The lower end of the connection wire 1067 is connected to the wire 1034 of the first wiring layer 1030.
The third wiring layer 1070 has wires 1071, 1072, 1073 and 1074 embedded in an interlayer dielectric film 1075. As a material of the wires 1071, 1072, 1073 and 1074, for example, a metal such as copper (Cu) can be used.
The third element layer 1080 has the third active elements 1082 and 1083 that are formed in a semiconductor substrate (Si substrate) 1081 including Si, and are included in a logic circuit. Each of the third active elements 1082 and 1083 can include a MOS transistor, but more typically may be a MIS transistor. For convenience,
Because the semiconductor apparatus according to the first embodiment has the shield layer 1040 between the first element layer 1020 formed in the first substrate 1101 and the second element layer 1050 formed in the second substrate 1102, the shield layer 1040 functions as an optical, electromagnetic and thermal shield between the first element layer 1020 arranged below the shield layer 1040 and the second element layer 1050 arranged above the shield layer 1040. Because of this, the mutual influence of noise and heat propagated between the first active element 1021 included in the first element layer 1020 and the second active elements 1052, 1053, 1054 and 1055 included in the second element layer 1050 is excluded, and noise, operation errors and the like that affect element characteristics can be suppressed. As a result, deterioration of element characteristics of the first active element 1021 included in the first element layer 1020 and the second active elements 1052, 1053, 1054 and 1055 included in the second element layer 1050 can be suppressed.
Next, an example of a semiconductor apparatus manufacturing method according to the first embodiment is explained with reference to
First, a photoresist film is applied onto the Si substrate 1011, and patterning of the photoresist film is performed by using a photolithography technology. Using the photoresist film on which the patterning has been performed as an etching mask, deep groove sections (trenches) having vertical side walls are formed by dry etching such as reactive ion etching (RIE). Thereafter, the photoresist film is removed, and the Si substrate 1011 is cleaned. Then, by an atomic layer deposition (ALD) method, a chemical vapor deposition (CVD) method or the like, insulating films or structures formed by stacking an insulating film and a metal film one on another are embedded inside the groove sections. Thereafter, by etch-back, chemical mechanical polishing (CMP) or the like, the insulating films and the metal films on the Si substrate 1011 are removed. As a result, as depicted in
Next, by a photolithography technology, ion implantation, thermal treatment or the like, p-type well regions and n-type electric charge generation regions to be included in photodiodes are formed at the upper section of the Si substrate 1011, and the photoelectric converting sections 1011a, 1011b and 1011c are formed. In addition, diffusion layers such as n-type electric charge accumulation regions are also formed at the upper section of the Si substrate 1011. Further, by a CVD method, a lithography technology, etching or the like, a gate insulating film and a gate electrode of the first active element 1021 are formed. As a result, as depicted in
Next, by a dual damascene method or the like, as depicted in
Next, by a CVD method or the like, the shield layer 1040 including a metal film is deposited on the first wiring layer 1030. Then, a photoresist film is applied onto the shield layer 1040, and patterning of the photoresist film is performed by using a photolithography technology. Using the photoresist film on which the patterning has been performed as an etching mask, a part of the shield layer 1040 is selectively removed by dry etching such as RIE. Thereafter, the photoresist film is removed. As a result, as depicted in
On the other hand, as depicted in
Next, by using an adhesive or the like, a support substrate 1057 is adhered onto the Si substrate 1051 on the side of a surface (front surface) where the second active elements 1052, 1053, 1054 and 1055 are formed. Then, by polishing, by CMP or the like, a surface (backside) opposite to the surface of the Si substrate 1051 where the second active elements 1052, 1053, 1054 and 1055 are formed, as depicted in
Next, the surface (backside) opposite to the surface of the Si substrate 1051 where the second active elements 1052, 1053, 1054 and 1055 are formed depicted in
Next, by dry etching such as a photoresist technology or RIE, or the like, a groove section that penetrates the second element layer 1050, the shield layer 1040 and the first wiring layer 1030 makes the front surface of the Si substrate 1011 exposed, and is for forming the connection wire 1066, and a groove section that penetrates the second element layer 1050 and the shield layer 1040 makes the front surface of the wire 1034 exposed, and is for forming the connection wire 1067 are formed. Then, by a CVD method or the like, a metal film is deposited such that it fills the groove sections, and by etch-back, CMP or the like, the metal film on the interlayer dielectric film 1056 is removed. As a result, as depicted in
The connection wires 1066 and 1067 are formed to penetrate the openings 1041a and 1041b of the shield layer 1040. In addition, insulation structures are formed in the Si substrate 1051 of the second element layer 1050 such that they surround the outer circumferential surfaces of the connection wires 1066 and 1067. Note that in a case where insulation layers are formed in advance at portions of the Si substrate 1051 of the second element layer 1050 that are penetrated by the connection wires 1066 and 1067, insulation structures do not have to be formed in the Si substrate 1051.
Next, by a dual damascene method or the like, as depicted in
On the other hand, as depicted in
Next, the side of the third wiring layer 1070 of the third substrate 1103 depicted in
Next, by CMP or the like, the Si substrate 1011 is polished from the backside to thereby make the element separating section 1012 exposed, and separate the photoelectric converting sections 1011a, 1011b and 1011c as elements. Further, wires (not depicted), the flattening film 1091, the color filter 1092, the microlens 1093 and the like are formed on the backside of the Si substrate 1011. As a result, the semiconductor apparatus according to the first embodiment depicted in
According to the semiconductor apparatus manufacturing method according to the first embodiment, the shield layer 1040 formed between the first element layer 1020 and the second element layer 1050 functions an optical, electromagnetic and thermal shield between the first element layer 1020 arranged below the shield layer 1040 and the second element layer 1050 arranged above the shield layer 1040. Because of this, mutual propagation of noise and heat between the first element layer 1020 and the second element layer 1050 can be suppressed. Because of this, it is possible to manufacture a semiconductor apparatus that makes it possible to suppress deterioration of element characteristics of the first active element 1021 included in the first element layer 1020 and the second active elements 1052, 1053, 1054 and 1055 included in the second element layer 1050.
As depicted in
Note that the flattening film, the color filter, the microlens and the like on the backside of the Si substrate 1011 are not depicted in
In the semiconductor apparatus according to the second embodiment of the present technology, as a part of the shield layer 1040, sheath sections 1043 and 1044 are provided around the openings 1041a and 1041b of the shield layer 1040, respectively. The sheath sections 1043 and 1044 are electrically connected with the shield layer 1040. As a material of the sheath sections 1043 and 1044, similarly to the shield layer 1040, for example, a material including an electrically conductive material such as a metal such as copper (Cu), aluminum (Al), gold (Au), silver (Ag) or tungsten (W), or an alloy of any of these can be used. As a material of the sheath sections 1043 and 1044, a material which is the same as a material of the shield layer 1040 may be used, or a different material may be used.
The sheath section 1043 extends vertically to surround the outer circumferential surface of the connection wire 1066. The upper end of the sheath section 1043 is positioned near the wire 1061 of the second wiring layer 1060. The lower end of the sheath section 1043 is positioned near the Si substrate 1011. Insulation structures are formed between the sheath section 1043 and the connection wire 1066, and between the sheath section 1043 and the second element layer 1050.
The sheath section 1044 extends vertically to surround the outer circumferential surface of the connection wire 1067. The upper end of the sheath section 1044 is positioned near the wire 1062 of the second wiring layer 1060. The lower end of the sheath section 1044 is positioned near the wire 1034 of the first wiring layer 1030. Insulation structures are formed between the sheath section 1044 and the connection wire 1067, and between the sheath section 1044 and the second element layer 1050.
When the semiconductor apparatus according to the second embodiment of the present technology is manufactured, for example, the second element layer 1050 is formed, and then, by dry etching such as a CVD method or RIE, or the like, metal films to be the sheath sections 1043 and 1044, interlayer dielectric films and the connection wires 1066 and 1067 are sequentially embedded in groove sections penetrating the second element layer 1050, the shield layer 1040 and the like, so that the connection wires 1066 and 1067 and the sheath sections 1043 and 1044 can be formed. The other manufacturing steps of the semiconductor apparatus according to the second embodiment of the present technology are similar to manufacturing steps of the semiconductor apparatus according to the first embodiment of the present technology, and so overlapping explanations are omitted.
Similarly to the semiconductor apparatus according to the first embodiment of the present technology, because the semiconductor apparatus according to the second embodiment of the present technology has the shield layer 1040 between the first element layer 1020 formed in the first substrate 1101 and the second element layer 1050 formed in the second substrate 1102, the shield layer 1040 functions as an optical, electromagnetic and thermal shield between the first element layer 1020 arranged below the shield layer 1040 and the second element layer 1050 arranged above the shield layer 1040. Because of this, the mutual influence of noise and heat propagated between the first active element 1021 included in the first element layer 1020 and the second active elements 1052, 1053, 1054 and 1055 included in the second element layer 1050 is excluded, and noise, operation errors and the like that affect element characteristics can be suppressed. As a result, deterioration of element characteristics of the first active element 1021 included in the first element layer 1020 and the second active elements 1052, 1053, 1054 and 1055 included in the second element layer 1050 can be suppressed.
Further, because the semiconductor apparatus according to the second embodiment of the present technology includes, as a part of the shield layer 1040, the sheath sections 1043 and 1044 such that they extend along the outer circumferential surfaces of the connection wires 1066 and 1067, the connection wires 1066 and 1067 inside the sheath sections 1043 and 1044 can propagate signals stably without being influenced by capacitive coupling or the like.
A semiconductor apparatus according to a third embodiment of the present technology is explained by using
As depicted in
The electromagnetic shield layer 1302 is a layer including an electrically conductive material, and is formed to cover at least the first active elements 1221 between the first wiring layer 1230 and the interlayer dielectric film 1242. The electromagnetic shield layer 1302 has electrical conductivity to such an extent that the potential in the electromagnetic shield layer 1302 becomes constant, and has a function as an electromagnetic shield that prevents potential variations on the side of the first active elements 1221 from influencing the second active elements 1252. As a material included in the electromagnetic shield layer 1302, a metal layer or a semiconductor layer can be used, and particularly tungsten (W), titanium (Ti), titanium nitride (TiN), carbon (C) or polycrystalline silicon (Si) is used preferably in terms of prevention of diffusion of constituent atoms in latter steps. The electromagnetic shield layer 1302 is connected with wires or the like which are not depicted, a fixed potential is preferably applied to the electromagnetic shield layer 1302, and a ground potential is more preferably applied to the electromagnetic shield layer 1302.
The diffusion prevention layers 1301 and 1303 are layers including a dielectric material formed on the top and bottom surfaces of the electromagnetic shield layer 1302, and prevent atoms such as oxygen having been taken into the electromagnetic shield layer 1302 when the electromagnetic shield layer 1302 is formed from being diffused to the first wiring layer 1230 or the interlayer dielectric film 1242. The material included in the diffusion prevention layers 1301 and 1303 is not limited to any particular kind, and SiN can be used, for example.
Next, the semiconductor apparatus manufacturing method according to the present embodiment is explained by using
According to the semiconductor apparatus according to the third embodiment of the present technology, potential variations that occur when the first active elements 1221 are driven are electromagnetically blocked by the electromagnetic shield layer 1302. Thereby, it is possible to prevent substrate bias variations, and reduce noise to the second active elements 1252. In particular, it is preferred in terms of noise reduction to fix the electromagnetic shield layer 1302 to a ground potential. In addition, in the present embodiment, in a semiconductor apparatus not including photoelectric converting sections in the first substrate also, the electromagnetic shield layer 1302 provided between the first active elements 1221 and the second active elements 1252 can prevent substrate bias variations, and reduce noise.
In addition, if tungsten (W), titanium (Ti), titanium nitride (TiN), carbon (C) or polycrystalline silicon (Si) which is a high melting point material is used as a material included in the electromagnetic shield layer 1302, the electromagnetic shield layer 1302 can prevent diffusion into the first wiring layer 1230 or the interlayer dielectric film 1242 even if there is a step to be performed under a high-temperature environment such as formation of the second active elements 1252 after the first substrate and the second substrate are pasted together.
In the present first modification example also, potential variations that occur when the first active elements 1221 are driven are electromagnetically blocked by the electromagnetic shield layer 1302, and it is possible to prevent substrate bias variations, and reduce noise to the second active elements 1252.
In the stacked structure of three or more layers of substrates as in the present modification example also, potential variations that occur when each active element is driven can be electromagnetically blocked by the electromagnetic shield layer 1302 by providing the electromagnetic shield layer 1302 between active elements. Thereby, it is possible to prevent substrate bias variations, and reduce noise to the active elements.
Because the electromagnetic shield layer 1302 is formed limitedly in desired regions in the present modification example, regions inside the first wiring layer 1230 and the interlayer dielectric film 1242 where wires and connection wires can be formed can be expanded, and the degree of freedom of element design can be enhanced.
Because the electromagnetic shield layer 1302 is formed to cover positions apart from regions directly above the photoelectric converting sections in the present modification example, it becomes easier to connect wires and connection wires to the electromagnetic shield layer 1302, and apply a ground potential which is a fixed potential to the electromagnetic shield layer 1302. In addition, the electromagnetic shield layer 1302 may partially extend to be connected to a grounding wire.
Although the planar shape of the electromagnetic shield layer 1302 in the present modification example is not limited to any particular kind, the electromagnetic shield layer 1302 which is common to plural photoelectric converting sections may be formed as depicted in
Because the connection wire 1311 is formed in the thickness direction of the semiconductor apparatus, and is electrically connected to the electromagnetic shield layer 1302 in the present modification example, a fixed potential can be supplied while the area size of the electromagnetic shield layer 1302 is reduced.
A semiconductor apparatus according to a fourth embodiment of the present technology is explained by using
The light attenuation sections 1501 and 1502 are micro-sized structures provided in the insulation layer 1446, and include materials whose refractive indices are higher than the refractive index of a material included in the insulation layer 1446. The shapes of the light attenuation sections 1501 and 1502 are not limited, and
In a semiconductor apparatus typically, synchrotron radiation due to hot carrier occurs in some cases at the time of driving of read circuits 1422 and logic circuits 1432. Because the intensity of synchrotron radiation is inversely proportional to the square of the distance, noise occurs in a case where synchrotron radiation enters a photodiode PD arranged at a position closer to a region where the synchrotron radiation is generated. In the semiconductor apparatus according to the present embodiment, synchrotron radiation having entered the light attenuation sections 1501 and 1502 is attenuated inside the light attenuation sections 1501 and 1502 due to repetitive reflection. Thereby, the intensity of synchrotron radiation due to hot carrier that reaches the photodiode PD can be lowered, and noise at the photodiode PD can be reduced. The heights of the light attenuation sections 1501 and 1502 are preferably equal to or higher than 1.1 μm, and the intervals between the adjacent light attenuation sections 1501 and 1502 are preferably equal to or smaller than 0.38 μm. By making the heights of the light attenuation sections 1501 and 1502 equal to or higher than 1.1 μm, even synchrotron radiation that has entered vertically from above and is not reflected totally can be absorbed approximately 90 % while it passes through the light attenuation sections 1501 and 1502.
In addition, in a case where the insulation layer 1446 includes SiO2, and the light attenuation sections 1501 and 1502 include Si, because the refractive index of Si02 is approximately 1.48, and the refractive index of Si is approximately 3.88, the critical angle at the interfaces between the light attenuation sections 1501 and 1502 and the insulation layer 1446 is approximately 22 degrees. Thereby, the area within which light having entered the light attenuation sections 1501 and 1502 is reflected totally can be made larger, and the advantages of repetitive total reflection of light and optical absorption can be enhanced.
In addition, as depicted in
Next, a semiconductor apparatus manufacturing method according to the present embodiment is explained by using
Next, as depicted in
Next, the SOI substrate is inverted as depicted in
As depicted in
Because the semiconductor apparatus according to the fourth embodiment of the present technology includes, between the photodiode PD and the read circuit 1422, the light attenuation sections 1501 and 1502 including materials whose refractive indices are higher than the refractive index of surrounding materials, it is possible to hinder synchrotron radiation generated by hot carrier at the read circuit 1422 or the logic circuit 1432 from reaching the photodiode PD, and to reduce noise.
Because the bottom surface portions of the light attenuation sections 1521 and 1522 are formed as the projections 1521a and 1522a in the semiconductor apparatus according to the present modification example, synchrotron radiation having entered from directly above also is reflected totally at the projections 1521a and 1522a, and the synchrotron radiation can be attenuated effectively. While the conical shapes are depicted as an example of the shapes of the projections 1521a and 1522a here, it is sufficient if they are formed to have angles that allow reflection of synchrotron radiation having reached from above, and they may have shapes having inclined surfaces, micro recessed and projected shapes, mortar-like shapes or the like.
Next, a semiconductor apparatus manufacturing method according to the present modification example is explained by using
Next, the SOI substrate is inverted as depicted in
Because, in the semiconductor apparatus according to the present modification example also, the light attenuation sections 1531 which are Si quantum dots whose refractive index is higher than the refractive index of surrounding materials are arranged between the photodiode PD and the read circuit 1422, it is possible to hinder synchrotron radiation generated by hot carrier at the read circuit 1422 or the logic circuit 1432 from reaching the photodiode PD, and to reduce noise.
Next, a semiconductor apparatus manufacturing method according to the present modification example is explained by using
Next, as depicted in
Because, in the semiconductor apparatus according to the present modification example also, synchrotron radiation is reflected totally at the interfaces between the insulation layer 1446 and the projected light attenuation sections 1542 formed in the semiconductor substrate 1421, and the synchrotron radiation is attenuated in the light attenuation sections 1542, it is possible to hinder synchrotron radiation generated by hot carrier at the read circuit 1422 or the logic circuit 1432 from reaching the photodiode PD, and to reduce noise.
A semiconductor apparatus according to a fifth embodiment of the present technology is explained by using
The reflection preventing sections 1701 are arranged between at least the second active elements in the Si substrate 1651 and the photoelectric converting sections in the Si substrate 1611, and has a function of lowering the reflectance of light on the backside of the Si substrate 1651. In the example depicted in
Next, a semiconductor apparatus manufacturing method according to the present embodiment is explained by using
In a case where the reflection preventing sections 1701 are not provided, total reflection at the interfaces between SiO2 included in the first wiring layer 1630 and the Si substrate 1651 occurs more easily because the difference between their refractive indices is large. Because there is a distance between the Si substrate 1611 and the Si substrate 1651, there is a possibility that light having entered photoelectric converting sections of the Si substrate 1611, and having been reflected off from the Si substrate 1651 passes the element separating sections 1612, and enters other photoelectric converting sections. Light having been reflected off from the backside of the Si substrate 1651, and having entered photoelectric converting sections is converted into electric signals by the photoelectric converting sections, and accordingly generates noise inevitably.
Because the reflection preventing sections 1701 are provided between second active elements and photoelectric converting sections, and the reflection preventing sections 1701 include SiN having an intermediate refractive index of Si in the present embodiment, the difference between the refractive indices of SiN and Si becomes smaller than in a case where the reflection preventing sections 1701 are not provided, total reflection on the Si substrate 1651 can be suppressed, and noise of photoelectric converting sections can be reduced.
In the present modification example also, because the reflection preventing section 1711 is provided between second active elements and photoelectric converting sections, and the reflection preventing section 1711 is provided in an area larger than the Si substrate 1651, total reflection on the Si substrate 1651 can be suppressed, and noise of photoelectric converting sections can be reduced.
In the present modification example also, because the reflection preventing section 1721 is provided in an area larger than the Si substrate 1651 between second active elements and photoelectric converting sections, and the reflection preventing sections 1722 are provided on the side surfaces of the Si substrate 1651, total reflection on the Si substrate 1651 can be suppressed, and noise of photoelectric converting sections can be reduced.
In the present modification example also, because the reflection preventing section 1731 is provided between second active elements and photoelectric converting sections, and the refractive indices gradually decrease from the Si substrate 1651 toward the first wiring layer 1630, total reflection on the Si substrate 1651 can be suppressed, and noise of photoelectric converting sections can be reduced.
In the present modification example also, because the reflection preventing section 1731 is provided between second active elements and photoelectric converting sections, total reflection on the Si substrate 1651 can be suppressed, and noise of photoelectric converting sections can be reduced even if the intermediate film 1732 having a different refractive index is provided between the reflection preventing section 1731 and the Si substrate 1651.
In the semiconductor apparatus according to the present modification example, because light having reached the reflection preventing section 1741 is diffusedly reflected in a case where the size of the recessed/projected structure of the reflection preventing section 1741 is in the order of micrometers which are larger than the wavelength of light, the light is reflected off from the backside of the Si substrate 1651, the amount of light that enters photoelectric converting sections can be reduced, and noise can be reduced. In addition, in a case where the size of the recessed/projected structure is in the order of nanometers smaller than the wavelength of light, a moth-eye structure in which the refractive index changes gradually is formed, and so reflection of light off from the backside of the Si substrate 1651 can be suppressed, and noise due to entrance of light into photoelectric converting sections can be reduced.
The present technology has been described with reference to the first to fifth embodiments as described above, and statements and figures included as a part of the disclosure should not be understood to limit the present technology. For those skilled in the art, various alternative embodiments, implementation examples and operation technologies will be apparent from this disclosure.
For example, the semiconductor apparatus according to the first to fifth embodiments of the present technology can be applied to any type of electronic equipment having an image pickup function, such as a camera system such as a digital still camera or a video camera, or a mobile phone having an image pickup function, for example. For example, it can be applied to electronic equipment (camera) depicted in
The semiconductor apparatus according to the first to fifth embodiments can be applied as the semiconductor apparatus 2200. The optical system 2201 guides image light (incident light) from a subject to a pixel region 2001 of the semiconductor apparatus 2200. The optical system 2201 may include plural optical lenses. The shutter apparatus 2202 controls a light illumination period and a light blocking period of light heading toward the semiconductor apparatus 2200. The driving section 204 controls transfer operation of the semiconductor apparatus 2200 and shutter operation of the shutter apparatus 2202. The signal processing section 2203 performs various types of signal processing on signals output from the semiconductor apparatus 2200. Video signals after the signal processing are stored on a storage medium such as a memory or output to a monitor or the like.
According to the image pickup apparatus according to embodiments of the present technology, because electrical connection are established between substrates according to the degree of integration of the substrates, a structure that electrically connects the substrates will not inevitably necessitate an increase of the chip sizes, inhibit miniaturization of the area size per pixel, and so on. As a result, it is possible to provide the image pickup apparatus with a triple-layer structure that will not inhibit miniaturization of the area size per pixel with chip sizes equivalent to conventional chip sizes. Note that advantages of the present technology are not necessarily limited to the advantages described here, and may be any of advantages described in the present specification.
Those skilled in the art can conceive of various corrections, combinations, sub-combinations and changes according to requirements in terms of designs and other factors, and it should be understood that they are included within the scope of the attached claims and equivalents thereof.
In addition, while a backside illumination CMOS image sensor is depicted as an example of the semiconductor apparatus according to the first to fifth embodiments of the present technology, the semiconductor apparatus according to the first to fifth embodiments of the present technology can also be applied to a solid-state image pickup apparatus such as a backside illumination CCD image sensor. Further, the semiconductor apparatus of the present technology may be applied also to various types of semiconductor apparatuses other than solid-state image pickup apparatuses, such as a storage apparatus that uses a semiconductor, a display apparatus that uses a semiconductor, a sensor apparatus that uses a semiconductor or a computing apparatus that uses a semiconductor, for example.
For example, the semiconductor apparatus of the present technology may be applied to the configuration of a semiconductor storage apparatus such as a DRAM that has memory cells as unit cells, instead of pixels having photoelectric converting sections. Although current DRAMs include one-transistor type memory cells (unit cells), by adopting the stacked structure of the present technology, DRAMs having three transistor-type memory cells (unit cells) that were used in the 1970's can be configured without deteriorating the integration densities. Further, by forming a shield structure mentioned above between an upper-layer DRAM and a lower layer DRAM of a semiconductor storage apparatus with a three-dimensional structure formed by stacking plural layers of DRAMs having one-transistor type memory cells (unit cells), a thermal, optical and electromagnetic shield can be formed between the upper-layer DRAM and the lower layer DRAM. Accordingly, it is possible to prevent noise, operation errors and the like in operation that involves concentration of electrical energy in high-speed operation DRAMs or the like.
In addition, while negative electric charge (electrons) is used as signal charge in the semiconductor apparatus according to the first to fifth embodiments of the present technology in the examples explained, the present technology can be applied also to cases where positive electric charge (holes) is used as signal charge. In a case where holes are used as signal charge, it is sufficient if p-type regions and n-type regions are configured in opposite arrangement.
Hereinafter, the image pickup apparatus 1 according to a sixth embodiment of the present disclosure is explained in detail by referring to figures. Note that explanations are given in the following order.
1. Embodiment (Image Pickup Apparatus Having Stacked Structure of Three Substrates)
2. First Modification Example (First Example of Planar Configuration)
3. Second Modification Example (Second Example of Planar Configuration)
4. Third Modification Example (Third Example of Planar Configuration)
5. Fourth Modification Example (Example in which Middle Section of Pixel Array Section Has Contact Section between Substrates)
6. Fifth Modification Example (Example in which Planar Transfer Transistors are Provided)
7. Sixth Modification Example (Example in which One Pixel Circuit is Connected with One Pixel)
8. Seventh Modification Example (Configuration Example of Pixel Separating Section)
For example, the image pickup apparatus 1 in
The pixel array section 540 includes pixels 541 that are arranged repetitively in an array. More specifically, a pixel sharing unit 539 including plural pixels is a unit of repetition, and this is arranged repetitively in an array having a row direction and a column direction. Note that, in the present specification, for convenience, the row direction is called direction H, and the column direction orthogonal to the row direction is called direction V, in some cases. In the example in
For example, the row driving section 520 includes a row addressing control section that determines the position of a row whose pixels are to be driven, in other words, a row decoder section, and a row driving circuit section that generates signals for driving the pixels 541A, 541B, 541C and 541D.
For example, the column signal processing section 550 includes a load circuit section that is connected to the vertical signal lines 543, and forms a source follower circuit with the pixels 541A, 541B, 541C and 541D (pixel sharing units 539). The column signal processing section 550 may have an amplification circuit section that amplifies signals read out from the pixel sharing units 539 via the vertical signal lines 543. The column signal processing section 550 may have a noise processing section. For example, the noise processing section removes a noise level of the system from signals read out from the pixel sharing units 539 as a result of photoelectric conversion.
For example, the column signal processing section 550 has an analog-digital converter (ADC). The analog-digital converter converts signals read out from the pixel sharing units 539 or analog signals having been subjected to the noise process described above into digital signals. For example, the ADC includes a comparator section and a counter section. The comparator section compares analog signals which are the targets of conversion and reference signals which are the targets of comparison with the analog signals. The counter section measures time taken until a result of the comparison at the comparator section is inverted. The column signal processing section 550 may include a horizontal scanning circuit section that performs control to scan read columns.
On the basis of a reference clock signal or a timing control signal input to the apparatus, the timing control section 530 supplies the row driving section 520 and the column signal processing section 550 with signals for controlling timing.
The image signal processing section 560 is a circuit that performs various types of signal processing on data obtained as a result of photoelectric conversion, in other words, data obtained as a result of image pickup operation at the image pickup apparatus 1. For example, the image signal processing section 560 includes an image signal processing circuit section and a data retaining section. The image signal processing section 560 may include a processor section.
An example of the signal processing executed at the image signal processing section 560 is a tone curve correction process that increases gradations in a case where AD-converted image pickup data is data in which a captured subject is dark, and reduces gradations in a case where AD-converted image pickup data is data in which a captured subject is bright. In this case, tone curve characteristics data defining the type of a tone curve on the basis of which gradations of image pickup data are to be corrected is desirably stored in advance on a data retaining section of the image signal processing section 560.
For example, the input section 510A is for inputting the reference clock signal, timing control signal and characteristics data that are described above, and the like from the outside of the apparatus to the image pickup apparatus 1. For example, the timing control signal is a vertical synchronizing signal, a horizontal synchronization signal or the like. For example, the characteristics data is for being stored on the data retaining section of the image signal processing section 560. For example, the input section 510A includes an input terminal 511, an input circuit section 512, an input amplitude changing section 513, an input data conversion circuit section 514 and a power supply section (not depicted).
The input terminal 511 is an external terminal for inputting data. The input circuit section 512 is for taking in signals input to the input terminal 511 to the inside of the image pickup apparatus 1. The input amplitude changing section 513 changes the amplitudes of signals taken in through the input circuit section 512 into amplitudes that are easier to use inside the image pickup apparatus 1. The input data conversion circuit section 514 changes the order of the data array of input data. For example, the input data conversion circuit section 514 includes a serial-parallel conversion circuit. The serial-parallel conversion circuit converts serial signals received as input data into parallel signals. Note that the input amplitude changing section 513 and the input data conversion circuit section 514 may be omitted from the input section 510A. On the basis of power supply supplied from the outside to the image pickup apparatus 1, the power supply section supplies power supply set to various types of voltages that are necessary inside the image pickup apparatus 1.
When the image pickup apparatus 1 is connected with an external memory device, the input section 510A may be provided with a memory interface circuit that receives data from the external memory device. For example, the external memory device is a flash memory, an SRAM, a DRAM or the like.
The output section 510B outputs image data to the outside of the apparatus. For example, this image data is image data of images picked up at the image pickup apparatus 1, image data which has been subjected to signal processing at the image signal processing section 560, or the like. For example, the output section 510B includes an output data conversion circuit section 515, an output amplitude changing section 516, an output circuit section 517 and an output terminal 518.
For example, the output data conversion circuit section 515 includes a parallel-serial conversion circuit, and the output data conversion circuit section 515 converts parallel signals used inside the image pickup apparatus 1 into serial signals. The output amplitude changing section 516 changes the amplitudes of the signals used inside the image pickup apparatus 1. The signals with the changed amplitudes are easier to use in an external device which is connected outside the image pickup apparatus 1. The output circuit section 517 is a circuit that outputs data from the inside of the image pickup apparatus 1 to the outside of the apparatus, and the output circuit section 517 drives a wire that is outside of the image pickup apparatus 1 and connected to the output terminal 518. The output terminal 518 outputs data from the image pickup apparatus 1 to the outside of the apparatus. The output data conversion circuit section 515 and the output amplitude changing section 516 may be omitted from the output section 510B.
When the image pickup apparatus 1 is connected with an external memory device, the output section 510B may be provided with a memory interface circuit that outputs data to the external memory device. For example, the external memory device is a flash memory, an SRAM, a DRAM or the like.
Both the pixel array section 540 and the pixel sharing units 539 included in the pixel array section 540 are configured by using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with plural pixels 541A, 541B, 541C and 541D provided in the pixel sharing units 539. Each of these pixels 541 has a photodiode (a photodiode PD mentioned below) and a transfer transistor (a transfer transistor TR mentioned below). The second substrate 200 is provided with pixel circuits (pixel circuits 210 mentioned below) provided in the pixel sharing units 539. Each pixel circuit reads out a pixel signal transferred from the photodiode of the pixel 541A, 541B, 541C or 541D via the transfer transistor, or resets the photodiode. In addition to such pixel circuits, the second substrate 200 has plural row driving signal lines 542 extending in the row direction and plural vertical signal lines 543 extending in the column direction. The second substrate 200 further has a power line 544 extending in the row direction. For example, the third substrate 300 has the input section 510A, the row driving section 520, the timing control section 530, the column signal processing section 550, the image signal processing section 560 and the output section 510B. For example, the row driving section 520 is provided in a region that partially overlaps the pixel array section 540 in the stacking direction of the first substrate 100, the second substrate 200 and the third substrate 300 (hereinafter, simply referred to as the stacking direction). More specifically, the row driving section 520 is provided in a region overlapping, in the stacking direction, a portion near an end section in direction H of the pixel array section 540 (
For example, the first substrate 100 and the second substrate 200 are electrically connected by through-electrodes (through-electrodes 120E and 121E in
The electrical connecting sections electrically connecting the second substrate 200 and the third substrate 300 can be provided at desired locations. For example, as mentioned as being the contact regions 201R, 202R, 301R and 302R with reference to
For example, the first substrate 100 and the second substrate 200 are provided with connection hole sections H1 and H2. The connection hole sections H1 and H2 penetrate the first substrate 100 and the second substrate 200 (
Note that while
The pixels 541A, 541B, 541C and 541D have mutually the same constituent elements. Hereinafter, in order to make distinctions between the constituent elements of the pixels 541A, 541B, 541C and 541D, an identification number 1 is given at the ends of reference characters of constituent elements of the pixel 541A, an identification number 2 is given at the ends of reference characters of constituent elements of the pixel 541B, an identification number 3 is given at the ends of reference characters of constituent elements of the pixel 541C, and an identification number 4 is given at the ends of reference characters of constituent elements of the pixel 541D. In a case where it is not necessary to make distinctions between constituent elements of the pixels 541A, 541B, 541C and 541D, the identification numbers at the ends of the reference characters of the constituent elements of the pixels 541A, 541B, 541C and 541D are omitted.
For example, the pixels 541A, 541B, 541C and 541D have photodiodes PD, transfer transistors TR electrically connected with the photodiodes PD and floating diffusions FD electrically connected to the transfer transistors TR. The cathode of each photodiode PD (PD1, PD2, PD3 and PD4) is electrically connected to the source of a transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The photodiode PD performs photoelectric conversion of incident light, and generates electric charge according to the received light amount. For example, the transfer transistors TR (transfer transistors TR1, TR2, TR3 and TR4) are n-type CMOS (Complementary Metal Oxide Semiconductor) transistors. The drain of each transfer transistor TR is electrically connected to a floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to a driving signal line. The driving signal line is a part of plural row driving signal lines 542 (see
The four floating diffusions FD (floating diffusions FD1, FD2, FD3 and FD4) included in the one pixel sharing unit 539 are electrically connected with each other, and are electrically connected to the gate of the amplification transistor AMP, and the source of the FD conversion gain switch transistor FDG. The drain of the FD conversion gain switch transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switch transistor FDG is connected to a driving signal line. The driving signal line is a part of the plural row driving signal lines 542 connected to the one pixel sharing unit 539. The drain of the reset transistor RST is connected to the power line VDD, and the gate of the reset transistor RST is connected to a driving signal line. The driving signal line is a part of the plural row driving signal lines 542 connected to the one pixel sharing unit 539. The gate of the amplification transistor AMP is connected to the floating diffusions FD, the drain of the amplification transistor AMP is connected to the power line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line 543, and the gate of the selection transistor SEL is connected to a driving signal line. The driving signal line is a part of the plural row driving signal lines 542 connected to the one pixel sharing unit 539.
When a transfer transistor TR is turned on, the transfer transistor TR transfers electric charge of the photodiode PD to the floating diffusion FD. For example, the gate (transfer gate TG) of the transfer transistor TR includes what is generally called a vertical electrode, and, as depicted in
The FD conversion gain switch transistor FDG is used when the gain of electric charge-voltage conversion at the floating diffusion FD is to be changed. Typically, pixel signals are small at the time of imaging at a dark location. On the basis of Q=CV, when electric charge-voltage conversion is performed, if the capacitance (FD capacitance C) of the floating diffusion FD is large, V at the time of conversion into a voltage with the amplification transistor AMP becomes small inevitably. On the other hand, pixel signals become large at a bright location, and so if the FD capacitance C is not large, the floating diffusion FD cannot fully receive the electric charge of the photodiode PD. Further, it is necessary for the FD capacitance C to have become large in order to prevent V at the time of conversion into a voltage at the amplification transistor AMP from becoming too large (in other words, in order for V to become small). Taking these into consideration, when the FD conversion gain switch transistor FDG is turned on, there is an increase of the gate capacitance by an amount corresponding to the FD conversion gain switch transistor FDG, and so the overall FD capacitance C becomes large. On the other hand, when the FD conversion gain switch transistor FDG is turned off, the overall FD capacitance C becomes small. In such a manner, it is possible to make the FD capacitance C variable, and switch the conversion efficiency by turning on and off the FD conversion gain switch transistor FDG. For example, the FD conversion gain switch transistor FDG is an N-type CMOS transistor.
Note that in another possible configuration, the FD conversion gain switch transistor FDG is not provided. At this time, for example, the pixel circuit 210 includes three transistors which are the amplification transistor AMP, the selection transistor SEL and the reset transistor RST, for example. For example, the pixel circuit 210 has at least one of pixel transistors such as the amplification transistor AMP, the selection transistor SEL, the reset transistor RST or the FD conversion gain switch transistor FDG.
The selection transistor SEL may be provided between the power line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to a row driving signal line 542 (see
The first substrate 100 has an insulating film 111, a fixed electric charge film 112, the semiconductor layer 100S and the wiring layer 100T sequentially from the light-reception lens 401 side. For example, the semiconductor layer 100S includes a silicon substrate. For example, the semiconductor layer 100S has p well layers 115 at and near parts of the front surface (a surface on the wiring layer 100T side), and n-type semiconductor regions 114 in other regions (regions deeper than the p well layers 115). For example, the n-type semiconductor regions 114 and the p well layers 115 are included in pn junction-type photodiodes PD. The p well layers 115 are p-type semiconductor regions.
Near the front surface of the semiconductor layer 100S, floating diffusions FD and VSS contact regions 118 are provided. The floating diffusions FD include the n-type semiconductor regions provided in the p well layers 115. For example, the floating diffusions FD (floating diffusions FD1, FD2, FD3 and FD4) of the pixels 541A, 541B, 541C and 541D are provided proximately to each other at middle sections of pixel sharing units 539 (
The VSS contact regions 118 are regions electrically connected to the reference potential line VSS, and are arranged apart from the floating diffusions FD. For example, in the pixels 541A, 541B, 541C and 541D, a floating diffusion FD is arranged at one end of each pixel in direction V, and a VSS contact region 118 is arranged at the other end (
The first substrate 100 is provided with transfer transistors TR, along with photodiodes PD, floating diffusions FD and VSS contact regions 118. A photodiode PD, a floating diffusion FD, a VSS contact region 118 and a transfer transistor TR are provided in each of the pixels 541A, 541B, 541C and 541D. Each transfer transistor TR is provided on the front surface side (a side opposite to the light-incidence surface, the second substrate 200 side) of the semiconductor layer 100S. The transfer transistor TR has a transfer gate TG. For example, the transfer gate TG includes a horizontal portion TGb facing the front surface of the semiconductor layer 100S, and a vertical portion TGa provided in the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is in contact with the horizontal portion TGb, and the other end is provided in an n-type semiconductor region 114. Because the transfer transistor TR includes such a vertical transistor, occurrence of a transfer failure of pixel signals becomes unlikely, and it is possible to enhance the efficiency of reading out pixel signals.
The horizontal portion TGb of the transfer gate TG extends from a position facing the vertical portion TGa toward a middle section of the pixel sharing unit 539 in direction H, for example (
The semiconductor layer 100S is provided with the pixel separating section 117 separating the pixels 541A, 541B, 541C and 541D from each other. Each pixel separating section 117 is formed as a section extending in the normal direction of the semiconductor layer 100S (a direction perpendicular to the front surface of the semiconductor layer 100S). The pixel separating section 117 is provided to partition the pixels 541A, 541B, 541C and 541D, and has a grid planar shape, for example (
For example, the semiconductor layer 100S is provided with first pinning regions 113 and second pinning regions 116. Each first pinning region 113 is provided near the backside of the semiconductor layer 100S, and is arranged between an n-type semiconductor region 114 and the fixed electric charge film 112. Each second pinning region 116 is provided on the side surface of the pixel separating section 117, specifically, between the pixel separating section 117 and a p well layer 115 or an n-type semiconductor region 114. For example, the first pinning regions 113 and the second pinning regions 116 include p-type semiconductor regions.
The fixed electric charge film 112 having negative fixed electric charge is provided between the semiconductor layer 100S and the insulating film 111. Due to an electrical field induced by the fixed electric charge film 112, the first pinning regions 113 of a hole accumulation layer are formed at an interface on the light-reception surface side (backside) of the semiconductor layer 100S. Thereby, generation of a dark current due to the interface state on the light-reception surface side of the semiconductor layer 100S is suppressed. For example, the fixed electric charge film 112 includes an insulating film having negative fixed electric charge. For example, examples of a material of the insulating film having the negative fixed electric charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide and tantalum oxide.
Light-shielding films 117A are provided between the fixed electric charge film 112 and the insulating film 111. The light-shielding films 117A may be provided continuously with the light-shielding films 117A included in the pixel separating section 117. For example, the light-shielding films 117A between the fixed electric charge film 112 and the insulating film 111 are provided selectively at positions that are in the semiconductor layer 100S and that face the pixel separating section 117. The insulating film 111 is provided to cover the light-shielding films 117A. For example, the insulating film 111 includes silicon oxide.
The wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 has an interlayer dielectric film 119, pad sections 120 and 121, a passivation film 122, an interlayer dielectric film 123 and a junction film 124 in this order from the semiconductor layer 100S side. For example, the horizontal portions TGb of the transfer gates TG are provided in the wiring layer 100T. The interlayer dielectric film 119 is provided over the entire front surface of the semiconductor layer 100S, and is in contact with the semiconductor layer 100S. For example, the interlayer dielectric film 119 includes a silicon oxide film. Note that the configuration of the wiring layer 100T is not limited to the one mentioned above, and only has to be configuration having wires and an insulating film.
The pad sections 121 are for connecting plural VSS contact regions 118 with each other. For example, a pad section 121 electrically connects VSS contact regions 118 provided in pixels 541C and 541D of one of pixel sharing units 539 that are adjacent to each other in direction V, and VSS contact regions 118 provided in pixels 541A and 541B of the other pixel sharing unit 539. For example, each pad section 121 is provided to cross the pixel separating section 117, and is arranged to overlap at least a part of each of the four VSS contact regions 118. Specifically, the pad section 121 is formed in a region overlapping, in a direction perpendicular to the front surface of the semiconductor layer 100S, at least a part of each of plural VSS contact regions 118, and at least a part of the pixel separating section 117 formed between the plural VSS contact regions 118. The interlayer dielectric film 119 is provided with connection vias 121C for electrically connecting the pad sections 121 and the VSS contact regions 118. A connection via 121C is provided for each of the pixels 541A, 541B, 541C and 541D. For example, by a part of a pad section 121 being embedded in a connection via 121C, the pad section 121 and a VSS contact region 118 are electrically connected. For example, a pad section 120 and a pad section 121 of each of plural pixel sharing units 539 arranged next to each other in direction V are arranged at approximately the same positions in direction H (
By providing the pad sections 120, it is possible to reduce wires for connecting floating diffusions FD to pixel circuits 210 (e.g., the gate electrodes of amplification transistors AMP) over the entire chip. Similarly, by providing the pad sections 121, it is possible to reduce wires that supply a potential to VSS contact regions 118 over the entire chip. Thereby, reduction of the overall area size of the chip, suppression of electrical interference between wires in miniaturized pixels, cost reduction due to reduction of the number of parts, and/or the like become possible.
The pad sections 120 and 121 can be provided at desired positions of the first substrate 100 and the second substrate 200. Specifically, the pad sections 120 and 121 can be provided in either the wiring layer 100T or an insulation region 212 of the semiconductor layer 200S. In a case where the pad sections 120 and 121 are provided in the wiring layer 100T, the pad sections 120 and 121 may be brought into direct contact with the semiconductor layer 100S. Specifically, the pad sections 120 and 121 may be directly connected with at least a part of each of floating diffusions FD and/or VSS contact regions 118, in possible configuration. In addition, connection vias 120C and 121C may be provided from each of floating diffusions FD and/or VSS contact regions 118 connected to the pad sections 120 and 121, and the pad sections 120 and 121 may be provided at desired positions of the wiring layer 100T and the insulation region 2112 of the semiconductor layer 200S, in possible configuration.
In particular, in a case where the pad sections 120 and 121 are provided in the wiring layer 100T, it is possible to reduce wires connected to floating diffusions FD and/or VSS contact regions 118 in the insulation region 212 of the semiconductor layer 200S. Thereby, it is possible to reduce the area size of the insulation region 212 that is in the second substrate 200 where pixel circuits 210 are formed, and is for forming through-wires for connection from floating diffusions FD to the pixel circuits 210. Therefore, it is possible to ensure that there is a large area size for formation of the pixel circuits 210 in the second substrate 200. By ensuring that there is a large area size for the pixel circuits 210, pixel transistors can be formed large, and this can contribute to enhancement of the image quality due to noise reduction or the like.
In particular, in a case where an FTI structure is used for the pixel separating section 117, a floating diffusion FD and/or a VSS contact region 118 are/is preferably provided for each pixel 541, and so it is possible to significantly reduce wires that connect the first substrate 100 and the second substrate 200 by using the configuration with the pad sections 120 and 121.
In addition, as in
For example, the pad sections 120 and 121 include polysilicon (Poly Si), more specifically doped polysilicon doped with impurities. The pad sections 120 and 121 preferably include a highly heat-resistant electrically conductive material such as polysilicon, tungsten (W), titanium (Ti) or titanium nitride (TiN). Thereby, it becomes possible to form pixel circuits 210 after the semiconductor layer 200S of the second substrate 200 is pasted onto the first substrate 100. Hereinafter, reasons for this are explained. Note that in the following explanation, a method in which pixel circuits 210 are formed after the first substrate 100 and the semiconductor layer 200S of the second substrate 200 are pasted together is called a first manufacturing method.
Here, pixel circuits 210 are formed in the second substrate 200, and then the second substrate 200 is pasted onto the first substrate 100 in another possible method (hereinafter, this is called a second manufacturing method). In this second manufacturing method, in each of the front surface (the front surface of the wiring layer 100T) of the first substrate 100, and the front surface (the front surface of the wiring layer 200T) of the second substrate 200, electrodes for electrical connection are formed in advance. When the first substrate 100 and the second substrate 200 are pasted together, simultaneously, the electrodes for electrical connection formed in the front surface of the first substrate 100 and the front surface of the second substrate 200 come into contact with each other. Thereby, electrical connection are formed between wires included in the first substrate 100 and wires included in the second substrate 200. Therefore, by adopting the configuration of the image pickup apparatus 1 formed by using the second manufacturing method, for example, it can be manufactured by using appropriate processes according to the configuration of each of the first substrate 100 and the second substrate 200, and a high-quality, high-performance image pickup apparatus can be manufactured.
When the first substrate 100 and the second substrate 200 are pasted together in such a second manufacturing method, an alignment error occurs due to a manufacturing apparatus for pasting in some cases. In addition, for example, the first substrate 100 and the second substrate 200 have sizes with diameters which are approximately several dozen centimeters, and when the first substrate 100 and the second substrate 200 are pasted together, there is a risk that expansion/contraction of the substrates occurs in microscopic regions of each section of the first substrate 100 and the second substrate 200. This expansion/contraction of the substrates is attributable to the fact there are slight differences in the timing at which the substrates come into contact with each other. Due to such expansion/contraction of the first substrate 100 and the second substrate 200, an error occurs in the positions of the electrodes for electrical connection formed in the front surface of the first substrate 100 and the front surface of the second substrate 200 in some cases. In the second manufacturing method, preferably, measures are taken to ensure that the electrodes of the first substrate 100 and the second substrate 200 come into contact with each other even if such an error occurs. Specifically, electrodes of at least one of the first substrate 100 and the second substrate 200, preferably both the first substrate 100 and the second substrate 200, are made larger taking the error described above into consideration. Because of this, if the second manufacturing method is used, for example, the sizes (the sizes in the substrate planar surface direction) of the electrodes formed in the front surface of the first substrate 100 or the second substrate 200 become larger than the sizes of inner electrodes extending from the inside of the first substrate 100 or the second substrate 200 toward the front surface in the thickness direction.
On the other hand, if the pad sections 120 and 121 include a heat-resistant electrically conductive material, it becomes possible to use the first manufacturing method described above. In the first manufacturing method, the first substrate 100 including photodiodes PD, transfer transistors TR and the like is formed, and then the first substrate 100 and the second substrate 200 (semiconductor layer 2000S) are pasted together. At this time, in the second substrate 200, patterns of active elements, wiring layers and the like included in the pixel circuit 210 have not been formed yet. Because patterns are not formed in the second substrate 200 yet, even if an error occurs in positions where the first substrate 100 and the second substrate 200 are pasted together when the first substrate 100 and the second substrate 200 are pasted together, such an error in the pasting does not cause an error in alignment between patterns of the first substrate 100 and patterns of the second substrate 200. This is because the patterns of the second substrate 200 are formed after the first substrate 100 and the second substrate 200 are pasted together. Note that when patterns are formed in the second substrate, for example, the patterns are formed in a light-exposure apparatus for pattern formation by using the patterns formed in the first substrate as the alignment targets. For the reason described above, an error in positions where the first substrate 100 and the second substrate 200 are pasted together does not become a problem in manufacturing of the image pickup apparatus 1 in the first manufacturing method. For a similar reason, an error attributable to expansion/contraction of the substrates that occurs in the second manufacturing method also does not become a problem in manufacturing of the image pickup apparatus 1 in the first manufacturing method.
In the first manufacturing method, the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are pasted together, and then active elements are formed on the second substrate 200 in such a manner. Thereafter, through-electrodes 120E and 121E and through-electrodes TGV (
The image pickup apparatus 1 manufactured by using such a first manufacturing method has features that are different from those of an image pickup apparatus manufactured by using the second manufacturing method. Specifically, in the image pickup apparatus 1 manufactured by the first manufacturing method, for example, the through-electrodes 120E, 121E and TGV have approximately uniform thicknesses (sizes in the substrate planar surface direction) from the second substrate 200 to the first substrate 100. Alternatively, when the through-electrodes 120E, 121E and TGV have tapered shapes, the tapered shapes have constant inclinations. The image pickup apparatus 1 having such through-electrodes 120E, 121E and TGV allows easier miniaturization of pixels 541.
Here, if the image pickup apparatus 1 is manufactured by the first manufacturing method, active elements are formed in the second substrate 200 after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are pasted together, and so the influence of a heating process necessary at the time of the formation of the active elements reaches the first substrate 100 also. Because of this, as described above, a highly heat-resistant electrically conductive material is preferably used for the pad sections 120 and 121 provided in the first substrate 100. For example, a material with a melting point higher than (i.e., more heat-resistant than) at least a part of wire materials included in the wiring layer 200T of the second substrate 200 is preferably used for the pad sections 120 and 121. For example, a highly heat-resistant electrically conductive material such as doped polysilicon, tungsten, titanium or titanium nitride is used for the pad sections 120 and 121. Thereby, it becomes possible to manufacture the image pickup apparatus 1 by using the first manufacturing method described above.
For example, the passivation film 122 is provided over the entire front surface of the semiconductor layer 100S such that it covers the pad sections 120 and 121 (
For example, the light-reception lenses 401 face the semiconductor layer 100S with the fixed electric charge film 112 and the insulating film 111 being interposed therebetween (
The second substrate 200 has the semiconductor layer 200S and the wiring layer 200T in this order from the first substrate 100 side. The semiconductor layer 200S includes a silicon substrate. In the semiconductor layer 200S, well regions 211 are provided in the thickness direction. For example, the well regions 211 are p-type semiconductor regions. The second substrate 20 is provided with pixel circuits 210 each of which is arranged for one pixel sharing unit 539. For example, the pixel circuits 210 are provided on the front surface side (wiring layer 200T side) of the semiconductor layer 200S. In the image pickup apparatus 1, the second substrate 200 is pasted onto the first substrate 100 such that the backside (semiconductor layer 200S side) of the second substrate 200 faces the front surface side (wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is pasted onto the first substrate 100 face-to-back.
The second substrate 200 is provided with the insulation region 212 that splits the semiconductor layer 200S, and the element separation regions 213 provided at parts of the semiconductor layer 200S in the thickness direction (
The insulation region 212 has a thickness which is approximately the same as the thickness of the semiconductor layer 200S (
The through-electrodes 120E and 121E are provided to penetrate the insulation region 212 in the thickness direction. The upper ends of the through-electrodes 120E and 121E are connected to wires (a first wire W1, a second wire W2, a third wire W3 and a fourth wire W4 mentioned below) of the wiring layer 200T. The through-electrodes 120E and 121E are provided to penetrate the insulation region 212, the junction film 124, the interlayer dielectric film 123 and the passivation film 122, and the lower ends thereof are connected to the pad sections 120 and 121 (
The through-electrodes TGV are provided to penetrate the insulation region 212 in the thickness direction. The upper ends of the through-electrodes TGV are connected to wires of wires 200T. The through-electrodes TGV are provided to penetrate the insulation region 212, the junction film 124, the interlayer dielectric film 123, the passivation film 122 and the interlayer dielectric film 119, and the lower ends thereof are connected to transfer gates TG (
The insulation region 212 is a region for providing the through-electrodes 120E and 121E and the through-electrodes TGV for electrically connecting the first substrate 100 and the second substrate 200 such that they are insulated from the semiconductor layer 200S. For example, in an insulation region 212 provided between two pixel circuits 210 (pixel sharing units 539) that are adjacent to each other in direction H, through-electrodes 120E and 121E and through-electrodes TGV (through-electrodes TGV1, TGV2, TGV3 and TGV4) connected to those two pixel circuits 210 are arranged. For example, the insulation region 212 is provided extending in direction V (
As explained with reference to
The element separation regions 213 are provided on the front surface side of the semiconductor layer 200S. The element separation regions 213 have an STI (Shallow Trench Isolation) structure. In the element separation regions 213, the semiconductor layer 200S has trenches extending in the thickness direction (in a direction vertical to the main surface of the second substrate 200), and insulating films are embedded in the trenches. For example, the insulating films include silicon oxide. Each element separation region 213 element-separates plural transistors included in a pixel circuit 210 from each other according to the layout of the pixel circuit 210. The semiconductor layer 200S (specifically, the well region 211) extends below the element separation regions 213 (at a deep section of the semiconductor layer 200S).
Here, differences between the outline shapes (the outline shapes in the substrate planar surface direction) of pixel sharing units 539 in the first substrate 100, and the outline shapes of pixel sharing units 539 in the second substrate 200 are explained with reference to
In the image pickup apparatus 1, pixel sharing units 539 are provided over both the first substrate 100 and the second substrate 200. For example, the outline shapes of the pixel sharing units 539 provided in the first substrate 100, and the outline shapes of the pixel sharing units 539 provided in the second substrate 200 are different from each other.
In
In
For example, in each pixel circuit 210, a selection transistor SEL, an amplification transistor AMP, a reset transistor RST and an FD conversion gain switch transistor FDG are arranged next to each other in direction V in this order (
For example, in addition to selection transistors SEL, amplification transistors AMP, reset transistors RST and FD conversion gain switch transistors FDG, VSS contact regions 218 connected to reference potential lines VSS are provided near the front surface of the semiconductor layer 200S. For example, the VSS contact regions 218 include p-type semiconductor regions. The VSS contact regions 218 are electrically connected to VSS contact regions 118 of the first substrate 100 (semiconductor layer 100S) via wires of the wiring layer 200T and through-electrodes 121E. For example, the VSS contact regions 218 are provided at positions that are adjacent to the sources of FD conversion gain switch transistors FDG with element separation regions 213 being interposed therebetween (
Next, the positional relation between pixel sharing units 539 provided in the first substrate 100 and pixel sharing units 539 provided in the second substrate 200 is explained with reference to
For example, the internal layout (the arrangement of transistors or the like) of one pixel sharing unit 539 in two pixel sharing units 539 of the second substrate 200 that are next to each other in direction H is approximately equal to an inversion in direction V and direction H of the internal layout of the other pixel sharing unit 539. Hereinafter, advantages attained by this layout are explained.
In two pixel sharing units 539 of the first substrate 100 that are next to each other in direction V, each pad section 120 is arranged at a middle section of the outline shape of a pixel sharing unit 539, that is, at a middle section of the pixel sharing unit 539 in direction V and direction H (
In contrast to this, by inverting, relative to each other at least in direction V, the internal layouts of two pixel sharing units 539 of the second substrate 200 that are next to each other in direction H, the distance between each pair of an amplification transistors AMP and a pad section 120 of both the two pixel sharing units 539 can be made short. Accordingly, as compared with the configuration in which the internal layouts of two pixel sharing units 539 of the second substrate 200 that are next to each other in direction H are made the same, miniaturization of the image pickup apparatus 1 becomes easy. Note that the planar layout of each of plural pixel sharing units 539 of the second substrate 200 is symmetric in the left and right directions in the area described in
In addition, the internal layouts of two pixel sharing units 539 of the second substrate 200 that are next to each other in direction H are preferably inverted also in direction H relative to each other. Hereinafter, reasons for this are explained. As depicted in
In addition, the position of the outline of each pixel sharing unit 539 of the second substrate 200 does not have to be aligned with the outline of any of pixel sharing units 539 of the first substrate 100. For example, regarding one pixel sharing unit 539 (e.g., one on the left side on the paper surface of
In addition, the positions of the outlines of plural pixel sharing units 539 of the second substrate 200 may not be aligned with each other. For example, the positions in direction V of the outlines of two pixel sharing units 539 of the second substrate 200 that are next to each other in direction H are arranged by being displaced relative to each other. Thereby, it becomes possible to make the distance between each pair of an amplification transistor AMP and a pad section 120 shorter. Accordingly, miniaturization of the image pickup apparatus 1 becomes easier.
Repetitive arrangement of pixel sharing units 539 in the pixel array section 540 is explained with reference to
For example, amplification transistors AMP preferably have a three-dimensional structure such as a Fin type structure (
For example, the wiring layer 200T includes a passivation film 221, an interlayer dielectric film 222 and plural wires (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3 and a fourth wiring layer W4). For example, the passivation film 221 is in contact with the front surface of the semiconductor layer 200S, and covers the entire front surface of the semiconductor layer 200S. The passivation film 221 covers the gate electrode of each of selection transistors SEL, amplification transistors AMP, reset transistors RST and FD conversion gain switch transistors FDG. The interlayer dielectric film 222 is provided between the passivation film 221 and the third substrate 300. The interlayer dielectric film 222 separates the plural wires (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3 and the fourth wiring layer W4). For example, the interlayer dielectric film 222 includes silicon oxide.
For example, in the wiring layer 200T, the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, the fourth wiring layer W4 and the contact sections 201 and 202 are provided in this order from the semiconductor layer 200S side, and these are insulated from each other by the interlayer dielectric film 222. The interlayer dielectric film 222 is provided with plural connecting sections that connect the first wiring layer W1, the second wiring layer W2, the third wiring layer W3 or the fourth wiring layer W4 and a layer underlying the layer. The connecting sections are portions formed by embedding an electrically conductive material in connection holes provided through the interlayer dielectric film 222. For example, the interlayer dielectric film 222 is provided with connecting sections 218V that connect the first wiring layer W1 and VSS contact regions 218 of the semiconductor layer 200S. For example, the hole sizes of such connecting sections that connect elements of the second substrate 200 are different from the hole sizes of through-electrodes 120E and 121E and through-electrodes TGV. Specifically, the hole sizes of the connection holes connecting elements of the second substrate 200 are preferably smaller than the hole sizes of the through-electrodes 120E and 121E and the through-electrodes TGV. Hereinafter, reasons for this are explained. The depths of connecting sections (the connecting sections 218V, etc.) provided in the wiring layer 200T are shallower than the depths of the through-electrodes 120E and 121E and the through-electrodes TGV. Because of this, it is possible to embed the electrically conductive material in the connection holes of the connecting sections easily as compared with the through-electrodes 120E and 121E and the through-electrodes TGV. By making the hole sizes of the connecting sections smaller than the hole sizes of the through-electrodes 120E and 121E and the through-electrodes TGV, miniaturization of the image pickup apparatus 1 becomes easier.
For example, the first wiring layer W1 connects through-electrodes 120E, and the gates of amplification transistors AMP and the sources of FD conversion gain switch transistors FDG (specifically, connection holes reaching the sources of the FD conversion gain switch transistors FDG). For example, the first wiring layer W1 connects through-electrodes 121E and connecting sections 218V, and thereby electrically connects VSS contact regions 218 of the semiconductor layer 200S and VSS contact regions 118 of the semiconductor layer 100S.
Next, a planar configuration of the wiring layer 200T is explained by using
For example, the third wiring layer W3 includes wires TRG1, TRG2, TRG3, TRG4, SELL, RSTL and FDGL extending in direction H (row direction) (
For example, the fourth wiring layer W4 includes power lines VDD, reference potential lines VSS and vertical signal lines 543 extending in direction V (column direction) (
Contact sections 201 and 202 may be provided at positions overlapping the pixel array section 540 when seen in a plan view (e.g.,
For example, the third substrate 300 has the wiring layer 300T and the semiconductor layer 300S in this order from the second substrate 200 side. For example, the front surface of the semiconductor layer 300S is provided on the second substrate 200 side. The semiconductor layer 300S includes a silicon substrate. Portions on the front surface side of the semiconductor layer 300S are provided with circuits. Specifically, for example, the portions on the front surface side of the semiconductor layer 300S are provided with at least some of the input section 510A, the row driving section 520, the timing control section 530, the column signal processing section 550, the image signal processing section 560 and the output section 510B. For example, the wiring layer 300T provided between the semiconductor layer 300S and the second substrate 200 includes an interlayer dielectric film, plural wiring layers separated by the interlayer dielectric film, and contact sections 301 and 302. The contact sections 301 and 302 are exposed at the front surface (a surface on the second substrate 200 side) of the wiring layer 300T, the contact section 301 is in contact with a contact section 201 of the second substrate 200, and the contact section 302 is in contact with a contact section 202 of the second substrate 200. The contact sections 301 and 302 are electrically connected to circuits (e.g., at least any of the input section 510A, the row driving section 520, the timing control section 530, the column signal processing section 550, the image signal processing section 560 and the output section 510B) formed in the semiconductor layer 300S. For example, the contact sections 301 and 302 include a metal such as Cu (copper) or aluminum (Al). For example, an external terminal TA is connected to the input section 510A via the connection hole section H1, and an external terminal TB is connected to the output section 510B via the connection hole section H2.
Here, features of the image pickup apparatus 1 are explained.
Typically, an image pickup apparatus includes photodiodes and pixel circuits as a main configuration. Here, if the area sizes of the photodiodes are increased, electric charge that is generated as a result of photoelectric conversion increases; as a result, the signal/noise ratio (S/N ratio) of pixel signals is improved, and the image pickup apparatus can output better image data (image information). On the other hand, if the sizes of transistors (particularly, the sizes of amplification transistors) included in the pixel circuits are increased, noise that is generated in the pixel circuits decreases; as a result, the S/N ratio of image pickup signals is improved, and the image pickup apparatus can output better image data (image information).
However, if the area sizes of photodiodes are increased within a limited area size of a semiconductor substrate in an image pickup apparatus in which the photodiodes and pixel circuits are provided in the same semiconductor substrate, it can be considered that the sizes of transistors included in the pixel circuits become smaller inevitably. In addition, if the sizes of the transistors included in the pixel circuits are increased, it can be considered that the area sizes of the photodiodes become smaller inevitably.
In order to solve these problems, for example, the image pickup apparatus 1 according to the present embodiment uses a structure in which plural pixels 541 share one pixel circuit 210, and the shared pixel circuit 210 is arranged to overlap photodiodes PD. Thereby, it is possible to realize the largest possible increases of the area sizes of photodiodes PD, and the largest possible increases of the sizes of transistors provided in the pixel circuits 210 within a limited area size of semiconductor substrates. Thereby, the S/N ratio of pixel signals can be improved, and the image pickup apparatus 1 can output better image data (image information).
When a structure in which plural pixels 541 share one pixel circuit 210, and the one pixel circuit 210 is arranged to overlap photodiodes PD is realized, there are plural wires extending from floating diffusions FD of the plural pixels 541, and being connected to the one pixel circuit 210. In order to ensure that there is a large area size for formation of pixel circuits 210 in the semiconductor substrate 200, for example, a connection wire that connects the plural extending wires with each other into one can be formed. The same applies also to plural wires extending from VSS contact regions 118, and a connection wire that connects the plural extending wires with each other into one can be formed.
For example, if the connection wire that connects the plural wires extending from the floating diffusions FD of the plural pixels 541 with each other is formed in the semiconductor substrate 200 in which pixel circuits 210 are formed, it can be considered that the area sizes for forming transistors included in the pixel circuits 210 become smaller inevitably. Similarly, if the connection wire that connects the plural wires extending from the VSS contact regions 118 of the plural pixels 541 with each other into one is formed in the semiconductor substrate 200 in which the pixel circuits 210 are formed, it can be considered that the area sizes for forming the transistors included in the pixel circuits 210 become smaller inevitably.
In order to solve these problems, for example, the image pickup apparatus 1 according to the present embodiment can include a structure in which plural pixels 541 share one pixel circuit 210, and the shared pixel circuit 210 is arranged to overlap photodiodes PD, and a structure in which a connection wire that connects floating diffusions FD of the plural pixels 541 with each other into one, and a connection wire that connects VSS contact regions 118 of the plural pixels 541 with each other into one are provided in the first substrate 100.
Here, if the second manufacturing method mentioned earlier is used as a manufacturing method for providing the first substrate 100 with the connection wire that connects the floating diffusions FD of the plural pixels 541 with each other into one, and the connection wire that connects the VSS contact regions 118 of the plural pixels 541 with each other into one, for example, it can be manufactured by using processes that are appropriate according to the configuration of each of the first substrate 100 and the second substrate 200, and a high-quality, high-performance image pickup apparatus can be manufactured. In addition, connection wires of the first substrate 100 and the second substrate 200 can be formed with easy processes. Specifically, in a case where the second manufacturing method described above is used, the front surface of the first substrate 100 and the front surface of the second substrate 200 which surfaces become boundary surfaces on which the first substrate 100 and the second substrate 200 are pasted together are provided with electrodes to be connected to the floating diffusions FD, and electrodes to be connected to the VSS contact regions 118. Further, electrodes that are formed in the front surfaces of the first substrate 100 and the second substrate 200 are made larger preferably such that the electrodes formed in the front surfaces of these two substrates come into contact with each other even if positional misalignment occurs between the electrodes provided in these two substrates when the front surfaces of these two substrates are pasted together. In this case, it can be considered that it inevitably becomes difficult to arrange the electrodes described above within a limited area size of each pixel provided in the image pickup apparatus 1.
In order to solve a problem that it becomes necessary to form large electrodes at the boundary surfaces on which the first substrate 100 and the second substrate 200 are pasted together, for example, the first manufacturing method mentioned earlier can be used as a method of manufacturing the image pickup apparatus 1 according to the present embodiment in which plural pixels 541 share one pixel circuit 210, and the shared pixel circuit 210 is arranged to overlap photodiodes PD. Thereby, alignment of elements formed in each of the first substrate 100 and the second substrate 200 becomes easier, and a high-quality, high-performance image pickup apparatus can be manufactured. Further, a unique structure that is generated by using this manufacturing method can be provided. That is, the image pickup apparatus includes a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100, and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked one on another in this order, in other words, a structure in which the first substrate 100 and the second substrate 200 are stacked one on another face-to-back, and the image pickup apparatus includes through-electrodes 120E and 121E that penetrate the semiconductor layer 200S of the second substrate 200 and the wiring layer 100T of the first substrate 100 from the front surface side of the semiconductor layer 200S, and reach the front surface of the semiconductor layer 100S of the first substrate 100.
If the structure in which the connection wire that connects the floating diffusions FD of the plural pixels 541 with each other into one, and the connection wire that connects the VSS contact regions 118 of the plural pixels 541 with each other into one are provided in the first substrate 100, and the second substrate 200 are stacked one on another by using the first manufacturing method, and the pixel circuits 210 are formed in the second substrate 200, there is a possibility that influence of a heating process that is necessary when active elements provided in the pixel circuits 210 are formed inevitably reaches the connection wires described above formed in the first substrate 100.
In view of this, in order to solve the problem that the influence of the heating process when the active elements described above are formed inevitably reaches the connection wires described above, the image pickup apparatus 1 according to the present embodiment desirably uses a highly heat-resistant electrically conductive material for the connection wire that connects the floating diffusions FD of the plural pixels 541 with each other into one, and the connection wire that connects the VSS contact regions 118 of the plural pixels 541 with each other into one. Specifically, as the highly heat-resistant electrically conductive material, a material having a melting point higher than that of at least some of wire materials included in the wiring layer 200T of the second substrate 200 can be used.
In such a manner, for example, the image pickup apparatus 1 according to the present embodiment includes: (1) the structure in which the first substrate 100 and the second substrate 200 are stacked one on another face-to-back (specifically, the structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100, and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked one on another in this order); (2) the structure in which the through-electrodes 120E and 121E that penetrate the semiconductor layer 200S of the second substrate 200 and the wiring layer 100T of the first substrate 100 from the front surface side of the semiconductor layer 200S, and reach the front surface of the semiconductor layer 100S of the first substrate 100 are provided; and (3) the structure in which the connection wire that connects the floating diffusions FD provided in the plural pixels 541 with each other into one, and the connection wire that connects the VSS contact regions 118 provided in the plural pixels 541 with each other into one include a highly heat-resistant electrically conductive material. Because of this, it is made possible to provide the first substrate 100 with the connection wire that connects the floating diffusions FD provided in the plural pixels 541 with each other into one, and the connection wire that connects the VSS contact regions 118 provided in the plural pixels 541 with each other into one, without including large electrodes at the interface between the first substrate 100 and the second substrate 200.
Next, operation of the image pickup apparatus 1 is explained by using
In the present embodiment, pixels 541A, 541B, 541C and 541D (pixel sharing units 539), and pixel circuits 210 are provided in different substrates (the first substrate 100 and the second substrate 200). Thereby, as compared with a case where the pixels 541A, 541B, 541C and 541D and the pixel circuit 210 are formed in the same substrate, the area sizes of the pixels 541A, 541B, 541C and 541D and the pixel circuit 210 can be expanded. As a result, the amounts of pixel signals obtained by photoelectric conversion can be increased, and transistor noise of the pixel circuits 210 can be reduced. Thereby, the signal/noise ratio of pixel signals can be improved, and the image pickup apparatus 1 can output better pixel data (image information). In addition, miniaturization of the image pickup apparatus 1 (i.e., reduction of pixel sizes, and size reduction of the image pickup apparatus 1) becomes possible. Due to the reduction of pixel sizes, the image pickup apparatus 1 can have a larger number of pixels per unit area size, and can output high image-quality images.
In addition, in the image pickup apparatus 1, the first substrate 100 and the second substrate 200 are electrically connected with each other by through-electrodes 120E and 121E provided in the insulation region 212. For example, possible methods include a method in which the first substrate 100 and the second substrate 200 are connected by junctions between pad electrodes, and a method in which the first substrate 100 and the second substrate 200 are connected by through-wires (e.g., TSVs (Thorough Si Vias)) that penetrate semiconductor layers. As compared with such methods, by providing the through-electrodes 120E and 121E in the insulation region 212, it is possible to reduce area sizes necessary for connection of the first substrate 100 and the second substrate 200. Thereby, pixel sizes can be reduced, and the size of the image pickup apparatus 1 can be reduced further. In addition, further miniaturization of the area size per pixel enables a higher resolution. When it is not necessary to reduce the chip sizes, the formation regions of pixels 541A, 541B, 541C and 541D and pixel circuits 210 can be expanded. As a result, the amounts of pixel signals obtained by photoelectric conversion can be increased, and noise of transistors provided in the pixel circuits 210 can be reduced. Thereby, the signal/noise ratio of pixel signals can be improved, and the image pickup apparatus 1 can output better pixel data (image information).
In addition, in the image pickup apparatus 1, pixel circuits 210, and the column signal processing section 550 and the image signal processing section 560 are provided in different substrates (the second substrate 200 and the third substrate 300). Thereby, as compared with a case where the pixel circuits 210, and the column signal processing section 550 and the image signal processing section 560 are formed in the same substrate, the area size for the pixel circuits 210, and the area size for the column signal processing section 550 and the image signal processing section 560 can be expanded. Thereby, it becomes possible to reduce noise that occurs in the column signal processing section 550, mount a more advanced image processing circuit on the image signal processing section 560, and so on. Therefore, the signal/noise ratio of pixel signals can be improved, and the image pickup apparatus 1 can output better pixel data (image information).
In addition, in the image pickup apparatus 1, the pixel array section 540 is provided in the first substrate 100 and the second substrate 200, and the column signal processing section 550 and the image signal processing section 560 are provided in the third substrate 300. In addition, contact sections 201, 202, 301 and 302 that connect the second substrate 200 and the third substrate 300 are formed above the pixel array section 540. Because of this, it becomes possible for the contact sections 201, 202, 301 and 302 to have a freer layout without being interfered by various types of wires provided in the pixel array in terms of layouts. Thereby, it becomes possible to use the contact sections 201, 202, 301 and 302 for electrical connection between the second substrate 200 and the third substrate 300. By using the contact sections 201, 202, 301 and 302, for example, the degree of freedom of the layout of the column signal processing section 550 and the image signal processing section 560 becomes higher. Thereby, it becomes possible to reduce noise that occurs in the column signal processing section 550, mount a more advanced image processing circuit on the image signal processing section 560, and so on. Accordingly, the signal/noise ratio of pixel signals can be improved, and the image pickup apparatus 1 can output better pixel data (image information).
In addition, in the image pickup apparatus 1, the pixel separating section 117 penetrates the semiconductor layer 100S. Thereby, even in a case where the distances between adjacent pixels (pixels 541A, 541B, 541C and 541D) become shorter due to miniaturization of the area size per pixel, color mixing between the pixels 541A, 541B, 541C and 541D can be suppressed. Thereby, the signal/noise ratio of pixel signals can be improved, and the image pickup apparatus 1 can output better pixel data (image information).
In addition, in the image pickup apparatus 1, a pixel circuit 210 is provided for each pixel sharing unit 539. Thereby, as compared with a case where a pixel circuit 210 is provided for each of the pixels 541A, 541B, 541C and 541D, the formation regions for transistors (amplification transistors AMP, reset transistors RST, selection transistors SEL and FD conversion gain switch transistors FDG) included in the pixel circuits 210 can be increased. For example, by increasing the formation regions for the amplification transistors AMP, it becomes possible to suppress noise. Thereby, the signal/noise ratio of pixel signals can be improved, and the image pickup apparatus 1 can output better pixel data (image information).
Further, in the image pickup apparatus 1, pad sections 120 each of which electrically connects floating diffusions FD (floating diffusions FD1, FD2, FD3 and FD4) of four pixels (pixels 541A, 541B, 541C and 541D) are provided in the first substrate 100. Thereby, as compared with a case where such pad sections 120 are provided in the second substrate 200, the number of through-electrodes (through-electrodes 120E) that connect the first substrate 100 and the second substrate 200 can be reduced. Accordingly, it is possible to make the insulation region 212 small, and to ensure that there is a sufficiently large formation region (semiconductor layer 200S) for transistors included in the pixel circuits 210. Thereby, it becomes possible to reduce noise of the transistors included in the pixel circuits 210, it becomes possible to improve the signal/noise ratio of pixel signals, and the image pickup apparatus 1 can output better pixel data (image information).
Hereinafter, modification examples of the image pickup apparatus 1 according to the embodiment described above are explained. In the following modification examples, configurations which are the same as those in the embodiment described above are explained by giving them identical reference characters.
In the present modification example, as depicted in
In the present modification example, the outline of each pixel circuit 210 has an approximately square planar shape (
For example, as explained in the embodiment described above, pixel sharing units 539 of the first substrate 100 are formed in a pixel region including two rows and two columns, and have an approximately square planar shape (
As another possible arrangement example, horizontal portions TGb of transfer gates TG1, TG2, TG3 and TG4 can be provided only in regions facing the vertical portions Tga. At this time, as explained in the embodiment described above, the semiconductor layer 200S tends to be split into smaller pieces. Accordingly, it becomes difficult to form large transistors in pixel circuits 210. On the other hand, if horizontal portions TGb of transfer gates TG1, TG2, TG3 and TG4 extend from positions overlapping the vertical portions Tga in direction H as in the modification example described above, it becomes possible to increase widths of the semiconductor layer 200S as explained in the embodiment described above. Specifically, it becomes possible to arrange the positions in direction H of through-electrodes TGV1 and TGV3 connected to transfer gates TG1 and TG3 proximately to the position in direction H of a through-electrode 120E, and arrange the positions in direction H of through-electrodes TGV2 and TGV4 connected to transfer gates TG2 and TG4 proximately to the position in direction H of a through-electrode 121E (
For example, the sizes of pixel sharing units 539 of the second substrate 200 are approximately the same as the sizes in direction H and direction V of pixel sharing units 539 of the first substrate 100, and, for example, are provided in regions corresponding to pixel regions including approximately two rows and two columns. For example, in each pixel circuit 210, a selection transistor SEL and an amplification transistor AMP are arranged next to each other in direction V in one semiconductor layer 200S extending in direction V, and an FD conversion gain switch transistor FDG and a reset transistor RST are arranged next to each other in direction V in one semiconductor layer 200S extending in direction V. The one semiconductor layer 200S provided with the selection transistor SEL and the amplification transistor AMP, and the one semiconductor layer 200S provided with the FD conversion gain switch transistor FDG and the reset transistor RST are next to each other in direction H with an insulation region 212 being interposed therebetween. The insulation region 212 extends in direction V (
Here, the outline of pixel sharing units 539 of the second substrate 200 is explained with reference to
A first outer edge is an outer edge on one end (an end on the upper side on the paper surface of
The outline of the pixel sharing unit 539 of the second substrate 200 including such first, second, third and fourth outer edges is arranged such that the third and fourth outer edges are displaced toward one side in direction V relative to the first and second outer edges (in other words, offset toward one side in direction V). By using such a layout, it becomes possible to arrange both the gate of the amplification transistor AMP and the source of the FD conversion gain switch transistor FDG proximately to a pad section 120 as much as possible. Accordingly, it becomes easier to reduce the area sizes of wires connecting them, and to miniaturize the image pickup apparatus 1. Note that a VSS contact region 218 is provided between the semiconductor layer 200S including the selection transistor SEL and the amplification transistor AMP, and the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switch transistor FDG. For example, plural pixel circuits 210 have mutually the same arrangement.
The image pickup apparatus 1 having such a second substrate 200 also can provide advantages similar to those explained in the embodiment described above. The arrangement of pixel sharing units 539 of the second substrate 200 is not limited to the arrangement explained in the embodiment described above and the present modification example.
In the present modification example, the semiconductor layer 200S of the second substrate 200 extends in direction H (
For example, as explained in the embodiment described above, pixel sharing units 539 of the first substrate 100 are formed in a pixel region including two rows and two columns, and have an approximately square planar shape (
In each pixel circuit 210, a selection transistor SEL and an amplification transistor AMP are arranged next to each other in direction H, and a reset transistor RST is arranged at a position adjacent to a selection transistor SEL in direction V with an insulation region 212 being interposed therebetween (
The image pickup apparatus 1 having such a second substrate 200 also can provide advantages similar to those explained in the embodiment described above. The arrangement of pixel sharing units 539 of the second substrate 200 is not limited to the arrangement explained in the embodiment described above and the present modification example. For example, the semiconductor layer 200S explained in the embodiment and the first modification example described above may extend in direction H.
The contact sections 203 and 204 are provided in the second substrate 200, and exposed at a surface of junction with the third substrate 300. The contact sections 303 and 304 are provided in the third substrate 300, and exposed at a surface of junction with the second substrate 200. The contact section 203 is in contact with the contact section 303, and the contact section 204 is in contact with the contact section 304. That is, in this image pickup apparatus 1, the second substrate 200 and the third substrate 300 are connected by the contact sections 203, 204, 303 and 304 in addition to the contact sections 201, 202, 301 and 302.
Next, operation of the image pickup apparatus 1 is explained by using
The image pickup apparatus 1 having such contact sections 203, 204, 303 and 304 also can provide advantages similar to those explained in the embodiment described above. It is possible to change the positions, number and the like of the contact sections 303 and 304 according to the design of circuits or the like of the third substrate 300 which are the destinations of connection of wires via the contact sections.
In the transfer transistors TR, transfer gates TG include only horizontal portions TGb. Stated differently, the transfer gates TG do not have vertical portions Tga, and are provided to face the semiconductor layer 100S.
The image pickup apparatus 1 having such transfer transistors TR with the planar structure also can provide advantages similar to those explained in the embodiment described above. Further, by providing the planar transfer gates TG in the first substrate 100, it is possible to consider forming photodiodes PD to positions close to the front surface of the semiconductor layer 100S and thereby increasing the saturation signal amount (Qs), as compared with a case where vertical transfer gates TG are provided in the first substrate 100. In addition, it is also possible to consider that the method of forming the planar transfer gates TG in the first substrate 100 requires a small number of manufacturing steps, and is less likely to cause negative influence on photodiodes PD due to the manufacturing steps, as compared with the method of forming the vertical transfer gates TG in the first substrate 100.
The image pickup apparatus 1 according to the present modification example is the same as the image pickup apparatus 1 explained in the embodiment described above in that pixels 541A and pixel circuits 210 are provided in different substrates (the first substrate 100 and the second substrate 200). Because of this, the image pickup apparatus 1 according to the present modification example also can provide advantages similar to those explained in the embodiment described above.
While the pixel separating section 117 has an FTI structure penetrating the semiconductor layer 100S in the example explained in the embodiment described above (see
Specifically, in a pixel unit PU of the image pickup apparatus 1A depicted in
As depicted in
The semiconductor substrate 11 that the first substrate 10 has includes a silicon substrate, for example. Well layers WE of a first conductivity type (e.g., p type) are provided at and near parts of the front surface of the semiconductor substrate 11, and photodiodes PD of a second conductivity type (e.g., n type) are provided in regions deeper than the well layers WE. Well-contact layers with a higher p-type concentration than that of the well layers WE, and n-type floating diffusions FD are provided in the well layers WE.
The semiconductor substrate 11 is provided with element separation layers 16 that electrically separate mutually adjacent sensor pixels 12. For example, the element separation layers 16 have an STI (Shallow Trench Isolation) structure, and extend in the depth direction of the semiconductor substrate 11. In the semiconductor substrate 11, impurity diffusion layers 17 are provided between the element separation layers 16 and the photodiodes PD. For example, the impurity diffusion layers 17 have p-type layers and n-type layers extending in the thickness direction of the semiconductor substrate 11. The p-type layers are positioned on the element separation layer 16 sides, and the n-type layers are positioned on the photodiode PD sides. An insulating film 15 is provided on a front surface 11a side of the semiconductor substrate 11.
The second substrate 20 has a lower substrate 20a and an upper substrate 20b. The lower substrate 20a has a first semiconductor substrate 21. For example, the first semiconductor substrate 21 is a silicon substrate including monocrystalline silicon. On one surface 211a side of the first semiconductor substrate 21, amplification transistors AMP, and element separation layers 213 surrounding the circumference of the amplification transistors AMP are provided. Each element separation layer 213 electrically separates one amplification transistors AMP of adjacent pixel units PU and the other amplification transistor AMP. The lower substrate 20a has an insulating film 215 covering a front surface 211a of the first semiconductor substrate 21. The insulating film 215 covers the amplification transistors AMP and the element separation layers 213. In addition, the lower substrate 20a has an insulating film 217 covering the other surface 211b of the first semiconductor substrate 21. The insulating film 15 of the first substrate 10 and the insulating film 217 of the lower substrate 20a are joined together to form an interlayer dielectric film 228.
The upper substrate 20b has a second semiconductor substrate 21A. For example, the second semiconductor substrate 21A is a silicon substrate including monocrystalline silicon. On one surface 221a side of the second semiconductor substrate 21A, reset transistors RST and selection transistors SEL, and element separation layers 223 are provided. For example, each element separation layers 223 is provided between a reset transistor RST and a selection transistor SEL or between a selection transistor SEL and a well layer of the second semiconductor substrate 21A. The upper substrate 20b has an insulating film 225 that covers a front surface 221a, a backside 221b and side surfaces of the second semiconductor substrate 21A. The insulating film 215 of the lower substrate 20a and the insulating film 225 of the upper substrate 20b are joined together to form an interlayer dielectric film 226.
The image pickup apparatus 1 includes plural wires L1 to L10 that are provided in the interlayer dielectric films 226 and 228, and are electrically connected to at least one of the first substrate 10 and the second substrate 20. The wire L1 electrically connects the drain of an amplification transistor AMP and a power line VDD. The wire L2 electrically connects four floating diffusions FD included in one pixel unit PU and a gate electrode AG of the amplification transistor AMP. The wire L3 electrically connects the source of the amplification transistor AMP and the drain of a selection transistor SEL. The wire L4 electrically connects a gate electrode SG of the selection transistor SEL and a pixel driving line 23 (see
The wire L5 electrically connects the source of the selection transistor SEL and a vertical signal line 24. The wire L6 electrically connects the drain of a reset transistor RST and the power line VDD. The wire L7 electrically connects a gate electrode RG (see
In the wires L1 to L10, portions extending in the thickness direction of the stack include tungsten (W), and portions extending in a direction (e.g., the horizontal direction) orthogonal to the thickness direction of the stack include copper (Cu) or a Cu alloy including Cu as its principal component. It should be noted however that in embodiments of the present disclosure, a material included in the wires L1 to L10 is not limited to these, and another material may be included. The second substrate 20 has plural pad electrodes 227 that are connected to certain wires (e.g., the wires L1, L4 to L7, L9 and L10) in the wires L1 to L10 described above.
The third substrate 30 is arranged on a side of the second substrate 20 which is opposite to a surface that faces the first substrate 10. The third substrate 30 includes the semiconductor substrate 31, an insulating film 304 that covers a front surface 301a side of the semiconductor substrate 31, plural wires L30 provided on the front surface 301a side of the semiconductor substrate 31, and pad electrodes 305 connected to the plural wires L30. For example, the semiconductor substrate 31 is a silicon substrate including monocrystalline silicon.
The wires L30 are provided in contact holes. In the wires L30, portions extending in the thickness direction of the third substrate 30 include titanium (Ti) or cobalt (Co), and portions extending in a direction (e.g., the horizontal direction) orthogonal to the thickness direction of the third substrate 30 include Cu or a Cu alloy including Cu as its principal component. At connecting sections between the wires L30 and the semiconductor substrate 31, a silicide 39 (e.g., titanium silicide (TiSi) or cobalt silicide (CoSi2)) is formed.
For example, the plural pad electrodes 305 include Cu or a Cu alloy. In the thickness direction of the image pickup apparatus 1, the pad electrodes 305 of the third substrate 30 face, and are electrically connected with the pad electrodes 227 of the second substrates 20. For example, the pad electrodes 305 and 227 are integrated into one by being Cu—Cu-joined in a state in which they face each other. Thereby, the second substrate 20 and the third substrate 30 are electrically connected, and the strength of pasting of the second substrate 20 and the third substrate 30 is increased.
In the seventh embodiment of the present disclosure, one floating-diffusion contact may be arranged for each set of plural sensor pixels 12. For example, four mutually adjacent sensor pixels 12 may share one floating-diffusion contact. Similarly, one well contact may be arranged for each set of plural sensor pixels 12. For example, four mutually adjacent sensor pixels 12 may share one well contact. In addition, one wire L2 (floating diffusion contact) that is electrically connected with a floating diffusion FD, and one wire L10 (well contact) that is electrically connected with a well layer WE may be arranged for each of plural sensor pixels 12.
As depicted in
One wire L2 (i.e., a floating diffusion contact) is provided on a central section of each common pad electrode 102. As depicted in
In addition, as depicted in
One wire L10 (i.e., a well contact) is provided on a central section of each common pad electrode 110. As depicted in
Each wire L10 provided on a central section of a common pad electrode 110 is electrically connected to the top surface of the common pad electrode 110, the inner side surface of a through-hole provided through the lower substrate 20a, and the inner side surface of a through-hole provided through the upper substrate 20b. Thereby, a well layer WE of the semiconductor substrate 11 of the first substrate 10, and a well layer of the lower substrate 20a and a well layer of the upper substrate 20b of the second substrate 20 are connected to a reference potential (e.g., ground potential: 0 V).
The image pickup apparatus 1A according to the seventh embodiment of the present disclosure includes: the first substrate 10 provided with sensor pixels 12 that perform photoelectric conversion; and the second substrate 20 that is arranged on a front surface 12a side of the first substrate 10, and has read circuits 22 that output pixel signals based on electric charge output from the sensor pixels 12. The second substrate 20 has: the first semiconductor substrate 21 provided with amplification transistors AMP included in the read circuits 22; and the second semiconductor substrate 21A that is arranged on the front surface 211a side of the first semiconductor substrate 21, and is provided with selection transistors SEL and reset transistors RST that are included in the read circuits 22.
According to this, as compared with a case where all transistors included in read circuits 22 are arranged in one semiconductor substrate, the area size of arrangement regions of the transistors can be increased, and so the degree of freedom of the layout of the read circuits 22 is enhanced. Thereby, the area size of the gate of an amplification transistor AMP can be maximized in each pixel unit PU, and favorable noise characteristics can be realized. By maximizing the area size of each amplification transistor AMP, it becomes possible to reduce random noise generated in the image pickup apparatus 1.
In addition, the image pickup apparatus 1A further includes common pad electrode 102 and 110 that are provided on the front surface 11a side of the semiconductor substrate 11 included in the first substrate 10, and are arranged across plural mutually adjacent sensor pixels 12 (e.g., four sensor pixels). Each common pad electrode 102 is electrically connected with floating diffusions FD of four sensor pixels 12. Each common pad electrode 110 is electrically connected with well layers WE of the four sensor pixels 12. According to this, each set of four sensor pixels 12 can share a wire L2 connected to the floating diffusions FD. Each set of four sensor pixels 12 can share a wire L10 connected to the well layers WE. Thereby, the numbers of the wires L2 and L10 can be reduced, and so it is possible to reduce the area sizes sensor pixels 12, and to reduce the size of the image pickup apparatus 1A.
In addition, similarly to the seventh embodiment of the present disclosure, while amplification transistors AMP, reset transistors RST and selection transistors SEL that can be included in read circuits 22 are formed in the same semiconductor substrate 21 in the example depicted regarding the second substrate 20 of the semiconductor apparatus according to the first embodiment depicted in
In addition, plural new semiconductor substrates may be provided, and transistors of desired read circuits 22 may be provided in each of them. For example, amplification transistors AMP can be formed in the semiconductor substrate 21. Further, if an insulation layer, connecting sections and connection wires are stacked on the semiconductor substrate 21, and furthermore the semiconductor substrate 21A is stacked thereon, reset transistors RST can be formed in the semiconductor substrate 21A. If an insulation layer, connecting sections and connection wires are stacked on the semiconductor substrate 21A, and furthermore a semiconductor substrate 21B is stacked thereon, selection transistors SEL can be formed in the semiconductor substrate 21B. Transistors formed in the semiconductor substrates 21, 21A and 21B may be any transistors included in the read circuits 22.
Due to the configuration in which the second substrate 20 is provided with plural semiconductor substrates in such a manner, it is possible to reduce the area size in the semiconductor substrate 21 that is occupied by one read circuit 22. It becomes possible also to reduce the area sizes of chips if it is possible to reduce the area size of each read circuit 22 and miniaturize each transistor. In addition, it is possible to expand the area size of a desired transistor in an amplification transistor, a reset transistor and a selection transistor that can be included in a read circuit 22. In particular, a noise reduction effect can also be expected by expanding the area size of the amplification transistor.
In such a manner, in the configuration of the semiconductor apparatus according to the first to sixth embodiments also, the second substrate 20 can be provided with plural semiconductor substrates. In a case where the configuration in which the second substrate 20 is provided with plural semiconductor substrates is adopted, the structure of the semiconductor apparatus according to the first to sixth embodiments may be applied between the plural semiconductor substrates included in the second substrate. For example, the shield layer 1040 of the semiconductor apparatus according to the first and second embodiments may be arranged between the plural semiconductor substrates included in the second substrate. In addition, the light attenuation sections 1501, 1502, 1521, 1531 and 1542 of the semiconductor apparatus according to the fourth embodiment may be arranged between the plural semiconductor substrates included in the second substrate. In addition, the reflection preventing sections 1701, 1711, 1721, 1721, 1731 and 1741 of the semiconductor apparatus according to the fifth embodiment may be arranged between the plural semiconductor substrates included in the second substrate.
For example, the image pickup system 7 is electronic equipment such as an image pickup apparatus such as a digital still camera or a video camera, or a mobile terminal apparatus such as a smartphone or a tablet-type terminal. For example, the image pickup system 7 includes the image pickup apparatus 1 according to the embodiment described above and modification examples thereof, a DSP circuit 243, a frame memory 244, a display section 245, a storage section 246, an operation section 247 and a power supply section 248. In the image pickup system 7, the image pickup apparatus 1 according to the embodiment described above and modification examples thereof, the DSP circuit 243, the frame memory 244, the display section 245, the storage section 246, the operation section 247 and the power supply section 248 are connected with each other via a bus line 249.
The image pickup apparatus 1 according to the embodiment described above and modification examples thereof outputs image data according to incident light. The DSP circuit 243 is a signal processing circuit that processes signals (image data) output from the image pickup apparatus 1 according to the embodiment described above and modification examples thereof. The frame memory 244 temporarily retains framewise image data processed by the DSP circuit 243. For example, the display section 245 includes a panel-type display apparatus such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays moving images or still images picked up by the image pickup apparatus 1 according to the embodiment described above and modification examples thereof. The storage section 246 records image data of moving images or still images picked up by the image pickup apparatus 1 according to the embodiment described above and modification examples thereof on a recording medium such as a semiconductor memory or a hard disk. According to operation by a user, the operation section 247 gives an operation command for various types of functions that the image pickup system 7 has. As appropriate, the power supply section 248 supplies the image pickup apparatus 1 according to the embodiment described above and modification examples thereof, the DSP circuit 243, the frame memory 244, the display section 245, the storage section 246 and the operation section 247 with various types of power supplies to be operation power supplies of those supply targets.
Next, an image pickup procedure at the image pickup system 7 is explained.
The image pickup apparatus 1 outputs image data obtained by the image pickup to the DSP circuit 243. Here, the image data means data corresponding to all pixels of pixel signals generated on the basis of electric charge temporarily retained in floating diffusions FD. On the basis of the image data input from the image pickup apparatus 1, the DSP circuit 243 performs predetermined signal processing (e.g., a noise reduction process, etc.) (Step S104). The DSP circuit 243 makes the frame memory 244 retain the image data on which the predetermined signal processing has been performed, and the frame memory 244 causes the image data to be stored on the storage section 246 (Step S105). In such a manner, image pickup at the image pickup system 7 is performed.
In the present application example, the image pickup apparatus 1 according to the embodiment described above and modification examples thereof is applied to the image pickup system 7. Thereby, the image pickup apparatus 1 with a smaller size or higher resolution can be realized, and so the image pickup system 7 with a smaller size or higher resolution can be provided.
The technology according to the present disclosure (present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as an apparatus to be mounted on any type of mobile body such as an automobile, an electric automobile, a hybrid electric automobile, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship or a robot.
The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in
The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.
The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.
The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.
The imaging section 12031 is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section 12031 can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section 12031 may be visible light, or may be invisible light such as infrared rays or the like.
The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that images the driver. On the basis of detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.
The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.
In addition, the microcomputer 12051 can perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.
In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.
The sound/image output section 12052 transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of
In
The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the sideview mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.
Incidentally,
At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km/hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.
For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062, and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.
At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound/image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound/image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.
An example of the mobile body control system to which the technology according to the present disclosure can be applied is explained above. The technology according to the present disclosure can be applied to the imaging section 12031 in the configuration explained above. Specifically, the image pickup apparatus 1 according to the embodiment described above and modification examples thereof can be applied to the imaging section 12031. By applying the technology according to the present disclosure to the imaging section 12031, high-resolution captured images with less noise can be obtained, and so highly precise control using the captured images can be performed in the mobile body control system.
In
The endoscope 11100 includes a lens barrel 11101 having a region of a predetermined length from a distal end thereof to be inserted into a body cavity of the patient 11132, and a camera head 11102 connected to a proximal end of the lens barrel 11101. In the example depicted, the endoscope 11100 is depicted which includes as a rigid endoscope having the lens barrel 11101 of the hard type. However, the endoscope 11100 may otherwise be included as a flexible endoscope having the lens barrel 11101 of the flexible type.
The lens barrel 11101 has, at a distal end thereof, an opening in which an objective lens is fitted. A light source apparatus 11203 is connected to the endoscope 11100 such that light generated by the light source apparatus 11203 is introduced to a distal end of the lens barrel 11101 by a light guide extending in the inside of the lens barrel 11101 and is irradiated toward an observation target in a body cavity of the patient 11132 through the objective lens. It is to be noted that the endoscope 11100 may be a forward-viewing endoscope or may be an oblique-viewing endoscope or a side-viewing endoscope.
An optical system and an image pickup element are provided in the inside of the camera head 11102 such that reflected light (observation light) from the observation target is condensed on the image pickup element by the optical system. The observation light is photo-electrically converted by the image pickup element to generate an electric signal corresponding to the observation light, namely, an image signal corresponding to an observation image. The image signal is transmitted as RAW data to a CCU 11201.
The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU) or the like and integrally controls operation of the endoscope 11100 and a display apparatus 11202. Further, the CCU 11201 receives an image signal from the camera head 11102 and performs, for the image signal, various image processes for displaying an image based on the image signal such as, for example, a development process (demosaic process).
The display apparatus 11202 displays thereon an image based on an image signal, for which the image processes have been performed by the CCU 11201, under the control of the CCU 11201.
The light source apparatus 11203 includes a light source such as, for example, a light emitting diode (LED) and supplies irradiation light upon imaging of a surgical region to the endoscope 11100.
An inputting apparatus 11204 is an input interface for the endoscopic surgery system 11000. A user can perform inputting of various kinds of information or instruction inputting to the endoscopic surgery system 11000 through the inputting apparatus 11204. For example, the user would input an instruction or a like to change an image pickup condition (type of irradiation light, magnification, focal distance or the like) by the endoscope 11100.
A treatment tool controlling apparatus 11205 controls driving of the energy device 11112 for cautery or incision of a tissue, sealing of a blood vessel or the like. A pneumoperitoneum apparatus 11206 feeds gas into a body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to inflate the body cavity in order to secure the field of view of the endoscope 11100 and secure the working space for the surgeon. A recorder 11207 is an apparatus capable of recording various kinds of information relating to surgery. A printer 11208 is an apparatus capable of printing various kinds of information relating to surgery in various forms such as a text, an image or a graph.
It is to be noted that the light source apparatus 11203 which supplies irradiation light when a surgical region is to be imaged to the endoscope 11100 may include a white light source which includes, for example, an LED, a laser light source or a combination of them. Where a white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and the output timing can be controlled with a high degree of accuracy for each color (each wavelength), adjustment of the white balance of a picked up image can be performed by the light source apparatus 11203. Further, in this case, if laser beams from the respective RGB laser light sources are irradiated time-divisionally on an observation target and driving of the image pickup elements of the camera head 11102 are controlled in synchronism with the irradiation timings. Then images individually corresponding to the R, G and B colors can be also picked up time-divisionally. According to this method, a color image can be obtained even if color filters are not provided for the image pickup element.
Further, the light source apparatus 11203 may be controlled such that the intensity of light to be outputted is changed for each predetermined time. By controlling driving of the image pickup element of the camera head 11102 in synchronism with the timing of the change of the intensity of light to acquire images time-divisionally and synthesizing the images, an image of a high dynamic range free from underexposed blocked up shadows and overexposed highlights can be created.
Further, the light source apparatus 11203 may be configured to supply light of a predetermined wavelength band ready for special light observation. In special light observation, for example, by utilizing the wavelength dependency of absorption of light in a body tissue to irradiate light of a narrow band in comparison with irradiation light upon ordinary observation (namely, white light), narrow band observation (narrow band imaging) of imaging a predetermined tissue such as a blood vessel of a superficial portion of the mucous membrane or the like in a high contrast is performed. Alternatively, in special light observation, fluorescent observation for obtaining an image from fluorescent light generated by irradiation of excitation light may be performed. In fluorescent observation, it is possible to perform observation of fluorescent light from a body tissue by irradiating excitation light on the body tissue (autofluorescence observation) or to obtain a fluorescent light image by locally injecting a reagent such as indocyanine green (ICG) into a body tissue and irradiating excitation light corresponding to a fluorescent light wavelength of the reagent upon the body tissue. The light source apparatus 11203 can be configured to supply such narrow-band light and/or excitation light suitable for special light observation as described above.
The camera head 11102 includes a lens unit 11401, an image pickup unit 11402, a driving unit 11403, a communication unit 11404 and a camera head controlling unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412 and a control unit 11413. The camera head 11102 and the CCU 11201 are connected for communication to each other by a transmission cable 11400.
The lens unit 11401 is an optical system, provided at a connecting location to the lens barrel 11101. Observation light taken in from a distal end of the lens barrel 11101 is guided to the camera head 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focusing lens.
The number of image pickup elements which is included by the image pickup unit 11402 may be one (single-plate type) or a plural number (multi-plate type). Where the image pickup unit 11402 is configured as that of the multi-plate type, for example, image signals corresponding to respective R, G and B are generated by the image pickup elements, and the image signals may be synthesized to obtain a color image. The image pickup unit 11402 may also be configured so as to have a pair of image pickup elements for acquiring respective image signals for the right eye and the left eye ready for three dimensional (3D) display. If 3D display is performed, then the depth of a living body tissue in a surgical region can be comprehended more accurately by the surgeon 11131. It is to be noted that, where the image pickup unit 11402 is configured as that of stereoscopic type, a plurality of systems of lens units 11401 are provided corresponding to the individual image pickup elements.
Further, the image pickup unit 11402 may not necessarily be provided on the camera head 11102. For example, the image pickup unit 11402 may be provided immediately behind the objective lens in the inside of the lens barrel 11101.
The driving unit 11403 includes an actuator and moves the zoom lens and the focusing lens of the lens unit 11401 by a predetermined distance along an optical axis under the control of the camera head controlling unit 11405. Consequently, the magnification and the focal point of a picked up image by the image pickup unit 11402 can be adjusted suitably.
The communication unit 11404 includes a communication apparatus for transmitting and receiving various kinds of information to and from the CCU 11201. The communication unit 11404 transmits an image signal acquired from the image pickup unit 11402 as RAW data to the CCU 11201 through the transmission cable 11400.
In addition, the communication unit 11404 receives a control signal for controlling driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head controlling unit 11405. The control signal includes information relating to image pickup conditions such as, for example, information that a frame rate of a picked up image is designated, information that an exposure value upon image picking up is designated and/or information that a magnification and a focal point of a picked up image are designated.
It is to be noted that the image pickup conditions such as the frame rate, exposure value, magnification or focal point may be designated by the user or may be set automatically by the control unit 11413 of the CCU 11201 on the basis of an acquired image signal. In the latter case, an auto exposure (AE) function, an auto focus (AF) function and an auto white balance (AWB) function are incorporated in the endoscope 11100.
The camera head controlling unit 11405 controls driving of the camera head 11102 on the basis of a control signal from the CCU 11201 received through the communication unit 11404.
The communication unit 11411 includes a communication apparatus for transmitting and receiving various kinds of information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted thereto from the camera head 11102 through the transmission cable 11400.
Further, the communication unit 11411 transmits a control signal for controlling driving of the camera head 11102 to the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication or the like.
The image processing unit 11412 performs various image processes for an image signal in the form of RAW data transmitted thereto from the camera head 11102.
The control unit 11413 performs various kinds of control relating to image picking up of a surgical region or the like by the endoscope 11100 and display of a picked up image obtained by image picking up of the surgical region or the like. For example, the control unit 11413 creates a control signal for controlling driving of the camera head 11102.
Further, the control unit 11413 controls, on the basis of an image signal for which image processes have been performed by the image processing unit 11412, the display apparatus 11202 to display a picked up image in which the surgical region or the like is imaged. Thereupon, the control unit 11413 may recognize various objects in the picked up image using various image recognition technologies. For example, the control unit 11413 can recognize a surgical tool such as forceps, a particular living body region, bleeding, mist when the energy device 11112 is used and so forth by detecting the shape, color and so forth of edges of objects included in a picked up image. The control unit 11413 may cause, when it controls the display apparatus 11202 to display a picked up image, various kinds of surgery supporting information to be displayed in an overlapping manner with an image of the surgical region using a result of the recognition. Where surgery supporting information is displayed in an overlapping manner and presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery with certainty.
The transmission cable 11400 which connects the camera head 11102 and the CCU 11201 to each other is an electric signal cable ready for communication of an electric signal, an optical fiber ready for optical communication or a composite cable ready for both of electrical and optical communications.
Here, while, in the example depicted, communication is performed by wired communication using the transmission cable 11400, the communication between the camera head 11102 and the CCU 11201 may be performed by wireless communication.
An example of the endoscopic surgery system to which the technology according to the present disclosure can be applied is explained above. The technology according to the present disclosure can be suitably applied to the image pickup unit 11402 provided in the camera head 11102 of the endoscope 11100 in the configurations explained above. By applying the technology according to the present disclosure to the image pickup unit 11402, the image pickup unit 11402 with a smaller size or higher resolution can be realized, and so the endoscope 11100 with a smaller size or higher resolution can be provided.
While the present disclosure has been explained above by mentioning embodiments, and modification examples, application examples and application examples thereof, the present disclosure is not limited to the embodiments and the like described above, and a variety of modifications are possible. Note that advantages described in the present specification are presented merely for illustrative purposes. Advantages of the present disclosure are not limited to the advantages described in the present specification. The present disclosure may have advantages other than the advantages described in the present specification.
Note that the present technology can have configuration like the ones below.
(1)
A semiconductor apparatus including:
a first substrate that includes a first element layer including a first active element, a first wiring layer arranged on the first element layer, and a shield layer including an electrically conductive material arranged on the first wiring layer; and
a second substrate that includes a second element layer including a second active element arranged on the shield layer, and a second wiring layer arranged on the second element layer, in which
the first substrate and the second substrate are stacked one on another.
(2)
The semiconductor apparatus according to (1), in which the first substrate further includes a photoelectric converting section arranged under the first element layer.
(3)
The semiconductor apparatus according to (2), in which
an opening is provided through the shield layer, and
the semiconductor apparatus further includes a connection wire that penetrates the opening, and connects the photoelectric converting section or the first wiring layer and the second wiring layer.
(4)
The semiconductor apparatus according to (3), in which a part positioned at the opening of the shield layer extends coaxially with the connection wire, and along a longitudinal direction of the connection wire so as to surround an outer circumferential surface of the connection wire with an interlayer dielectric film being interposed therebetween.
(5)
The semiconductor apparatus according to any one of (1) to (4), in which a third substrate is stacked on the second substrate.
(6)
The semiconductor apparatus according to any one of (1) to (5), in which the semiconductor apparatus is included in a solid-state image pickup apparatus.
(7)
A semiconductor apparatus manufacturing method including:
forming a first wiring layer on a first element layer including a first active element;
forming a first substrate including the first element layer, the first wiring layer, and a shield layer, by forming the shield layer including an electrically conductive material on the first wiring layer;
preparing a second substrate in which a second element layer including a second active element is formed;
forming the second element layer on the shield layer by pasting, on a shield layer side of the first substrate, a second element layer side of the second substrate; and
forming a second wiring layer on the second element layer.
(8)
A semiconductor apparatus including:
a first substrate that includes a first element layer including a first active element, and a first wiring layer arranged on the first element layer; and
a second substrate that includes a second element layer including a second active element, and a second wiring layer arranged on the second element layer, in which
the first substrate and the second substrate are stacked one on another, and the semiconductor apparatus further includes, between the first substrate and the second substrate, an electromagnetic shield layer including an electrically conductive material.
(9)
The semiconductor apparatus according to (8), in which the electromagnetic shield layer is connected to a ground potential.
(10)
The semiconductor apparatus according to (8), in which the electromagnetic shield layer is arranged to cover at least the first active element when seen in a plan view.
(11)
The semiconductor apparatus according to (8), in which the electrically conductive material includes any one of tungsten, titanium, titanium nitride, carbon and polycrystalline silicon.
(12)
The semiconductor apparatus according to (11), in which the electromagnetic shield layer includes diffusion prevention layers provided on top and bottom surfaces of the electrically conductive material.
(13)
A semiconductor apparatus manufacturing method including:
forming a first substrate including a first element layer and a first wiring layer, by forming the first wiring layer on the first element layer including a first active element;
preparing a second substrate;
forming an electromagnetic shield layer including an electrically conductive material on the first substrate or the second substrate;
pasting together the first substrate and the second substrate with the electromagnetic shield layer being interposed therebetween;
forming, on the second substrate, a second element layer including a second active element; and
forming a second wiring layer on the second element layer.
(14)
A semiconductor apparatus including:
a first substrate that includes a first element layer including a first active element, a first wiring layer arranged on the first element layer, and a photoelectric converting section arranged under the first element layer; and
a second substrate that includes a second element layer including a second active element, and a second wiring layer arranged on the second element layer, in which
the first substrate and the second substrate are stacked one on another, and the semiconductor apparatus further includes, between the second active element and the photoelectric converting section, a light attenuation section including a material whose refractive index is higher than a refractive index of surrounding materials.
(15)
The semiconductor apparatus according to (14), in which the light attenuation section includes a silicon material formed in an interlayer dielectric film.
(16)
The semiconductor apparatus according to (14) or (15), in which the light attenuation section includes silicon quantum dots.
(17)
The semiconductor apparatus according to any one of (14) to (16), in which the light attenuation section includes projections formed in the second substrate.
(18)
A semiconductor apparatus manufacturing method including:
forming a first substrate including a first element layer, a first wiring layer, and a photoelectric converting section, by forming the first wiring layer on the first element layer including a first active element and forming the photoelectric converting section under the first element layer;
preparing a second substrate;
forming, in the second substrate, a light attenuation section including a material whose refractive index is higher than a refractive index of surrounding materials;
pasting together the first substrate and a light attenuation section side of the second substrate;
forming, on the second substrate, a second element layer including a second active element; and
forming a second wiring layer on the second element layer.
(19)
A semiconductor apparatus including:
a first substrate that includes a first element layer including a first active element, a first wiring layer arranged on the first element layer, and a photoelectric converting section arranged under the first element layer;
a second substrate that includes a second element layer including a second active element, and a second wiring layer arranged on the second element layer; and
a reflection preventing section that includes a material whose refractive index is lower than a refractive index of a semiconductor material included in the second substrate, in which
the first substrate and the second substrate are stacked one on another, and the reflection preventing section is arranged at least between the second active element and the photoelectric converting section.
(20)
The semiconductor apparatus according to (19), in which the reflection preventing section is arranged further in a side region of the second active element when seen in a plan view.
(21)
The semiconductor apparatus according to (18) or (19), in which the reflection preventing section includes silicon nitride.
(22)
The semiconductor apparatus according to any one of (18) to (21), further including:
between the reflection preventing section and the second active element, an intermediate film that includes a material different from a material of the reflection preventing section.
(23)
The semiconductor apparatus according to (22), in which a film thickness of the intermediate film is smaller than a film thickness of the reflection preventing section.
(24)
The semiconductor apparatus according to any one of (18) to (21), in which the reflection preventing section includes plural recesses and projections.
(25)
A semiconductor apparatus manufacturing method including:
forming a first substrate including a first element layer, a first wiring layer, and a photoelectric converting section, by forming the first wiring layer on the first element layer including a first active element and forming the photoelectric converting section under the first element layer;
preparing a second substrate;
forming, in the second substrate, a reflection preventing section including a material whose refractive index is lower than a refractive index of a semiconductor material included in the second substrate;
pasting together the first substrate and a reflection preventing section side of the second substrate;
forming, on the second substrate, a second element layer including a second active element; and
forming a second wiring layer on the second element layer.
1, 1A: Image pickup apparatus
10, 1101, 1410: First substrate
11, 21, 21A, 31, 1251, 1411, 1421, 1431: Semiconductor substrate
12, 12A: Sensor pixel
13, 1001, 2001: Pixel region
15: Column processing section
18A, 38A: DAC
20, 1102, 1420: Second substrate
20
a: Lower substrate
20
b: Upper substrate
22, 1422: Read circuit
23: Pixel driving line
24, 1008b: Vertical signal line
25, 1031, 1033, 1034, 1061, 1062, 1063, 1071, 1261, 1661: Wire
26: Low resistance region
30, 1103, 1430: Third substrate
32, 1432: Logic circuit
32A, 32B: Circuit
33, 1003: Vertical driving circuit
34, 1004: Column signal processing circuit
34A: Comparator
34B: Up/down counter
34C: Transfer switch
34D: Memory apparatus
35, 10005: Horizontal driving circuit
36: System control circuit
37: Horizontal output line
38: Reference voltage supply section
40, 1092: Color filter
41: PD
42: Well layer
43, 1012, 1612: Element separating section
44: P well layer
45: Fixed electric charge film
46, 52, 53, 57, 63, 1446, 1452, 1512: Insulation layer
47, 48, 54: Through-wire
50: Light-reception lens
51, 61, 1035, 1042, 1056, 1065, 1075, 1242, 1256, 1265, 1656, 1665: Interlayer dielectric film
55, 1066, 1067, 1266, 1311, 1666: Connection wire
56, 62, 1462: Wiring layer
58, 64: Pad electrode
59: Connecting section
102, 110: Common pad electrode
141: DSP circuit
142: Frame memory
144: Storage section
1441, PD: Photodiode
145: Operation section
146: Power supply section
147: Bus line
204: Driving section
227, 305: Pad electrode
1002: Pixel
1006: Output circuit
1008
a: Pixel driving wire
1009: Horizontal signal line
1010: Sensor layer
1011, 1051, 1081, 1611, 1651: Si substrate
1011
a: Photoelectric converting section
1020: First element layer
1021, 1221: First active element
1030, 1230, 1630: First wiring layer
1040: Shield layer
1041
a,
1041
b,
1241
a: Opening
1043, 1044: Sheath section
1050: Second element layer
1052, 1053, 1252: Second active element
1057: Support substrate
1060: Second wiring layer
1070: Third wiring layer
1080: Third element layer
1082: Third active element
1091: Flattening film
1093: Microlens
1211: Semiconductor substrate
1242: Interlayer dielectric film
1301, 1303, 1304: Diffusion prevention layer
1302: Electromagnetic shield layer
1501, 1502, 1521, 1531, 1542: Light attenuation section
1511: Semiconductor layer
1513: Resist mask
1514, 1541, 1702: Recessed section
1521
a: Projection
1701, 1711, 1721, 1721, 1731, 1741: Reflection preventing section
1723: SiN film
1732: Intermediate film
2200: Semiconductor apparatus
2201: Optical system
2202: Shutter apparatus
2203: Signal processing section
2204, 11403: Driving section
11000: Endoscopic surgery system
1101
a: Photoelectric converting section formation region
1102
a: Pixel transistor formation region
1103
a: Logic circuit formation region
11101: Lens barrel
11102: Camera head
11110: Surgical tool
11111: Pneumoperitoneum tube
11112: Energy device
11120: Supporting arm apparatus
11131: Surgeon
11132: Patient
11133: Patient bed
11200: Cart
11201: CCU
11202: Display apparatus
11203: Light source apparatus
11204: Inputting apparatus
11205: Treatment tool controlling apparatus
11206: Pneumoperitoneum apparatus
11207: Recorder
11208: Printer
11400: Transmission cable
11401: Lens unit
11402, 12031, 12101, 12102, 12104, 12105: Image pickup section
11404: Communication unit
11405: Camera head controlling unit
11411: Communication unit
11412: Image processing unit
11413: Control unit
12000: Vehicle control system
12001: Communication network
12010: Driving system control unit
12020: Body system control unit
12030, 12040: Outside-vehicle information detecting unit
12041: Driver state detecting section
12050: Integrated control unit
12051: Microcomputer
12052: Sound/image output section
12061: Audio speaker
12062: Display section
12063: Instrument panel
12100: Vehicle
12111, 12112, 12114: Imaging range
FD: Floating diffusion
FDG: FD transfer transistor
RST, T2: Reset transistor
SEL, T4: Selection transistor
T1, TR, T3: Amplification transistor
TG: Transfer gate
| Number | Date | Country | Kind |
|---|---|---|---|
| 2019-119167 | Jun 2019 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2020/025146 | 6/26/2020 | WO |
