Semiconductor constructions; and methods for providing electrically conductive material within openings.
The fabrication of integrated circuitry may involve formation of electrically conductive lines across a semiconductor substrate. A damascene process may be utilized to form such lines.
Referring to
A plurality of openings 16-18 are formed to extend into material 14. The openings may be formed by utilizing a patterned photoresist mask (not shown) to define locations of the openings, utilizing one or more etches to extend the openings into such locations, and then removing the photoresist mask to leave the structure shown in
Referring to
The material 20 may comprise titanium nitride, tantalum nitride, tantalum/ruthenium, tantalum, or titanium oxide, and may function as a barrier to block copper diffusion.
The material 22 may, for example, comprise ruthenium and nitrogen, or as another example may consist of ruthenium. The material 22 may be utilized as a stratum to adhere the subsequently deposited copper 24.
Referring to
The conductive lines 25-27 shown in
In some embodiments copper is utilized to fill narrow openings. The copper may be subjected to conditions which create enough mobility (for instance, surface diffusion) within the copper to enable the copper to flow into the openings. In particular embodiments, the openings may be narrow enough to create capillary forces which assist in bringing the copper into the openings. A balance may be struck relative to the mobility of the copper (which may be, for example, a surface transport type mechanism) so that the copper is dynamic enough to flow into the openings, but is sufficiently static (or bound) to avoid agglomeration.
Some example embodiments are described with reference to
Referring to
In some embodiments base 32 may comprise, consist essentially of, or consist of monocrystalline silicon, and may be referred to as a semiconductor substrate, or as a portion of a semiconductor substrate. The terms “semiconductive substrate,” “semiconductor construction” and “semiconductor substrate” mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Although base 32 is shown to be homogenous, the base may comprise numerous layers in some embodiments. For instance, base 32 may correspond to a semiconductor substrate containing one or more layers associated with integrated circuit fabrication. In such embodiments, such layers may correspond to one or more of refractory metal layers, barrier layers, diffusion layers, insulator layers, etc.
Openings 40-42 extend into the electrically insulative material 34. Such openings may be formed utilizing the same processing discussed above with reference to
A barrier material 36 is optionally provided within the openings to line the openings. The barrier material may comprise any of the compositions discussed above with reference to the barrier material 20 of
A liner 38 is provided over barrier material 36. The liner 38 is a metal-containing material comprising one or both of ruthenium and cobalt. In some embodiments the liner may consist essentially of, or consist of one or both of ruthenium and cobalt. In other embodiments the liner may comprise one or more transition metals alloyed with one or both of ruthenium and cobalt; and may, for example, comprise, consist essentially of, or consist of tantalum alloyed with one or both of ruthenium and cobalt. In some embodiments the liner may comprise nitrogen in combination with one or both of ruthenium and cobalt.
Referring to
The copper-containing material is preferably deposited under conditions which maintain small grain sizes (specifically, grain sizes less than or equal to about one-fourth pitch) within such material to avoid undesired surface roughness. For instance, the copper-containing material may be physical vapor deposited while maintaining a temperature of the construction 30 and the deposited copper-containing material at less than or equal to about 40° C. The physical vapor depositing may utilize any appropriate technique for sputtering copper from a target, such as, for example, utilization of a self-ionizing plasma. The physical vapor depositing may be conducted under suitable conditions, and for a suitable duration, to form a contiguous layer of copper-containing material 44 across an upper surface of construction 30.
Referring to
Although
An advantage of the processing of
Referring to
Although the example processing of
If the deposition is conducted under sufficiently high temperatures, the separate anneal of
In some embodiments the high temperature deposition/anneal (i.e., the deposition/anneal at the temperature greater than 100° C.) may be conducted to form copper directly on a liner (such as the liner 38 of
In some embodiments the deposition of the copper-containing material is conducted with intermittent plasma pulses to achieve substantially uniform filling of trenches or other cavities. Specifically, the copper-containing material is sputter-deposited at a suitable temperature of the deposited material (for instance, about 400° C.) utilizing plasma; and then the plasma is extinguished (i.e., “killed”) while maintaining suitable high temperature of the deposited copper-containing material for a sufficient duration of time (for instance, about 15 seconds) to allow the copper-containing material to surface diffuse into trenches, openings or other types of cavities. The surface diffusion can allow the copper to fill the cavities without pinching off (also referred to as “necking off”) at the tops of the cavities. The pinching off at the tops of the cavities can form voids within the cavities, and the avoidance of the pinching off can thus alleviate, or even prevent, void formation. The sputter deposition and subsequent killing of the plasma may be considered a single iteration of a process for forming copper-containing material within cavities. Multiple iterations may be conducted to fill the cavities to a desired level.
A difficulty that may occur during high-temperature deposition of copper-containing material is that the material may have large grain sizes if the deposition occurs too quickly or too slowly. Such large grain sizes may interfere with the concurrent reflow of the copper-containing material and lead to an agglomeration of the copper-containing material, rather than uniform filling of openings 40-42. In some embodiments, the copper-containing material is deposited at a rate of from about 20 angstroms/second to about 50 angstroms/second, while maintaining a temperature within a deposition chamber in a range of from about 180° C. to about 450° C.
The deposition may be conducted utilizing any suitable process. An example process comprises sputtering material from a copper-containing target. In some embodiments it may be desirable to utilize a deposition process having a relatively slow rate of sputtering; with an example process being utilization of a noble gas (for instance argon) or another inert substance to sputter copper-containing material from a sputtering target.
As discussed above with reference to
Referring to
Referring to
The nitriding of the material of the liner may convert some or all of the liner into a composition containing metal and nitrogen. In some embodiments the nitrided liner may contain nitrogen in combination with one or both of cobalt and ruthenium. In some embodiments the nitrided liner may contain nitrogen in combination with a transition metal (for instance tantalum) and one or both of cobalt and ruthenium.
Referring to
Referring to
Although the nitrogen-containing liner of
In applications in which the liner 38 comprises one or more transition metals alloyed with one or both of ruthenium and cobalt, it may be desirable to omit the barrier 36. Specifically, the liner 38 may be able to achieve both of the functions of being a barrier to copper migration, and of being a stratum for retaining a copper-containing material.
The liner 80 is directly against electrically insulative material 34. In some embodiments, electrically insulative material 34 may be a silicon oxide-containing material (for instance, silicon dioxide, BPSG, PSG, FSG, etc.), and the liner 80 may be directly against such silicon oxide-containing material.
Referring to
Referring to
The embodiments discussed above may be utilized in forming integrated circuitry. Such circuitry may be used in electronic systems, such as, for example, computers, cars, airplanes, clocks, cellular phones, etc. In some applications, the embodiments described herein may be utilized for forming integrated memory, such as flash memory.
The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The description provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings, or are rotated relative to such orientation.
When an element is referred to above as being “on” or “against” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly against” another element, there are no intervening elements present. When an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.
Number | Name | Date | Kind |
---|---|---|---|
5686760 | Miyakawa | Nov 1997 | A |
5891803 | Gardner | Apr 1999 | A |
5903053 | Iijima et al. | May 1999 | A |
6090701 | Hasunuma et al. | Jul 2000 | A |
6399512 | Blosse et al. | Jun 2002 | B1 |
6475900 | Lee | Nov 2002 | B2 |
6790774 | Fujikawa et al. | Sep 2004 | B2 |
7625815 | Yang | Dec 2009 | B2 |
8310052 | Torazawa | Nov 2012 | B2 |
8517769 | Lin et al. | Aug 2013 | B1 |
20060065969 | Antol et al. | Mar 2006 | A1 |
20060251872 | Wang et al. | Nov 2006 | A1 |
20070052096 | Su et al. | Mar 2007 | A1 |
20070292603 | Dordi et al. | Dec 2007 | A1 |
20080102599 | Yang | May 2008 | A1 |
20080132050 | Lavoie | Jun 2008 | A1 |
20080296768 | Chebiam et al. | Dec 2008 | A1 |
20090017621 | Sako et al. | Jan 2009 | A1 |
20090209101 | Shinriki et al. | Aug 2009 | A1 |
20110204518 | Arunachalam | Aug 2011 | A1 |
Number | Date | Country |
---|---|---|
1272224 | Nov 2000 | CN |
101174608 | May 2008 | CN |
201180040193.8 | Dec 2014 | CN |
08-139092 | May 1996 | JP |
08-148560 | Jun 1996 | JP |
H08-16233 | Nov 1996 | JP |
11-054612 | Feb 1999 | JP |
11-186273 | Jul 1999 | JP |
H11-186573 | Jul 1999 | JP |
H11-260620 | Sep 1999 | JP |
H 11260820 | Sep 1999 | JP |
2001-007049 | Jan 2001 | JP |
2001-007050 | Jan 2001 | JP |
2001-250829 | Sep 2001 | JP |
2001-284358 | Oct 2001 | JP |
2008-071850 | Mar 2008 | JP |
2008-141051 | Jun 2008 | JP |
2009-016520 | Jan 2009 | JP |
2009-105289 | May 2009 | JP |
2010-153487 | Jul 2010 | JP |
100128399 SR | Oct 2013 | TW |
WO 9917358 | Apr 1999 | WO |
WO 2009054266 | Apr 2009 | WO |
WO PCTUS2011045067 | Feb 2012 | WO |
WO PCTUS2011045067 | Mar 2013 | WO |
Entry |
---|
Radisic, A. et al., “Electrochemical Nucleation and Growth of Copper on Resistive Substrates”, presented at the Electrochemical Society Program on Electrodeposition of Nanoengineered Materials and Alloys on Tuesday, Oct. 9, 2007, pp. 1. |
Number | Date | Country | |
---|---|---|---|
20120043658 A1 | Feb 2012 | US |