Patent Application
20130234245
This application claims the benefit of CN application No. 201210057865.2, filed on Mar. 7, 2012, and incorporated herein by reference.
The present invention generally relates to semiconductor technology, and more particularly but not exclusively relates to a super junction semiconductor device and associated fabrication method.
Super junction structure may reduce the product of on-state resistance Ron and area A, and thus be widely utilized in small scale device.
For super junction device, since the charge at the corner of P-type or N-type pillar is imbalanced, it may be easy to cause breaking down at the corner of the super junction die, as shown in the dash line frame of
One embodiment of the present invention discloses a semiconductor device, comprising: a die; a substantially rectangle-shaped first region, and a second region in the periphery of the first region, wherein both the first region and the second region are formed on the die; trench gate MOSFET units, formed in the first region, the trench gate MOSFET units comprising a plurality of trench gate regions and a first plurality of pillars, wherein each of the first plurality of pillars separates two adjacent trench gate regions; a body region formed among the trench gate regions and the first plurality of pillars, wherein each of the first plurality of pillars has two ends; and a second plurality of pillars, formed in the second region, the second plurality of pillars extending along a corresponding side of the first region, the second plurality of pillars comprising a plurality of lateral pillars and a plurality of longitudinal pillars, wherein each of the plurality of lateral pillars and the plurality of longitudinal pillars has two ends, and wherein in a corner part of the second region, ends of the lateral pillars and ends of the longitudinal pillars are stagger and separated apart from each other.
The embodiment described above may achieve the charge balance at corner part by forming pillars with a stagger structure at the corner part and keeping a certain spacing for each pillar. With such design, the corner part avoids to be broken down firstly, so the breakdown voltage of the device is improved.
Non-limiting and non-exhaustive embodiments are described with reference to the following drawings. The drawings are not depicted to scale and only for illustration purpose.
The use of the same reference label in different drawings indicates the same or like components.
Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.
In the following text, the term “substrate” includes but not limited to a variation types of dies, e.g. monolithic integrated circuit die, sensor die, switch die and any other die with semiconductor property.
As shown in
See the right part of
In one embodiment, trench gate metal oxide semiconductor field effect transistor (MOSFET) units comprising a first plurality of trench regions 330 and a first plurality of pillars 340 are formed in the first region FR, as depicted in
In a low voltage super junction device, since the pillars in the device are relatively shallow, the charge of the P-type body region 370 could not be ignored compared with the charge of the pillars. If the spacing L2 between two adjacent pillars in termination region 320 (peripheral region PR) keeps the same as the spacing between adjacent pillars in main cell region 310 (the first region FR and the intermediate region IR), the charge may be imbalanced. Therefore, the spacing L2 between two adjacent pillars in termination region 320 is set to be smaller than the spacing L1 between two adjacent pillars in main cell region 310.
However, one skilled in the art could understand that in high voltage super junction device, the spacing L1 between two adjacent pillars in the intermediate region IR and the first region FR may be the same as the spacing L2 between two pillars in the periphery region PR.
According to the illustrated embodiment shown in
The right part of
In the edge part of the main cell region, the spacing between each end of the first plurality of pillars 340 in the first region FR and the nearest longitudinal pillar 360 in the intermediate region IR is set to be the first spacing which is substantially half of the spacing L1.
A body region 507 formed in top of the epitaxy layer 503. The semiconductor substrate 502 serves as drain region. Each of the trench gate MOSFET unit comprises a source region 508 and a shallow trench gate both formed in the body region 507, wherein the depth of the shallow trench gate is no more than half or even one third of the spacing of two adjacent deep wells, configured to lower down the density of trench gate and to reduce the gate charge Qg.
According to another embodiment, a thick oxide layer is formed on the sidewall and the bottom of the shallow trench gate, and the shallow trench gate is further filled with poly silicon layer 506.
In this embodiment, a gate oxide layer 509 and a metal layer as source electrode 510 are formed on the trench gate, which establishes an electrical connection from the gate poly silicon to outside through vias. In addition, a metal layer 501 is also formed on the backside of the semiconductor substrate as drain electrode.
In the illustrated embodiment, the body region 507 may be positioned on the deep wells 504 so that the portions of body region of adjacent trench gate MOSFET units are connected with each other. However, in another embodiment, the deep wells 504 may separate portions of body region 507 of adjacent MOSFET units. Body region 507 is formed as shallow body region and light doped. In yet another embodiment, body region 507 is formed by applying two ion implantation steps of light doping.
The super junction device according to above embodiments may significantly reduce the product of on-state resistance Ron and gate charge Qg (Ron×Qg). Besides, this improvement of super junction technology may also reduce the product of on-state resistance Ron and area A (Ron×A). Therefore the semiconductor device according to these embodiments is proper to be applied into the area of high voltage high speed circuit.
To achieve a high accuracy doping distribution, in certain embodiments, a plurality of ion implantation steps in epitaxy layer 503 are applied to form the deep wells 504. The dose of the deepest implantation step is higher than other implantation. For example, the dose of deepest implantation step is 105%-110% of the dose of other implantations. Thus more charges are provided to the bottom of the deep wells 504 for bottom charge compensation. In some embodiments, epitaxy layer 503 is formed by a plurality of epitaxial growth steps, and followed by a plurality of ion implantation steps for each epitaxial growth step, so that a relatively excellent doping distribution of deep wells 504 may be obtained. In other embodiment, the thicknesses formed in the plurality of epitaxial growth steps are different, and wherein the thickness formed in the first epitaxial growth step is larger than that in any other epitaxial layer growth steps.
Step 601: providing a die;
Step 602: forming a substantially rectangle-shaped first region, and forming a second region surrounding the periphery of the first region, wherein the second region comprises an intermediate region and a peripheral region;
Step 603: forming a plurality of trench gate regions and a first plurality of pillars of trench gate MOSFET units, wherein each of the first plurality of pillars has two ends, and wherein each of the first plurality of pillar 320 separates two adjacent trench gate regions; and
Step 604: forming a body region among the trench gate regions and the first plurality of pillars, and forming a second plurality of pillars in the second region extending along the corresponding side of the first region, and wherein the second plurality of pillars comprise a plurality of lateral pillars and a plurality of longitudinal pillars, wherein each of the plurality of lateral pillars and the plurality of longitudinal pillars has two ends, and further wherein in a corner of the second region, the ends of a plurality of lateral pillars and a plurality of longitudinal pillars are stagger and separated with each other.
According to another embodiments, in the corner of the intermediate region, each end of the lateral pillars separates apart from the nearest longitudinal pillar for a first spacing, wherein the first spacing is substantially half of a spacing L1 between the two adjacent longitudinal pillars in the intermediate region. In the corner of the peripheral region, each end of the lateral pillars separates apart from the nearest longitudinal pillar for a second spacing, wherein the second spacing is substantially half of the spacing between the two adjacent longitudinal pillars in the periphery region.
In one embodiment, the first spacing L1 is larger than the second spacing L2. In another embodiment, the first spacing L1 is the same as the second spacing L2.
In yet another embodiment, each end of the first plurality of pillars separates apart from the nearest longitudinal pillar for half of the spacing L1 between the two adjacent first plurality of pillars.
For the issue that it is difficult to achieve the charge balance between the N-type pillar and the P-type pillar at the corner part of a conventional super junction device, the embodiments described above achieve the charge balance at corner part by forming pillars with a stagger structure at the corner part and keeping a certain spacing for each pillar. With such design, the corner part avoids to be broken down firstly, so the breakdown voltage of the device is improved.
Although the specification proposes some embodiments, it should not be understood as a limitation of the present invention. By reading the above text, one skilled in relevant art may master transformations or variations other than the described embodiments. For example, the above embodiments take n-channel device as example, however, by change the conductivity types of semiconductor region, the embodiments of the present invention may also applied in p-channel device. Therefore these transformations or variations should be included in the scope of protection of the present invention.
The above description and discussion about specific embodiments of the present invention is for purposes of illustration. However, one with ordinary skill in the relevant art should know that the invention is not limited by the specific examples disclosed herein. Variations and modifications can be made on the apparatus, methods and technical design described above. Accordingly, the invention should be viewed as limited solely by the scope and spirit of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201210057865.2 | Mar 2012 | CN | national |
