Patent Application
20240057326
The present application describes embodiments generally related to a memory system, semiconductor devices and fabrication processes for the semiconductor devices.
Semiconductor manufactures developed vertical device technologies, such as three dimensional (3D) NAND flash memory technology, and the like to achieve higher data storage density without requiring smaller memory cells. In some examples, a 3D NAND memory device includes a core region and a staircase region. The core region includes a stack of alternating gate layers and insulating layers. The stack of alternating gate layers and insulating layers is used to form memory cells that are stacked vertically. The staircase region includes the respective gate layers in the stair-step form to facilitate forming contacts to the respective gate layers. The contacts are used to connect driving circuitry to the respective gate layers for controlling the stacked memory cells.
Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatingly and are formed into stair steps in a staircase region. Further, the semiconductor device includes a landing stack formed on the stair steps in the staircase region. The landing stack includes an upper layer that is etch selective to a contact isolation layer that covers the staircase region. Then, the semiconductor device includes a first contact structure on a first stair step of the stair steps. The first contact structure extends through a first contact hole in the contact isolation layer and the landing stack. The first contact structure is connected with a first gate layer (e.g., a top gate layer) of the first stair step.
In some examples, the landing stack with the upper layer extends over the stair steps. In some embodiments, the upper layer is formed of a conductive material.
According to an aspect of the disclosure, the upper layer is formed of a same material as the gate layers. In an example, the upper layer includes tungsten. In some examples, the semiconductor device includes a spacer isolation structure disposed between the upper layer and the first contact structure. The spacer isolation structure isolates the upper layer from the first contact structure. According to an aspect of the disclosure, the spacer isolation structure is disposed in a recessed space of the upper layer from a sidewall of the first contact hole.
In some examples, the landing stack further includes an isolation layer. The isolation layer includes a first portion disposed on a riser sidewall from the first stair step to a second stair step. The first portion of the isolation layer isolates the upper layer from a second gate layer of the second stair step. In some examples, the isolation layer includes a second portion disposed on a sidewall of multiple gate layers and insulating layers. The isolation layer can extend over the stair steps.
Aspects of the disclosure also provide a method for fabricating a semiconductor device. The method includes forming stair steps in a memory stack of gate layers and insulating layers in a staircase region. The gate layers and the insulating layers are stacked alternatingly. Further, the method includes forming a landing stack over the stair steps in the staircase region. The landing stack includes an etch stop layer that is etch selective to a contact isolation layer that covers the staircase region. Then, the method includes forming a first contact structure on a first stair step of the stair steps. The first contact structure extends through a first contact hole in the contact isolation layer and the landing stack. The first contact structure is connected with a first gate layer (e.g., a top gate layer) of the first stair step.
To form the stair steps, in some examples, the method includes forming the stair steps in an initial memory stack for the memory stack. The initial memory stack includes sacrificial layers corresponding to the gate layers. Then, the method includes replacing the sacrificial layers with the gate layers to form the memory stack.
To form the landing stack, in some examples, the method includes depositing an isolation layer that conforms to the stair steps in the initial memory stack, depositing a topside sacrificial layer over the isolation layer, and replacing the topside sacrificial layer with the etch stop layer at a same time as the replacing the sacrificial layers with the gate layers.
To deposit the isolation layer, in some examples, the method includes depositing a silicon dioxide film using atomic layer deposition (ALD) that covers riser sidewalls of the stair steps and sidewalls of multiple gate layers and insulating layers in the staircase region.
To form the first contact structure, in some examples, the method includes forming a spacer isolation structure between the etch stop layer and the first contact structure. The spacer isolation structure isolates the etch stop layer from the first contact structure. To form the spacer isolation structure, the method includes forming a first portion of the first contact hole in the contact isolation layer by etching the contact isolation layer with a stop in the etch stop layer, recessing the etch stop layer that forms a recessed space into the etch stop layer on a sidewall of a second portion of the first contact hole. The second portion of the first contact hole is in the etch stop layer. Then, the method includes forming the spacer isolation structure that fills the recessed space. In an example, the method includes depositing silicon dioxide using atomic layer deposition (ALD). The silicon dioxide fills the recessed space.
To form the first contact structure, the method includes forming a third portion of the first contact hole based on the first portion and the second portion of the first contact hole, and the third portion of the first contact hole exposes the first gate layer of the first stair step. Then, the method includes forming the first contact structure in the first contact hole.
Aspects of the disclosure also provide a memory system device. The memory system device includes a controller coupled to the semiconductor device to control data storage operations on the semiconductor device.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
A three dimensional (3D) NAND flash memory device includes vertical memory cell strings formed in a memory stack of gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatingly. The gate layers can correspond to gate terminals of transistors in the vertical memory cell strings. The 3D NAND flash memory device can include a staircase region to facilitate connections to the gate layers. The staircase region includes stair steps, each stair step includes a top gate layer that is one of the gate layers and each gate layer can be a top gate layer of a stair step. In some examples, contact holes are etched through a contact isolation layer to expose respective top gate layers on respective stair steps in the staircase region. Then, contact structures can be formed in the contact holes to connect respective top gate layers of the stair steps to, for example word lines of the 3D NANAD flash memory device.
According to some aspects of the disclosure, to prevent the etch process for forming the contact holes from etching through (also referred to as punch through) a top gate layer of a stair step (the punch through can cause short circuits to another gate layer under the top gate layer), thickness of the top gate layer in the stair step can be increased. The thickness increase of the top gate layers in the staircase region can be performed by a use of a topside sacrificial layer technique in a gate last technology.
In the gate last technology, an initial memory stack of sacrificial layers and insulating layers are formed, and the sacrificial layers and the insulating layers are stacked alternatingly in the initial memory stack. After channel structures are formed in the initial memory stack in an array region and stair steps are formed based on the initial memory stack in the staircase region, the sacrificial layers can be replaced with gate layers to form the memory stack. In some examples, the sacrificial layers are made of silicon nitride, and the insulating layers are made of silicon dioxide.
In some examples, to use the topside sacrificial layer technique, after the formation of the stair steps in the initial memory stack in the staircase region, top sacrificial layers (corresponding to the top gate layers) can be exposed on respective stair steps. Then, a topside sacrificial layer (e.g., an additional silicon nitride layer) can be formed over the stair steps. The topside sacrificial layer can increase the thickness of the top sacrificial layers on the stair steps. The topside sacrificial layer can be patterned to form initial landing pads respectively on the stair steps, and the initial landing pads are isolated from each other. In the process that replaces the sacrificial layers with the gate layers, the initial landing pads can be replaced by material(s) that forms the gate layers to form real landing pads on the stair steps.
In some related examples, the patterning of the topside sacrificial layer relies on a sidewall profile in the staircase region to ensure isolation of the landing pads. In a related example, a thicker top sacrificial layer can cause a gentle slope over a stair riser portion compared to a thinner top sacrificial layer that can cause a steep slope over a stair riser portion. The gentle slope may cause residues of the topside sacrificial layer between adjacent stair steps during the patterning process, the residues may be in touch with the sacrificial layers in the memory stack. During the replacement process to replace the sacrificial layers with the gate layers, the residues can be replaced by the material of the gate layers, and thus can cause leakage or even shorts between word lines. In another related example, a staircase region may include a sidewall of multiple gate layers and insulating layers (also referred to as a great wall in some examples) in the memory stack. When the profile of the sidewall is not steep enough, for example, a portion of the sidewall having a sub shoulder, the patterning process may leave residues at the sub shoulder. When the residues are replaced by the material of the gate layers, the residues can cause leakage or even shorts between word lines.
Some aspects of the disclosure provide techniques to avoid leakage or shorts between word lines. For example, a landing stack can be formed over the stair steps in the staircase region. The landing stack includes an etch stop layer. The landing stack with the etch stop layer can extend over the stair steps. The etch stop layer is etch-selective to a contact isolation layer that covers the staircase region, and can be used as a stop layer for etching contact holes in the contact isolation layer. Thus, when forming contact holes in the contact isolation layer for contact structures, the etch stop layer can prevent the eth process to punch through the top gate layers respectively on the stair steps. Further, the landing stack also includes an isolation layer that extends over the stair steps and can cover the gate layers from the sidewalls of the stair steps, and/or top surfaces of the stair steps, and can isolate the gate layers of the stair steps from the etch stop layer.
In some examples, the etch stop layer is formed of a conductive material, such as including tungsten. Then, a suitable spacer isolation structure can be formed to isolate the contact structures from the etch stop layer.
The techniques provided in the disclosure can reduce profile requirements of sidewalls in the staircase region, and improve process window for forming stair steps in the staircase region. Further, the techniques provided in the disclosure allow thicker topside sacrificial layer (corresponding to the etch stop layer) and can improve the process window for contact hole etching process.
It is noted that the semiconductor device 100 can be any suitable device, for example, memory circuits, a semiconductor die with memory circuits formed on the semiconductor die, a semiconductor wafer with multiple semiconductor dies formed on the semiconductor wafer, a semiconductor chip with a stack of semiconductor dies bonded together, a semiconductor package that includes one or more semiconductor dies or chips assembled on a package substrate, and the like.
It is also noted that, the semiconductor device 100 can include other suitable circuitry (not shown), such as logic circuitry, power circuitry, and the like that is formed on the same substrate, or other suitable substrate, and is suitably coupled with the memory cell arrays.
Generally, the semiconductor device 100 is fabricated based on a substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and/or a silicon-on-insulator (SOI) substrate. In some examples, the substrate can be in the final product of the semiconductor device 100. In some other examples, the substrate can be removed during fabrication processing and thus the substrate is not in the final product of the semiconductor device 100. For simplicity, the main surface of the substrate is referred to as an X-Y plane, and the direction perpendicular to the main surface is referred to as Z direction.
In the array region 101, vertical memory cell strings 111 are formed based on channel structures 110 in the memory stack 120. In the
It is noted that
In the array region 101, the channel structures 110 are formed in the memory stack 120. The memory stack 120 and the channel structures 110 are configured to form transistors that are stacked vertically. In some examples, a stack of transistors includes memory cells and select transistors, such as one or more bottom select transistors, one or more top select transistors and the like. In some examples, the stack of transistors can include one or more dummy select transistors. The gate terminals of the transistors in the vertical memory cell string 111 are connected to word line (WL) driving circuits, and the gate layers 123 can correspond to word lines. In some examples, one end of the stack of transistors is connected to a bit line (BL), and another end of the stack of transistors is connected to an array common source (ACS).
As shown in the
In the staircase region 102, stair steps are formed in the memory stack 120, each stair step includes a top gate layer associated with the stair step. For example, the gate layer 123(A) is the top gate layer of the stair step 1, and the gate layer 123(B) is the top gate layer of the stair step 2. The contact structures 180 (e.g., 180(A), 180(B)) are formed on the stair steps in the staircase region 102. For example, in the staircase region 102, the contact structures 180 are formed based on contact holes in a contact isolation layer 185. The contact structures 180 can connect the respective top gate layers of the stair steps with routing wires (not shown) that are connected to word line driving circuitry. For example, the contact structure 180(A) is conductively connected with the gate layer 123(A), and the contact structure 180(B) is conductively connected with the gate layer 123(B). The contact structures 180 are formed of suitable conductive materials, such as titanium (Ti), titanium nitride (TiN), tungsten and the like.
According to an aspect of the disclosure, the semiconductor device 100 includes a landing stack 170 that is formed in the staircase region 102. The landing stack 170 extends over the stair steps, for example cover the top surfaces of the stair steps and sidewalls of the stair steps. The landing stack 170 includes an upper structure such as an etch stop layer 175 that can be used as an etch stop for a contact hole etch process that forms contact holes in the contact isolation layer 185. The etch stop layer 175 can be used to protect the top gate layers from being punched through during the contact hole etch process. For example, the etch stop layer 175 is configured to be etch selective to the contact isolation layer 185. In an example, an etch rate ratio of the contact isolation layer 185 to the etch stop layer 175 in the contact hole etch process is over 10, such as 20, and the like. In some examples, the contact isolation layer 185 is formed of silicon oxide, and the etch stop layer 175 can be formed of the same material(s) as the gate layers. For example, the etch stop layer 175 includes high dielectric constant (high-k) gate insulator and tungsten.
In the
In the
In some other examples (not shown), on the top surface of a stair step, the isolation layer 171 is directly on the top gate layer to isolate etch stop layer 175 from the top gate layer.
According to some aspects of the disclosure, the staircase region 102 may include walls of multiple gate layers 123 and insulating layers 122. A wall of multiple gate layers 123 and insulating layers 122 can be referred to as a great wall. For example,
In some embodiments, the isolation layer 171 is made of silicon dioxide. In some examples, the isolation layer 171 is formed by on atomic layer deposition (ALD), and has a relatively good step coverage.
Further, according to an aspect of the disclosure, the semiconductor device 100 includes spacer isolation structures 190 (e.g., 190(A), 190(B)) that isolate the contact structures 180 from the etch stop layer 175. The spacer isolation structures 190 can include any suitable insulating material(s), such as silicon oxide, silicon dioxide, and the like. In some examples, the spacer isolation structures 190 is formed by filling the insulating material in a recessed space of the etch stop layer 175. In some examples, the spacer isolation structure 190(A) is formed in a recessed space of the etch stop layer 175 from a sidewall of the contact hole for the contact structure 180(A), and can isolate the etch stop layer 175 from the contact structure 180(A). Similarly, the spacer isolation structure 190(B) is formed in a recessed space of the etch stop layer 175 from a sidewall of the contact hole for the contact structure 180(B), and can isolate the etch stop layer 175 from the contact structure 180(B).
At S210, stair steps are formed in a memory stack in a staircase region. The memory stack includes gate layers and insulating layers stacked alternatingly. In some examples, the stair steps are formed in an initial memory stack for the memory stack. The initial memory stack includes sacrificial layers and the insulating layers stacked alternatingly. After channel structures are formed in an array region of the initial memory stack, and the stair steps are formed in a staircase region of the initial memory stack, the sacrificial layers can be replaced by the gate layers to form the memory stack.
At S220, a landing stack is formed over the stair steps. The landing stack includes an etch stop layer that is etch selective to a contact isolation layer in the staircase region. In some examples, an isolation layer is deposited over the stair steps in the initial memory stack, and a topside sacrificial layer is deposited over the isolation layer. The topside sacrificial layer can be replaced with the etch stop layer at the same time as the replacement of the sacrificial layers with the gate layers. In some examples, the isolation layer is made of silicon dioxide film that is deposited using atomic layer deposition (ALD). The silicon dioxide film by ALD has good step coverage, and can covers riser sidewalls of the stair steps and sidewalls of great walls of multiple gate layers and insulating layers in the staircase region.
At S230, contact structures to the gate layers are formed on the stair steps in the staircase region. The contact structures are formed in contact holes that extend the contact isolation layer and the landing stack. The contact structures are respectively connected with the top gate layers of the stair steps. For example, the contact structure 180(A) is formed in a contact hole that extends in the contact isolation layer 185 and the landing stack 170, is connected with the gate layer 123(A) of the stair step 1.
In an example, a first portion of the contact hole is formed in the contact isolation layer 185 by etching the contact isolation layer 185 with a stop in the etch stop layer 175. Then, the etch stop layer 175 is recessed to expose the isolation layer 171 and the form the recessed space into the etch stop layer 195. Then, spacer isolation structures can be formed from the sidewall of the contact hole. For example, a spacer isolation layer can be deposited, and the spacer isolation layer fills the recessed space and forms the spacer isolation structures 190. In some examples, the spacer isolation layer is formed by depositing silicon dioxide using atomic layer deposition (ALD).
Further, a second portion of the contact hole is formed based on the first portion of the contact hole. For example, an oxide etch process can be performed to form the second portion of the contact hole in the isolation layer and an insulating layer above the top gate layer. The second portion of the contact hole exposes the top gate layer of the stair step, such as the gate layer 123(A) of the stair step 1. Then, materials for the contact structure 180(A), such as titanium (Ti), titanium nitride (TiN), tungsten and the like can be deposited in the contact hole, and can be connected with the gate layer 123(A).
At S240, additional structure, such as routing wires, passivation, bonding structures, and the like can be formed.
It is noted that the process 200 can be suitably adapted. Step(s) in the process 200 can be modified and/or omitted. Additional step(s) can be added. Any suitable order of implementation can be used.
Due to the formation of the stair steps, the staircase region 102 includes sidewalls of sacrificial layer(s) and insulating layer(s). For example, the staircase region 102 includes a riser sidewall 127 that is transitional portion from the stair step 1 to the stair step 2. The staircase region 102 also includes a great wall 128 that is between the staircase region 102 and the array region 101.
In some examples, a contact isolation layer 185 is formed in the staircase region 102 before the replacement of the sacrificial layers. In an example, the contact isolation layer 185 is formed of silicon oxide, and can be deposited using high density plasma (HDP) deposition. The contact isolation layer 185 can be suitably planarized, for example, using chemical mechanical polishing (CMP) process. Then, the sacrificial layers, including the sacrificial layers 121 and the topside sacrificial layer 174 can be replaced by material(s) for gate layers. In some examples, trenches (not shown) can be formed in the initial memory stack 120′. Based on the trenches, the sacrificial layers 121 and the topside sacrificial layer 174 can be removed (e.g., using suitable wet etch process) to leave space for material(s) of gate layers. Further, based on the trenches, the material(s) for the gate layers (e.g., high-k isolation, tungsten and the like) can be filled into the space. Then, the trenches can be suitably filled.
It is noted that the replacement of the sacrificial layers with gate layers can also replace the topside sacrificial layer 174 with the etch stop layer 175.
As shown, a first portion 182(A) of a contact hole 181(A) is formed on the stair step 1, and the first portion 182(A) of the contact hole 181(A) may be formed with a stop in the etch stop layer 175. Similarly, a first portion 182(B) of a contact hole 181(B) is formed on the stair step 2, and the first portion 182(B) of the contact hole 181(B) may be formed with a stop in the etch stop layer 175.
It is noted that excess silicon dioxide maybe deposited on the top surface of the contact isolation layer 185, and the excess silicon dioxide can be removed for example by CMP process. It is also noted that the silicon dioxide can be deposited at the bottom of the second portion 183 of the contact holes 181, such as shown by 192.
It is noted that additional process(es), such as backend processes that form routing wires, passivation layer(s), and the like can be performed afterwards.
The memory system device 400 includes other suitable components. For example, the memory system device 400 includes an interface 401 and a master controller 402 coupled together as shown in
The interface 401 is suitably configured mechanically and electrically to connect between the memory system device 400 and a host device, and can be used to transfer data between the memory system device 400 and the host device.
The master controller 402 is configured to connect the respective semiconductor memory devices 411-414 to the interface 401 for data transfer. For example, the master controller 402 is configured to provide enable/disable signals respectively to the semiconductor memory devices 411-414 to active one or more semiconductor memory devices 411-414 for data transfer.
The master controller 402 is responsible for the completion of various instructions within the memory system device 400. For example, the master controller 402 can perform bad block management, error checking and correction, garbage collection, and the like.
The foregoing outlines features of several examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
